--- /dev/null
+++ b/arch/arm/mach-iproc/include/mach/socregs_ing_open.h
@@ -0,0 +1,775 @@
+/*
+ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef __SOCREGS_ING_OPEN_H
+#define __SOCREGS_ING_OPEN_H
+
+#define ChipcommonA_ChipID 0x18000000
+#define ChipcommonB_PWMCTL 0x18031000
+#define ChipcommonB_WDT_WDOGLOAD 0x18039000
+#define ChipcommonB_GP_DATA_IN 0x18030000
+#define ChipcommonB_GP_AUX_SEL_BASE 0x028
+#define ChipcommonB_SMBus_Config 0x18038000
+#define ChipcommonA_OTPProg 0x18000018
+#define ChipcommonA_OTPLayout 0x1800001c
+#define ChipcommonA_CoreCapabilities 0x18000004
+#define ChipcommonA_OTPStatus 0x18000010
+#define ChipcommonB_rng_CTRL 0x18033000
+#define QSPI_mspi_SPCR0_LSB 0x18027200
+#define QSPI_mspi_DISABLE_FLUSH_GEN 0x18027384
+#define QSPI_bspi_registers_REVISION_ID 0x18027000
+#define QSPI_bspi_registers_BSPI_PIO_DATA 0x1802704c
+#define QSPI_raf_START_ADDR 0x18027100
+#define QSPI_raf_interrupt_LR_fullness_reached 0x180273a0
+#define QSPI_mspi_interrupt_MSPI_halt_set_transaction_done 0x180273b8
+#define QSPI_IDM_IDM_IO_CONTROL_DIRECT 0x1811c408
+#define QSPI_raf_CURR_ADDR 0x18027120
+#define CRU_control 0x1803e000
+#define GMAC0_DEVCONTROL 0x18022000
+#define GMAC1_DEVCONTROL 0x18023000
+#define ChipcommonA_GPIOEvent_BASE 0x078
+#define ChipcommonA_GPIOInput_BASE 0x060
+#define ChipcommonB_GP_INT_CLR_BASE 0x024
+#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
+#define ChipcommonA_GPIOInput_BASE 0x060
+#define ChipcommonB_GP_INT_MSK_BASE 0x018
+#define ChipcommonA_GPIOIntMask_BASE 0x074
+#define ChipcommonB_GP_INT_MSK_BASE 0x018
+#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
+#define ChipcommonB_GP_INT_MSTAT_BASE 0x020
+#define ChipcommonA_GPIOEventIntPolarity_BASE 0x084
+#define ChipcommonA_IntStatus_BASE 0x020
+#define ChipcommonA_GPIOIntPolarity_BASE 0x070
+#define ChipcommonA_IntStatus_BASE 0x020
+#define ChipcommonB_GP_INT_DE_BASE 0x010
+#define ChipcommonB_GP_INT_EDGE_BASE 0x014
+#define ChipcommonB_GP_INT_TYPE_BASE 0x00c
+#define ChipcommonA_GPIOIntPolarity_BASE 0x070
+#define ChipcommonB_GP_AUX_SEL_BASE 0x028
+#define ChipcommonB_GP_PAD_RES_BASE 0x034
+#define ChipcommonB_GP_RES_EN_BASE 0x038
+#define ChipcommonA_ChipID 0x18000000
+#define DMAC_pl330_DS 0x18020000
+#define ChipcommonA_GPIOInput 0x18000060
+#define ChipcommonB_GP_DATA_IN 0x18030000
+#define PAXB_0_CLK_CONTROL 0x18012000
+#define PAXB_0_CONFIG_IND_ADDR_BASE 0x120
+#define ChipcommonB_MII_Management_Control 0x18032000
+#define ChipcommonB_MII_Management_Command_Data 0x18032004
+#define NAND_nand_flash_REVISION 0x18026000
+#define NAND_direct_read_rd_miss 0x18026f00
+#define NAND_IDM_IDM_IO_CONTROL_DIRECT 0x1811b408
+#define ChipcommonB_PWM_PERIOD_COUNT0_BASE 0x004
+#define ChipcommonB_PWM_PRESCALE_BASE 0x024
+#define ChipcommonB_PWM_PERIOD_COUNT1_BASE 0x00c
+#define ChipcommonB_PWM_PERIOD_COUNT2_BASE 0x014
+#define ChipcommonB_PWM_PERIOD_COUNT3_BASE 0x01c
+#define ChipcommonB_PWM_DUTYHI_COUNT0_BASE 0x008
+#define ChipcommonB_PWM_DUTYHI_COUNT1_BASE 0x010
+#define ChipcommonB_PWM_DUTYHI_COUNT2_BASE 0x018
+#define ChipcommonB_PWM_DUTYHI_COUNT3_BASE 0x020
+#define ChipcommonB_PWMCTL_BASE 0x000
+#define ChipcommonB_rng_CTRL 0x18033000
+#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
+	defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
+#define USB2_IDM_IDM_IO_CONTROL_DIRECT 0x18115408
+#define USB2D_IDM_IDM_IO_CONTROL_DIRECT 0x18116408
+#define USB2D_IDM_IDM_IO_CONTROL_DIRECT__clk_enable 0
+#define USB2D_IDM_IDM_RESET_CONTROL 0x18116800
+#define USB2D_IDM_IDM_RESET_CONTROL__RESET 0
+#endif
+#define DMU_CRU_RESET_BASE 0x200
+#define ChipcommonB_SMBus1_SMBus_Config 0x1803b000
+#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
+	 defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
+#define USB2D_ENDPNT_IN_CTRL_0 0x18042000
+#endif
+#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18107900
+#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18107904
+#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18107908
+#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810790c
+#define IHOST_S1_IDM_ERROR_LOG_ID 0x18107914
+#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810791c
+#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18107a00
+#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18108900
+#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18108904
+#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18108908
+#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810890c
+#define IHOST_S0_IDM_ERROR_LOG_ID 0x18108914
+#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810891c
+#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18108a00
+#define DDR_S1_IDM_ERROR_LOG_CONTROL 0x18109900
+#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0x18109904
+#define DDR_S1_IDM_ERROR_LOG_STATUS 0x18109908
+#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810990c
+#define DDR_S1_IDM_ERROR_LOG_ID 0x18109914
+#define DDR_S1_IDM_ERROR_LOG_FLAGS 0x1810991c
+#define DDR_S1_IDM_INTERRUPT_STATUS 0x18109a00
+#define DDR_S2_IDM_ERROR_LOG_CONTROL 0x1810a900
+#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0x1810a904
+#define DDR_S2_IDM_ERROR_LOG_STATUS 0x1810a908
+#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0x1810a90c
+#define DDR_S2_IDM_ERROR_LOG_ID 0x1810a914
+#define DDR_S2_IDM_ERROR_LOG_FLAGS 0x1810a91c
+#define DDR_S2_IDM_INTERRUPT_STATUS 0x1810aa00
+#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810b900
+#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810b904
+#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810b908
+#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810b90c
+#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x1810b914
+#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810b91c
+#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x1810ba00
+#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
+	 defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
+#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL 0x1810c900
+#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE 0x1810c904
+#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS 0x1810c908
+#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810c90c
+#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID 0x1810c914
+#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS 0x1810c91c
+#define AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS 0x1810ca00
+#endif
+#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810d900
+#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810d904
+#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810d908
+#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810d90c
+#define CMICD_S0_IDM_IDM_ERROR_LOG_ID 0x1810d914
+#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810d91c
+#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS 0x1810da00
+#define APBY_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810f900
+#define APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810f904
+#define APBY_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810f908
+#define APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810f90c
+#define APBY_S0_IDM_IDM_ERROR_LOG_ID 0x1810f914
+#define APBY_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810f91c
+#define APBY_S0_IDM_IDM_INTERRUPT_STATUS 0x1810fa00
+#define ROM_S0_IDM_ERROR_LOG_CONTROL 0x1811a900
+#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0x1811a904
+#define ROM_S0_IDM_ERROR_LOG_STATUS 0x1811a908
+#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1811a90c
+#define ROM_S0_IDM_ERROR_LOG_ID 0x1811a914
+#define ROM_S0_IDM_ERROR_LOG_FLAGS 0x1811a91c
+#define ROM_S0_IDM_INTERRUPT_STATUS 0x1811aa00
+#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0x1811b900
+#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0x1811b904
+#define NAND_IDM_IDM_ERROR_LOG_STATUS 0x1811b908
+#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811b90c
+#define NAND_IDM_IDM_ERROR_LOG_ID 0x1811b914
+#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0x1811b91c
+#define NAND_IDM_IDM_INTERRUPT_STATUS 0x1811ba00
+#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0x1811c900
+#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0x1811c904
+#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0x1811c908
+#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811c90c
+#define QSPI_IDM_IDM_ERROR_LOG_ID 0x1811c914
+#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0x1811c91c
+#define QSPI_IDM_IDM_INTERRUPT_STATUS 0x1811ca00
+#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1811d900
+#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1811d904
+#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x1811d908
+#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811d90c
+#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x1811d914
+#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811d91c
+#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x1811da00
+#define SRAM_S0_IDM_ERROR_LOG_CONTROL 0x18120900
+#define SRAM_S0_IDM_ERROR_LOG_COMPLETE 0x18120904
+#define SRAM_S0_IDM_ERROR_LOG_STATUS 0x18120908
+#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1812090c
+#define SRAM_S0_IDM_ERROR_LOG_ID 0x18120914
+#define SRAM_S0_IDM_ERROR_LOG_FLAGS 0x1812091c
+#define SRAM_S0_IDM_INTERRUPT_STATUS 0x18120a00
+#define APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18121900
+#define APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18121904
+#define APBZ_S0_IDM_IDM_ERROR_LOG_STATUS 0x18121908
+#define APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812190c
+#define APBZ_S0_IDM_IDM_ERROR_LOG_ID 0x18121914
+#define APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812191c
+#define APBZ_S0_IDM_IDM_INTERRUPT_STATUS 0x18121a00
+#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
+	 defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
+#define APBV_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18122900
+#define APBV_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18122904
+#define APBV_S0_IDM_IDM_ERROR_LOG_STATUS 0x18122908
+#define APBV_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812290c
+#define APBV_S0_IDM_IDM_ERROR_LOG_ID 0x18122914
+#define APBV_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812291c
+#define APBV_S0_IDM_IDM_INTERRUPT_STATUS 0x18122a00
+#endif
+#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x18123900
+#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x18123904
+#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x18123908
+#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1812390c
+#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x18123914
+#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x1812391c
+#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x18123a00
+#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
+	 defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
+#define AXIIC_DS_4_IDM_ERROR_LOG_CONTROL 0x18124900
+#define AXIIC_DS_4_IDM_ERROR_LOG_COMPLETE 0x18124904
+#define AXIIC_DS_4_IDM_ERROR_LOG_STATUS 0x18124908
+#define AXIIC_DS_4_IDM_ERROR_LOG_ADDR_LSB 0x1812490c
+#define AXIIC_DS_4_IDM_ERROR_LOG_ID 0x18124914
+#define AXIIC_DS_4_IDM_ERROR_LOG_FLAGS 0x1812491c
+#define AXIIC_DS_4_IDM_INTERRUPT_STATUS 0x18124a00
+#endif
+#define APBW_IDM_IDM_ERROR_LOG_CONTROL 0x18131900
+#define APBW_IDM_IDM_ERROR_LOG_COMPLETE 0x18131904
+#define APBW_IDM_IDM_ERROR_LOG_STATUS 0x18131908
+#define APBW_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813190c
+#define APBW_IDM_IDM_ERROR_LOG_ID 0x18131914
+#define APBW_IDM_IDM_ERROR_LOG_FLAGS 0x1813191c
+#define APBW_IDM_IDM_INTERRUPT_STATUS 0x18131a00
+#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18132900
+#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18132904
+#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18132908
+#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
+#define APBX_IDM_IDM_ERROR_LOG_ID 0x18132914
+#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1813291c
+#define APBX_IDM_IDM_INTERRUPT_STATUS 0x18132a00
+#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18141900
+#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18141904
+#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x18141908
+#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1814190c
+#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18141914
+#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x1814191c
+#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18141a00
+#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
+	 defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
+#define AXIIC_DS_1_IDM_ERROR_LOG_CONTROL 0x18142900
+#define AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE 0x18142904
+#define AXIIC_DS_1_IDM_ERROR_LOG_STATUS 0x18142908
+#define AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB 0x1814290c
+#define AXIIC_DS_1_IDM_ERROR_LOG_ID 0x18142914
+#define AXIIC_DS_1_IDM_ERROR_LOG_FLAGS 0x1814291c
+#define AXIIC_DS_1_IDM_INTERRUPT_STATUS 0x18142a00
+#endif
+#define DMU_PCU_IPROC_STRAPS_CAPTURED_BASE 0x028
+#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_boot_dev_R 9
+#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_type_R 5
+#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_page_R 3
+#define ChipcommonA_IntMask_BASE 0x024
+#define DMU_PCU_CRU_RESET_REASON 0x1803f014
+#define DMU_PCU_CRU_RESET_REASON__watchdog_reset 0
+#define ChipcommonA_GPIOInput 0x18000060
+#define ChipcommonA_GPIOOut 0x18000064
+#define ChipcommonA_GPIOOutEn 0x18000068
+#define AMAC_IDM0_IO_CONTROL_DIRECT 0x18110408
+#define AMAC_IDM0_IO_CONTROL_DIRECT__CLK_250_SEL 6
+#define AMAC_IDM0_IO_CONTROL_DIRECT__DIRECT_GMII_MODE 5
+#define AMAC_IDM0_IO_CONTROL_DIRECT__DEST_SYNC_MODE_EN 3
+#define AMAC_IDM1_IO_CONTROL_DIRECT 0x18111408
+#define AMAC_IDM1_IO_CONTROL_DIRECT__CLK_250_SEL 6
+#define AMAC_IDM1_IO_CONTROL_DIRECT__DIRECT_GMII_MODE 5
+#define AMAC_IDM1_IO_CONTROL_DIRECT__DEST_SYNC_MODE_EN 3
+#if defined(CONFIG_MACH_KT2)
+#define IPROC_WRAP_USBPHY_CTRL 0x1803fc20
+#define IPROC_WRAP_MISC_CONTROL__UNICORE_SERDES_CTRL_SEL 1
+#define IPROC_WRAP_MISC_CONTROL__IPROC_MDIO_SEL 3
+#define IPROC_WRAP_MISC_CONTROL 0x1803fc24
+#define IPROC_WRAP_MISC_CONTROL__UNICORE_SERDES_MDIO_SEL 2
+#define IPROC_DDR_PLL_CTRL_REGISTER_0 0x1803fc00
+#define IPROC_DDR_PLL_CTRL_REGISTER_0_BASE 0xc00
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_R 29
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_WIDTH 3
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__NDIV_RELOCK 28
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__NDIV_RELOCK_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__NDIV_RELOCK_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__FAST_LOCK 27
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__FAST_LOCK_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__FAST_LOCK_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DIV2 26
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DIV2_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DIV2_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_L 25
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_R 24
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_WIDTH 2
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_L 23
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_R 22
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_WIDTH 2
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_L 21
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_R 20
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_WIDTH 2
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__AUX_CTRL 19
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__AUX_CTRL_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__AUX_CTRL_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__TESTCLKOUT 18
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__TESTCLKOUT_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__TESTCLKOUT_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_UPDATE 17
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_UPDATE_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_UPDATE_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_L 16
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_R 14
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_WIDTH 3
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_RESET 13
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_RESET_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_RESET_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_ENABLE 12
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_ENABLE_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_ENABLE_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_L 11
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_WIDTH 12
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_RESETVALUE 0x000
+#define IPROC_DDR_PLL_CTRL_REGISTER_0_WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_0_ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_0_ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_0__ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_0_DATAMASK 0xffffffff
+#define IPROC_DDR_PLL_CTRL_REGISTER_0_RDWRMASK 0x00000000
+#define IPROC_DDR_PLL_CTRL_REGISTER_0_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_1 0x1803fc04
+#define IPROC_DDR_PLL_CTRL_REGISTER_1_BASE 0xc04
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_R 29
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_WIDTH 3
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_RESETVALUE 0x2
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_L 28
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_R 26
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_WIDTH 3
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_RESETVALUE 0x3
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_L 25
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_R 22
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_WIDTH 4
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_RESETVALUE 0x7
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_L 21
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_WIDTH 22
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_1_WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_1_ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_1_ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_1__ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_1_DATAMASK 0xffffffff
+#define IPROC_DDR_PLL_CTRL_REGISTER_1_RDWRMASK 0x00000000
+#define IPROC_DDR_PLL_CTRL_REGISTER_1_RESETVALUE 0x4dc00000
+#define IPROC_DDR_PLL_CTRL_REGISTER_2 0x1803fc08
+#define IPROC_DDR_PLL_CTRL_REGISTER_2_BASE 0xc08
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_R 29
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_WIDTH 3
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_RESETVALUE 0x1
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_PHASE_EN 28
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_PHASE_EN_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_PHASE_EN_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_L 27
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_R 16
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_WIDTH 12
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_RESETVALUE 0x000
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_L 15
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_WIDTH 16
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_RESETVALUE 0x0000
+#define IPROC_DDR_PLL_CTRL_REGISTER_2_WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_2_ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_2_ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_2__ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_2_DATAMASK 0xffffffff
+#define IPROC_DDR_PLL_CTRL_REGISTER_2_RDWRMASK 0x00000000
+#define IPROC_DDR_PLL_CTRL_REGISTER_2_RESETVALUE 0x20000000
+#define IPROC_DDR_PLL_CTRL_REGISTER_3 0x1803fc0c
+#define IPROC_DDR_PLL_CTRL_REGISTER_3_BASE 0xc0c
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__SSC_MODE 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__SSC_MODE_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__SSC_MODE_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__PHASE8_EN 30
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__PHASE8_EN_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__PHASE8_EN_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_L 29
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_R 10
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_WIDTH 20
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_RESETVALUE 0x00000
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_L 9
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_WIDTH 10
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_RESETVALUE 0x80
+#define IPROC_DDR_PLL_CTRL_REGISTER_3_WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_3_ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_3_ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_3__ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_3_DATAMASK 0xffffffff
+#define IPROC_DDR_PLL_CTRL_REGISTER_3_RDWRMASK 0x00000000
+#define IPROC_DDR_PLL_CTRL_REGISTER_3_RESETVALUE 0x80
+#define IPROC_DDR_PLL_CTRL_REGISTER_4 0x1803fc10
+#define IPROC_DDR_PLL_CTRL_REGISTER_4_BASE 0xc10
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_R 29
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_WIDTH 3
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__PWRDWN 28
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__PWRDWN_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__PWRDWN_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_L 27
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_R 24
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_WIDTH 4
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_EN 23
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_EN_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_EN_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_SEL 22
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_SEL_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_SEL_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__D2C_HYST_EN 21
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__D2C_HYST_EN_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__D2C_HYST_EN_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__BYPASS_POR 20
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__BYPASS_POR_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__BYPASS_POR_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_L 19
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_R 14
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_WIDTH 6
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_L 13
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_R 8
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_WIDTH 6
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_L 7
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_WIDTH 8
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_RESETVALUE 0x08
+#define IPROC_DDR_PLL_CTRL_REGISTER_4_WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_4_ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_4_ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_4__ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_4_DATAMASK 0xffffffff
+#define IPROC_DDR_PLL_CTRL_REGISTER_4_RDWRMASK 0x00000000
+#define IPROC_DDR_PLL_CTRL_REGISTER_4_RESETVALUE 0x8
+#define IPROC_DDR_PLL_CTRL_REGISTER_5 0x1803fc14
+#define IPROC_DDR_PLL_CTRL_REGISTER_5_BASE 0xc14
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_R 17
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_WIDTH 15
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_SW_OVWR 16
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_SW_OVWR_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_SW_OVWR_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT1_EN 15
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT1_EN_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT1_EN_RESETVALUE 0x1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT0_EN 14
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT0_EN_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT0_EN_RESETVALUE 0x1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_IN_SEL 13
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_IN_SEL_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_IN_SEL_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_POST_RESETB 12
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_POST_RESETB_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_POST_RESETB_RESETVALUE 0x1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_RESETB 11
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_RESETB_WIDTH 1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_RESETB_RESETVALUE 0x1
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_L 10
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_R 8
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_WIDTH 3
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_RESETVALUE 0x0
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_L 7
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_WIDTH 8
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_RESETVALUE 0x64
+#define IPROC_DDR_PLL_CTRL_REGISTER_5_WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__WIDTH 32
+#define IPROC_DDR_PLL_CTRL_REGISTER_5_ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_5_ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__ALL_L 31
+#define IPROC_DDR_PLL_CTRL_REGISTER_5__ALL_R 0
+#define IPROC_DDR_PLL_CTRL_REGISTER_5_DATAMASK 0xffffffff
+#define IPROC_DDR_PLL_CTRL_REGISTER_5_RDWRMASK 0x00000000
+#define IPROC_DDR_PLL_CTRL_REGISTER_5_RESETVALUE 0xd864
+#define IPROC_DDR_PLL_STATUS 0x1803fc18
+#define IPROC_DDR_PLL_STATUS_BASE 0xc18
+#define IPROC_DDR_PLL_STATUS__RESERVED_L 31
+#define IPROC_DDR_PLL_STATUS__RESERVED_R 14
+#define IPROC_DDR_PLL_STATUS__RESERVED_WIDTH 18
+#define IPROC_DDR_PLL_STATUS__RESERVED_RESETVALUE 0x0
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_LOST 13
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_LOST_WIDTH 1
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_LOST_RESETVALUE 0x0
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK 12
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_WIDTH 1
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_RESETVALUE 0x0
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_L 11
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_R 0
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_WIDTH 12
+#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_RESETVALUE 0x000
+#define IPROC_DDR_PLL_STATUS_WIDTH 32
+#define IPROC_DDR_PLL_STATUS__WIDTH 32
+#define IPROC_DDR_PLL_STATUS_ALL_L 31
+#define IPROC_DDR_PLL_STATUS_ALL_R 0
+#define IPROC_DDR_PLL_STATUS__ALL_L 31
+#define IPROC_DDR_PLL_STATUS__ALL_R 0
+#define IPROC_DDR_PLL_STATUS_DATAMASK 0xffffffff
+#define IPROC_DDR_PLL_STATUS_RDWRMASK 0x00000000
+#define IPROC_DDR_PLL_STATUS_RESETVALUE 0x0
+#endif
+#if (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
+	 defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
+#define IPROC_WRAP_USBPHY_CTRL 0x1803fc34
+#define IPROC_WRAP_GEN_PLL_STATUS__GEN_PLL_LOCK 0
+#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_R 0
+#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_WIDTH 10
+#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_R 10
+#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_WIDTH 3
+#define IPROC_WRAP_GEN_PLL_CTRL1__CH0_MDIV_R 13
+#define IPROC_WRAP_GEN_PLL_CTRL1__CH1_MDIV_R 21
+#define IPROC_WRAP_GEN_PLL_CTRL2__CH2_MDIV_R 0
+#define IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R 8
+#define IPROC_WRAP_GEN_PLL_CTRL2__CH4_MDIV_R 16
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0 0x1803fc1c
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_BASE 0xc1c
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_R 24
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_WIDTH 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_RESETVALUE 0x18
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_L 23
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_R 16
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_WIDTH 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_RESETVALUE 0x0f
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_L 15
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_R 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_WIDTH 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_RESETVALUE 0x64
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_L 7
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_WIDTH 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_RESETVALUE 0x1e
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_DATAMASK 0xffffffff
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_RDWRMASK 0x00000000
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_RESETVALUE 0x180f641e
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1 0x1803fc20
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_BASE 0xc20
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_R 28
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_WIDTH 4
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR 27
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB 26
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB_RESETVALUE 0x1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB 25
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB_RESETVALUE 0x1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_L 24
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_R 22
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_WIDTH 3
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_RESETVALUE 0x1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_L 21
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_R 18
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_WIDTH 4
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_RESETVALUE 0x8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_L 17
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_R 15
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_WIDTH 3
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_RESETVALUE 0x1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_L 14
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_R 12
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_WIDTH 3
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_RESETVALUE 0x4
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_L 11
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_R 6
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_WIDTH 6
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_L 5
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_WIDTH 6
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_DATAMASK 0xffffffff
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_RDWRMASK 0x00000000
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_RESETVALUE 0x660c000
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2 0x1803fc24
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_BASE 0xc24
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_R 28
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_WIDTH 4
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_L 27
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_R 20
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_WIDTH 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_RESETVALUE 0x00
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_L 19
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_R 17
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_WIDTH 3
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_L 16
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_R 14
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_WIDTH 3
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_L 13
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_R 11
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_WIDTH 3
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_L 10
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_R 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_WIDTH 3
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_L 7
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_WIDTH 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_RESETVALUE 0x0f
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_DATAMASK 0xffffffff
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_RDWRMASK 0x00000000
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_RESETVALUE 0xf
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3 0x1803fc28
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_BASE 0xc28
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_R 30
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_WIDTH 2
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT2_EN 29
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT2_EN_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT2_EN_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_2ED_OUT_EN 28
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_2ED_OUT_EN_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_2ED_OUT_EN_RESETVALUE 0x1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_L 27
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_R 26
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_WIDTH 2
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_RESETVALUE 0x1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_L 25
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_R 24
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_WIDTH 2
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_RESETVALUE 0x1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT_EN 23
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT_EN_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT_EN_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_OUTPUT_EN 22
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_OUTPUT_EN_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_OUTPUT_EN_RESETVALUE 0x1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_BYP_EN 21
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_BYP_EN_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_BYP_EN_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__VCOdiv2 20
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__VCOdiv2_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__VCOdiv2_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__AUX_CTRL 19
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__AUX_CTRL_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__AUX_CTRL_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__REFCLKOUT 18
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__REFCLKOUT_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__REFCLKOUT_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_UPDATE 17
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_UPDATE_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_UPDATE_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_L 16
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_R 14
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_WIDTH 3
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_RESET 13
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_RESET_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_RESET_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_ENABLE 12
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_ENABLE_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_ENABLE_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_L 11
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_WIDTH 12
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_RESETVALUE 0x000
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_DATAMASK 0xffffffff
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_RDWRMASK 0x00000000
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_RESETVALUE 0x15400000
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4 0x1803fc2c
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_BASE 0xc2c
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_R 28
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_WIDTH 4
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_L 27
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_R 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_WIDTH 20
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_RESETVALUE 0x00000
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_L 7
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_WIDTH 8
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_RESETVALUE 0x78
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_DATAMASK 0xffffffff
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_RDWRMASK 0x00000000
+#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_RESETVALUE 0x78
+#define IPROC_WRAP_IPROC_XGPLL_STATUS 0x1803fc30
+#define IPROC_WRAP_IPROC_XGPLL_STATUS_BASE 0xc30
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK 31
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK_WIDTH 1
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_L 30
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_R 0
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_WIDTH 31
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_RESETVALUE 0x0
+#define IPROC_WRAP_IPROC_XGPLL_STATUS_WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__WIDTH 32
+#define IPROC_WRAP_IPROC_XGPLL_STATUS_ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_STATUS_ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__ALL_L 31
+#define IPROC_WRAP_IPROC_XGPLL_STATUS__ALL_R 0
+#define IPROC_WRAP_IPROC_XGPLL_STATUS_DATAMASK 0xffffffff
+#define IPROC_WRAP_IPROC_XGPLL_STATUS_RDWRMASK 0x00000000
+#define IPROC_WRAP_IPROC_XGPLL_STATUS_RESETVALUE 0x0
+#if defined(CONFIG_MACH_HX4) || \
+	defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
+#define IPROC_WRAP_MISC_CONTROL__QUAD_SERDES_MDIO_SEL 3
+#define IPROC_WRAP_MISC_CONTROL__QUAD_SERDES_CTRL_SEL 2
+#define IPROC_WRAP_MISC_CONTROL__IPROC_MDIO_SEL 4
+#endif
+#define IPROC_WRAP_MISC_CONTROL 0x1803fc3c
+#endif
+
+#endif /* __SOCREGS_ING_OPEN_H */
diff --git a/arch/arm/mach-iproc/include/mach/socregs_ns_open.h b/arch/arm/mach-iproc/include/mach/socregs_ns_open.h
new file mode 100644
index 0000000..8f3d2eb
