--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -87,7 +87,26 @@ ENTRY(stext)
 
 	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
 						@ and irqs disabled
-	mrc	p15, 0, r9, c0, c0		@ get processor id
+#ifdef CONFIG_ARCH_IPROC
+
+#ifndef CONFIG_MACH_IPROC_P7
+#ifndef CONFIG_MACH_CYGNUS
+    /*
+     * fixup the vector table so that the secondary CPU does
+     * not start executing kernel instructions until we've
+     * patched its jump address during wakeup_secondary()
+     */
+    ldr r3,=0xffff002c
+    ldr r4,=0xffff0000
+    str r3, [r4, #0x400]
+#endif
+#endif
+
+    /* Make sure the cache is invalidated and MMU is disabled */
+    bl  __iproc_head_fixup
+#endif /* CONFIG_ARCH_IPROC */
+
+    mrc	p15, 0, r9, c0, c0		@ get processor id
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
  THUMB( it	eq )		@ force fixup-able long branch encoding
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1e9be5d..7ab2fa7 100644
