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7 Commits

Author SHA1 Message Date
Onn
4bb3dc565c Remove debug print 2025-11-17 16:22:46 +07:00
Onn
548eda5ccf My mistake 2025-11-17 16:22:02 +07:00
Onn
2bb8497a31 Correct quirk for C442 chipset 2025-11-17 15:52:07 +07:00
Hoang Hong Quan
39ac1c4a51 Add support for Intel Nehalem and Westmere architectures 2025-02-19 15:13:37 +07:00
Hoang Hong Quan
52766d2f03 Add support for Intel Core Ultra Series 2 processors 2025-02-12 19:18:03 +07:00
Hoang Hong Quan
a0d3fdf469 Update CPU generation and motherboard chipset info 2024-10-08 01:41:16 +07:00
Hoang Hong Quan
72a124244b Initial commit 2024-07-26 18:09:54 +07:00