From 0183e3cc7ffc507bbb3fc7d4165b3b13a90b813e Mon Sep 17 00:00:00 2001 From: Kyoung Kim Date: Fri, 24 Jul 2015 16:36:16 -0700 Subject: [PATCH] mec1322: keep 32KHz on for ROSC accuracy 32KHz osc is necessary to key ROSC in +-2% accuracy. If 32KHz osc is off/on during the heavy sleep, UART produces garbage characters to Tx port until its clock to be stabilized. BUG=none TEST=Cyan BRANCH=none Change-Id: Ie045b9f152eb7dc8d888a2840babefac68081cef Signed-off-by: Kyoung Kim Reviewed-on: https://chromium-review.googlesource.com/288421 Reviewed-by: Shawn N Reviewed-by: Alec Berg Commit-Queue: Divya Jyothi Tested-by: Divya Jyothi --- chip/mec1322/clock.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index 71c10e481c..9dda1e4228 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -164,9 +164,6 @@ static void prepare_for_deep_sleep(void) CPU_NVIC_ST_CTRL &= ~ST_ENABLE; CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG; - /* Disable 32KHz clock */ - MEC1322_VBAT_CE &= ~0x2; - /* Disable JTAG */ MEC1322_EC_JTAG_EN &= ~1; /* Power down ADC VREF, ADC_VREF overrides ADC_CTRL. */ @@ -212,9 +209,6 @@ static void resume_from_deep_sleep(void) /* Enable watchdog */ MEC1322_WDG_CTL |= 1; - /* Enable 32KHz clock */ - MEC1322_VBAT_CE |= 0x2; - MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0; MEC1322_PCR_CHIP_SLP_EN &= ~0x3; MEC1322_PCR_EC_SLP_EN &= ~0xe0700ff7; @@ -223,7 +217,7 @@ static void resume_from_deep_sleep(void) MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */ - /* Enable UART */ + /* Enable LPC */ MEC1322_LPC_ACT |= 1; MEC1322_LPC_CLK_CTRL &= ~0x2;