From 16f4c65daf528de399bf622d0aefcadc19238544 Mon Sep 17 00:00:00 2001 From: CHLin Date: Tue, 7 Nov 2017 10:50:16 +0800 Subject: [PATCH] npcx: fixed the assembly code of deep idle bypass The original assembly code of deep sleep bypass will cause build error if both CONFIG_LOW_POWER_IDLE and CONFIG_LTO are defined when buildiing board glkrvp/zoombini. This CL fixed it by change the bypass assembly code from: asm ("push {r0-r5}\n" "ldr r0, =0x100A8000\n" "wfi\n" "ldm r0, {r0-r5}\n" "pop {r0-r5}\n" "isb\n" ); to: asm ("push {r0-r5}\n" "wfi\n" "ldm %0, {r0-r5}\n" "pop {r0-r5}\n" "isb\n" :: "r" (0x100A8000) ); BRANCH=none BUG=none TEST=No build errors for "make buildall". TEST=build zoombini/glkrvp with CONFIG_LOW_POWER_IDLE and CONFIG_LTO, no build errors. TEST=build npcx7_evb/npcx_evb and do stress test for deep idle->wakeup on EVB, no symptom observed. Change-Id: I90b13b4baf418e3f4b3234d4811e3978b6436aac Signed-off-by: Vincent Palatin Signed-off-by: CHLin Reviewed-on: https://chromium-review.googlesource.com/756535 Commit-Ready: CH Lin Tested-by: CH Lin --- chip/npcx/clock.c | 10 ++++------ core/cortex-m/task.c | 5 ++--- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index 8021f3c4d6..e2f071fea8 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -342,11 +342,10 @@ void __idle(void) * Workaround: Apply the same bypass of idle. */ asm ("push {r0-r5}\n" - "ldr r0, =0x100A8000\n" "wfi\n" - "ldm r0, {r0-r5}\n" + "ldm %0, {r0-r5}\n" "pop {r0-r5}\n" - "isb\n" + "isb\n" :: "r" (0x100A8000) ); /* Get time delay cause of deep idle */ @@ -393,11 +392,10 @@ void __idle(void) * Please see task.c for more detail */ asm ("push {r0-r5}\n" - "ldr r0, =0x100A8000\n" "wfi\n" - "ldm r0, {r0-r5}\n" + "ldm %0, {r0-r5}\n" "pop {r0-r5}\n" - "isb\n" + "isb\n" :: "r" (0x100A8000) ); } diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 67785d4366..bab5310245 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -90,12 +90,11 @@ void __idle(void) asm ( "cpsid i\n" /* Disable interrupt */ "push {r0-r5}\n" /* Save needed registers */ - "ldr r0, =0x100A8000\n" /* Set r0 to a valid RAM addr */ "wfi\n" /* Wait for int to enter idle */ - "ldm r0, {r0-r5}\n" /* Add a delay after WFI */ + "ldm %0, {r0-r5}\n" /* Add a delay after WFI */ "pop {r0-r5}\n" /* Restore regs before enabling ints */ "isb\n" /* Flush the cpu pipeline */ - "cpsie i\n" /* Enable interrupts */ + "cpsie i\n" :: "r" (0x100A8000) /* Enable interrupts */ ); #else /*