From c6bc071020baebc660fc94390b50bc240e34c0a3 Mon Sep 17 00:00:00 2001 From: Dan Handley Date: Wed, 14 May 2014 12:38:32 +0100 Subject: [PATCH 1/8] Remove extern keyword from function declarations Function declarations implicitly have external linkage so do not need the extern keyword. Change-Id: Ia0549786796d8bf5956487e8996450a0b3d79f32 --- bl1/bl1_private.h | 4 +- bl2/bl2_private.h | 2 +- include/bl1/bl1.h | 4 +- include/bl2/bl2.h | 16 +- include/bl31/bl31.h | 21 +- include/bl31/context_mgmt.h | 40 +-- include/bl31/interrupt_mgmt.h | 12 +- include/bl31/runtime_svc.h | 6 +- include/bl31/services/psci.h | 54 ++-- include/bl32/bl32.h | 6 +- include/bl32/payloads/tsp.h | 64 ++--- include/common/bl_common.h | 34 +-- include/common/debug.h | 6 +- include/drivers/arm/cci400.h | 4 +- include/drivers/arm/gic_v2.h | 70 +++--- include/drivers/arm/gic_v3.h | 14 +- include/lib/aarch64/arch_helpers.h | 358 +++++++++++++-------------- include/lib/aarch64/xlat_tables.h | 8 +- include/lib/mmio.h | 12 +- lib/semihosting/semihosting.c | 4 +- plat/fvp/drivers/pwrc/fvp_pwrc.h | 16 +- plat/fvp/platform.h | 140 +++++------ services/spd/tspd/tspd_private.h | 10 +- services/std_svc/psci/psci_private.h | 90 +++---- 24 files changed, 496 insertions(+), 499 deletions(-) diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h index b2ebf21499..b54bf6ba17 100644 --- a/bl1/bl1_private.h +++ b/bl1/bl1_private.h @@ -34,7 +34,7 @@ /****************************************** * Function prototypes *****************************************/ -extern void bl1_arch_setup(void); -extern void bl1_arch_next_el_setup(void); +void bl1_arch_setup(void); +void bl1_arch_next_el_setup(void); #endif /* __BL1_PRIVATE_H__ */ diff --git a/bl2/bl2_private.h b/bl2/bl2_private.h index 2a66d42c53..022d1e93b1 100644 --- a/bl2/bl2_private.h +++ b/bl2/bl2_private.h @@ -34,6 +34,6 @@ /****************************************** * Function prototypes *****************************************/ -extern void bl2_arch_setup(void); +void bl2_arch_setup(void); #endif /* __BL2_PRIVATE_H__ */ diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h index d8afae460f..b1bbf244f9 100644 --- a/include/bl1/bl1.h +++ b/include/bl1/bl1.h @@ -40,7 +40,7 @@ struct meminfo; /****************************************** * Function prototypes *****************************************/ -extern void bl1_platform_setup(void); -extern struct meminfo *bl1_plat_sec_mem_layout(void); +void bl1_platform_setup(void); +struct meminfo *bl1_plat_sec_mem_layout(void); #endif /* __BL1_H__ */ diff --git a/include/bl2/bl2.h b/include/bl2/bl2.h index 4cd3cee4a2..b028faa0f8 100644 --- a/include/bl2/bl2.h +++ b/include/bl2/bl2.h @@ -40,34 +40,32 @@ extern unsigned long long bl2_entrypoint; * Forward declarations *****************************************/ struct meminfo; -struct bl31_args; +struct bl31_params; +struct entry_point_info; /****************************************** * Function prototypes *****************************************/ -extern void bl2_platform_setup(void); -extern struct meminfo *bl2_plat_sec_mem_layout(void); +void bl2_platform_setup(void); +struct meminfo *bl2_plat_sec_mem_layout(void); /******************************************************************************* * This function returns a pointer to the shared memory that the platform has * kept aside to pass trusted firmware related information that BL3-1 * could need ******************************************************************************/ -extern struct bl31_params *bl2_plat_get_bl31_params(void); - +struct bl31_params *bl2_plat_get_bl31_params(void); /******************************************************************************* * This function returns a pointer to the shared memory that the platform * has kept to point to entry point information of BL31 to BL2 ******************************************************************************/ -extern struct entry_point_info *bl2_plat_get_bl31_ep_info(void); - +struct entry_point_info *bl2_plat_get_bl31_ep_info(void); /************************************************************************ * This function flushes to main memory all the params that are * passed to BL3-1 **************************************************************************/ -extern void bl2_plat_flush_bl31_params(void); - +void bl2_plat_flush_bl31_params(void); #endif /* __BL2_H__ */ diff --git a/include/bl31/bl31.h b/include/bl31/bl31.h index e77c554de7..744dcc29dc 100644 --- a/include/bl31/bl31.h +++ b/include/bl31/bl31.h @@ -41,22 +41,21 @@ extern unsigned long bl31_entrypoint; /****************************************** * Forward declarations *****************************************/ -struct meminfo; struct entry_point_info; struct bl31_parms; /******************************************************************************* * Function prototypes ******************************************************************************/ -extern void bl31_arch_setup(void); -extern void bl31_next_el_arch_setup(uint32_t security_state); -extern void bl31_set_next_image_type(uint32_t type); -extern uint32_t bl31_get_next_image_type(void); -extern void bl31_prepare_next_image_entry(); -extern struct entry_point_info *bl31_get_next_image_info(uint32_t type); -extern void bl31_early_platform_setup(struct bl31_params *from_bl2, - void *plat_params_from_bl2); -extern void bl31_platform_setup(void); -extern void bl31_register_bl32_init(int32_t (*)(void)); +void bl31_arch_setup(void); +void bl31_next_el_arch_setup(uint32_t security_state); +void bl31_set_next_image_type(uint32_t type); +uint32_t bl31_get_next_image_type(void); +void bl31_prepare_next_image_entry(); +struct entry_point_info *bl31_get_next_image_info(uint32_t type); +void bl31_early_platform_setup(struct bl31_params *from_bl2, + void *plat_params_from_bl2); +void bl31_platform_setup(void); +void bl31_register_bl32_init(int32_t (*)(void)); #endif /* __BL31_H__ */ diff --git a/include/bl31/context_mgmt.h b/include/bl31/context_mgmt.h index ad9d785650..ce4f7a86d6 100644 --- a/include/bl31/context_mgmt.h +++ b/include/bl31/context_mgmt.h @@ -36,24 +36,24 @@ /******************************************************************************* * Function & variable prototypes ******************************************************************************/ -extern void cm_init(void); -extern void *cm_get_context(uint64_t mpidr, uint32_t security_state); -extern void cm_set_context(uint64_t mpidr, - void *context, - uint32_t security_state); -extern void cm_el3_sysregs_context_save(uint32_t security_state); -extern void cm_el3_sysregs_context_restore(uint32_t security_state); -extern void cm_el1_sysregs_context_save(uint32_t security_state); -extern void cm_el1_sysregs_context_restore(uint32_t security_state); -extern void cm_set_el3_eret_context(uint32_t security_state, uint64_t entrypoint, - uint32_t spsr, uint32_t scr); -extern void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint); -extern void cm_write_scr_el3_bit(uint32_t security_state, - uint32_t bit_pos, - uint32_t value); -extern void cm_set_next_eret_context(uint32_t security_state); -extern void cm_init_pcpu_ptr_cache(); -extern void cm_set_pcpu_ptr_cache(const void *pcpu_ptr); -extern void *cm_get_pcpu_ptr_cache(void); -extern uint32_t cm_get_scr_el3(uint32_t security_state); +void cm_init(void); +void *cm_get_context(uint64_t mpidr, uint32_t security_state); +void cm_set_context(uint64_t mpidr, + void *context, + uint32_t security_state); +void cm_el3_sysregs_context_save(uint32_t security_state); +void cm_el3_sysregs_context_restore(uint32_t security_state); +void cm_el1_sysregs_context_save(uint32_t security_state); +void cm_el1_sysregs_context_restore(uint32_t security_state); +void cm_set_el3_eret_context(uint32_t security_state, uint64_t entrypoint, + uint32_t spsr, uint32_t scr); +void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint); +void cm_write_scr_el3_bit(uint32_t security_state, + uint32_t bit_pos, + uint32_t value); +void cm_set_next_eret_context(uint32_t security_state); +void cm_init_pcpu_ptr_cache(); +void cm_set_pcpu_ptr_cache(const void *pcpu_ptr); +void *cm_get_pcpu_ptr_cache(void); +uint32_t cm_get_scr_el3(uint32_t security_state); #endif /* __CM_H__ */ diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index 0b24f39a54..3a2c00c2dd 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -117,12 +117,12 @@ typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, /******************************************************************************* * Function & variable prototypes ******************************************************************************/ -extern uint32_t get_scr_el3_from_routing_model(uint32_t security_state); -extern int32_t set_routing_model(uint32_t type, uint32_t flags); -extern int32_t register_interrupt_type_handler(uint32_t type, - interrupt_type_handler_t handler, - uint32_t flags); -extern interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type); +uint32_t get_scr_el3_from_routing_model(uint32_t security_state); +int32_t set_routing_model(uint32_t type, uint32_t flags); +int32_t register_interrupt_type_handler(uint32_t type, + interrupt_type_handler_t handler, + uint32_t flags); +interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type); #endif /*__ASSEMBLY__*/ #endif /* __INTERRUPT_MGMT_H__ */ diff --git a/include/bl31/runtime_svc.h b/include/bl31/runtime_svc.h index 66562e153f..d7d88d4c29 100644 --- a/include/bl31/runtime_svc.h +++ b/include/bl31/runtime_svc.h @@ -264,10 +264,10 @@ CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \ /******************************************************************************* * Function & variable prototypes ******************************************************************************/ -extern void runtime_svc_init(); +void runtime_svc_init(); extern uint64_t __RT_SVC_DESCS_START__; extern uint64_t __RT_SVC_DESCS_END__; -extern uint64_t get_crash_stack(uint64_t mpidr); -extern void runtime_exceptions(void); +uint64_t get_crash_stack(uint64_t mpidr); +void runtime_exceptions(void); #endif /*__ASSEMBLY__*/ #endif /* __RUNTIME_SVC_H__ */ diff --git a/include/bl31/services/psci.h b/include/bl31/services/psci.h index b6e272c3a4..887c4ceab5 100644 --- a/include/bl31/services/psci.h +++ b/include/bl31/services/psci.h @@ -178,36 +178,36 @@ typedef struct spd_pm_ops { /******************************************************************************* * Function & Data prototypes ******************************************************************************/ -extern unsigned int psci_version(void); -extern int __psci_cpu_suspend(unsigned int, unsigned long, unsigned long); -extern int __psci_cpu_off(void); -extern int psci_affinity_info(unsigned long, unsigned int); -extern int psci_migrate(unsigned int); -extern unsigned int psci_migrate_info_type(void); -extern unsigned long psci_migrate_info_up_cpu(void); -extern void psci_system_off(void); -extern void psci_system_reset(void); -extern int psci_cpu_on(unsigned long, - unsigned long, - unsigned long); -extern void __dead2 psci_power_down_wfi(void); -extern void psci_aff_on_finish_entry(void); -extern void psci_aff_suspend_finish_entry(void); -extern void psci_register_spd_pm_hook(const spd_pm_ops_t *); -extern int psci_get_suspend_stateid(unsigned long mpidr); -extern int psci_get_suspend_afflvl(unsigned long mpidr); +unsigned int psci_version(void); +int __psci_cpu_suspend(unsigned int, unsigned long, unsigned long); +int __psci_cpu_off(void); +int psci_affinity_info(unsigned long, unsigned int); +int psci_migrate(unsigned int); +unsigned int psci_migrate_info_type(void); +unsigned long psci_migrate_info_up_cpu(void); +void psci_system_off(void); +void psci_system_reset(void); +int psci_cpu_on(unsigned long, + unsigned long, + unsigned long); +void __dead2 psci_power_down_wfi(void); +void psci_aff_on_finish_entry(void); +void psci_aff_suspend_finish_entry(void); +void psci_register_spd_pm_hook(const spd_pm_ops_t *); +int psci_get_suspend_stateid(unsigned long mpidr); +int psci_get_suspend_afflvl(unsigned long mpidr); -extern uint64_t psci_smc_handler(uint32_t smc_fid, - uint64_t x1, - uint64_t x2, - uint64_t x3, - uint64_t x4, - void *cookie, - void *handle, - uint64_t flags); +uint64_t psci_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); /* PSCI setup function */ -extern int32_t psci_setup(void); +int32_t psci_setup(void); #endif /*__ASSEMBLY__*/ diff --git a/include/bl32/bl32.h b/include/bl32/bl32.h index 323948767d..ede7c48e01 100644 --- a/include/bl32/bl32.h +++ b/include/bl32/bl32.h @@ -41,8 +41,8 @@ struct meminfo; /****************************************** * Function prototypes *****************************************/ -extern void bl32_platform_setup(void); -extern struct meminfo *bl32_plat_sec_mem_layout(void); -extern uint64_t bl32_main(void); +void bl32_platform_setup(void); +struct meminfo *bl32_plat_sec_mem_layout(void); +uint64_t bl32_main(void); #endif /* __BL32_H__ */ diff --git a/include/bl32/payloads/tsp.h b/include/bl32/payloads/tsp.h index 9239ba4ab1..237ad48304 100644 --- a/include/bl32/payloads/tsp.h +++ b/include/bl32/payloads/tsp.h @@ -157,43 +157,43 @@ typedef struct tsp_args { */ CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch); -extern void tsp_get_magic(uint64_t args[4]); +void tsp_get_magic(uint64_t args[4]); -extern tsp_args_t *tsp_cpu_resume_main(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -extern tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -extern tsp_args_t *tsp_cpu_on_main(void); -extern tsp_args_t *tsp_cpu_off_main(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); +tsp_args_t *tsp_cpu_resume_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +tsp_args_t *tsp_cpu_on_main(void); +tsp_args_t *tsp_cpu_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); /* Generic Timer functions */ -extern void tsp_generic_timer_start(void); -extern void tsp_generic_timer_handler(void); -extern void tsp_generic_timer_stop(void); -extern void tsp_generic_timer_save(void); -extern void tsp_generic_timer_restore(void); +void tsp_generic_timer_start(void); +void tsp_generic_timer_handler(void); +void tsp_generic_timer_stop(void); +void tsp_generic_timer_save(void); +void tsp_generic_timer_restore(void); /* FIQ management functions */ -extern void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3); +void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3); /* Data structure to keep track of TSP statistics */ extern spinlock_t console_lock; diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 47b1e40ede..79f2329b7b 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -194,23 +194,23 @@ CASSERT(sizeof(unsigned long) == /******************************************************************************* * Function & variable prototypes ******************************************************************************/ -extern unsigned long page_align(unsigned long, unsigned); -extern void change_security_state(unsigned int); -extern void init_bl2_mem_layout(meminfo_t *, - meminfo_t *, - unsigned int, - unsigned long) __attribute__((weak)); -extern void init_bl31_mem_layout(const meminfo_t *, - meminfo_t *, - unsigned int) __attribute__((weak)); -extern unsigned long image_size(const char *); -extern int load_image(meminfo_t *, - const char *, - unsigned int, - unsigned long, - image_info_t *, - entry_point_info_t *); -extern unsigned long *get_el_change_mem_ptr(void); +unsigned long page_align(unsigned long, unsigned); +void change_security_state(unsigned int); +void init_bl2_mem_layout(meminfo_t *, + meminfo_t *, + unsigned int, + unsigned long) __attribute__((weak)); +void init_bl31_mem_layout(const meminfo_t *, + meminfo_t *, + unsigned int) __attribute__((weak)); +unsigned long image_size(const char *); +int load_image(meminfo_t *, + const char *, + unsigned int, + unsigned long, + image_info_t *, + entry_point_info_t *); +unsigned long *get_el_change_mem_ptr(void); extern const char build_message[]; #endif /*__ASSEMBLY__*/ diff --git a/include/common/debug.h b/include/common/debug.h index 522b4dfd9e..5b496d7629 100644 --- a/include/common/debug.h +++ b/include/common/debug.h @@ -57,15 +57,15 @@ * spin. This can be expanded in the future to provide more information. */ #if DEBUG -extern void __dead2 do_panic(const char *file, int line); +void __dead2 do_panic(const char *file, int line); #define panic() do_panic(__FILE__, __LINE__) #else -extern void __dead2 do_panic(void); +void __dead2 do_panic(void); #define panic() do_panic() #endif -extern void print_string_value(char *s, unsigned long *mem); +void print_string_value(char *s, unsigned long *mem); #endif /* __DEBUG_H__ */ diff --git a/include/drivers/arm/cci400.h b/include/drivers/arm/cci400.h index 3921675f78..7222391f92 100644 --- a/include/drivers/arm/cci400.h +++ b/include/drivers/arm/cci400.h @@ -66,7 +66,7 @@ #define CHANGE_PENDING_BIT (1 << 0) /* Function declarations */ -extern void cci_enable_coherency(unsigned long mpidr); -extern void cci_disable_coherency(unsigned long mpidr); +void cci_enable_coherency(unsigned long mpidr); +void cci_disable_coherency(unsigned long mpidr); #endif /* __CCI_400_H__ */ diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h index e81967638a..1859a8eb84 100644 --- a/include/drivers/arm/gic_v2.h +++ b/include/drivers/arm/gic_v2.h @@ -143,41 +143,41 @@ * GIC Distributor function prototypes ******************************************************************************/ -extern unsigned int gicd_read_igroupr(unsigned int, unsigned int); -extern unsigned int gicd_read_isenabler(unsigned int, unsigned int); -extern unsigned int gicd_read_icenabler(unsigned int, unsigned int); -extern unsigned int gicd_read_ispendr(unsigned int, unsigned int); -extern unsigned int gicd_read_icpendr(unsigned int, unsigned int); -extern unsigned int gicd_read_isactiver(unsigned int, unsigned int); -extern unsigned int gicd_read_icactiver(unsigned int, unsigned int); -extern unsigned int gicd_read_ipriorityr(unsigned int, unsigned int); -extern unsigned int gicd_read_itargetsr(unsigned int, unsigned int); -extern unsigned int gicd_read_icfgr(unsigned int, unsigned int); -extern unsigned int gicd_read_cpendsgir(unsigned int, unsigned int); -extern unsigned int gicd_read_spendsgir(unsigned int, unsigned int); -extern void gicd_write_igroupr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_isenabler(unsigned int, unsigned int, unsigned int); -extern void gicd_write_icenabler(unsigned int, unsigned int, unsigned int); -extern void gicd_write_ispendr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_icpendr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_isactiver(unsigned int, unsigned int, unsigned int); -extern void gicd_write_icactiver(unsigned int, unsigned int, unsigned int); -extern void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_icfgr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int); -extern void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int); -extern unsigned int gicd_get_igroupr(unsigned int, unsigned int); -extern void gicd_set_igroupr(unsigned int, unsigned int); -extern void gicd_clr_igroupr(unsigned int, unsigned int); -extern void gicd_set_isenabler(unsigned int, unsigned int); -extern void gicd_set_icenabler(unsigned int, unsigned int); -extern void gicd_set_ispendr(unsigned int, unsigned int); -extern void gicd_set_icpendr(unsigned int, unsigned int); -extern void gicd_set_isactiver(unsigned int, unsigned int); -extern void gicd_set_icactiver(unsigned int, unsigned int); -extern void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int); -extern void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int); +unsigned int gicd_read_igroupr(unsigned int, unsigned int); +unsigned int gicd_read_isenabler(unsigned int, unsigned int); +unsigned int gicd_read_icenabler(unsigned int, unsigned int); +unsigned int gicd_read_ispendr(unsigned int, unsigned int); +unsigned int gicd_read_icpendr(unsigned int, unsigned int); +unsigned int gicd_read_isactiver(unsigned int, unsigned int); +unsigned int gicd_read_icactiver(unsigned int, unsigned int); +unsigned int gicd_read_ipriorityr(unsigned int, unsigned int); +unsigned int gicd_read_itargetsr(unsigned int, unsigned int); +unsigned int gicd_read_icfgr(unsigned int, unsigned int); +unsigned int gicd_read_cpendsgir(unsigned int, unsigned int); +unsigned int gicd_read_spendsgir(unsigned int, unsigned int); +void gicd_write_igroupr(unsigned int, unsigned int, unsigned int); +void gicd_write_isenabler(unsigned int, unsigned int, unsigned int); +void gicd_write_icenabler(unsigned int, unsigned int, unsigned int); +void gicd_write_ispendr(unsigned int, unsigned int, unsigned int); +void gicd_write_icpendr(unsigned int, unsigned int, unsigned int); +void gicd_write_isactiver(unsigned int, unsigned int, unsigned int); +void gicd_write_icactiver(unsigned int, unsigned int, unsigned int); +void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int); +void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int); +void gicd_write_icfgr(unsigned int, unsigned int, unsigned int); +void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int); +void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int); +unsigned int gicd_get_igroupr(unsigned int, unsigned int); +void gicd_set_igroupr(unsigned int, unsigned int); +void gicd_clr_igroupr(unsigned int, unsigned int); +void gicd_set_isenabler(unsigned int, unsigned int); +void gicd_set_icenabler(unsigned int, unsigned int); +void gicd_set_ispendr(unsigned int, unsigned int); +void gicd_set_icpendr(unsigned int, unsigned int); +void gicd_set_isactiver(unsigned int, unsigned int); +void gicd_set_icactiver(unsigned int, unsigned int); +void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int); +void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int); /******************************************************************************* diff --git a/include/drivers/arm/gic_v3.h b/include/drivers/arm/gic_v3.h index 6f072a3dd0..0f99994c2c 100644 --- a/include/drivers/arm/gic_v3.h +++ b/include/drivers/arm/gic_v3.h @@ -68,13 +68,13 @@ ******************************************************************************/ uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr); -extern unsigned int read_icc_sre_el1(void); -extern unsigned int read_icc_sre_el2(void); -extern unsigned int read_icc_sre_el3(void); -extern void write_icc_sre_el1(unsigned int); -extern void write_icc_sre_el2(unsigned int); -extern void write_icc_sre_el3(unsigned int); -extern void write_icc_pmr_el1(unsigned int); +unsigned int read_icc_sre_el1(void); +unsigned int read_icc_sre_el2(void); +unsigned int read_icc_sre_el3(void); +void write_icc_sre_el1(unsigned int); +void write_icc_sre_el2(unsigned int); +void write_icc_sre_el3(unsigned int); +void write_icc_pmr_el1(unsigned int); /******************************************************************************* * GIC Redistributor interface accessors diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index f30301d179..f16c4b5ae3 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -37,243 +37,243 @@ /******************************************************************************* * Aarch64 translation tables manipulation helper prototypes ******************************************************************************/ -extern unsigned long create_table_desc(unsigned long *next_table_ptr); -extern unsigned long create_block_desc(unsigned long desc, - unsigned long addr, - unsigned int level); -extern unsigned long create_device_block(unsigned long output_addr, - unsigned int level, - unsigned int ns); -extern unsigned long create_romem_block(unsigned long output_addr, - unsigned int level, - unsigned int ns); -extern unsigned long create_rwmem_block(unsigned long output_addr, - unsigned int level, - unsigned int ns); +unsigned long create_table_desc(unsigned long *next_table_ptr); +unsigned long create_block_desc(unsigned long desc, + unsigned long addr, + unsigned int level); +unsigned long create_device_block(unsigned long output_addr, + unsigned int level, + unsigned int ns); +unsigned long create_romem_block(unsigned long output_addr, + unsigned int level, + unsigned int ns); +unsigned long create_rwmem_block(unsigned long output_addr, + unsigned int level, + unsigned int ns); /******************************************************************************* * TLB maintenance accessor prototypes ******************************************************************************/ -extern void tlbialle1(void); -extern void tlbialle1is(void); -extern void tlbialle2(void); -extern void tlbialle2is(void); -extern void tlbialle3(void); -extern void tlbialle3is(void); -extern void tlbivmalle1(void); +void tlbialle1(void); +void tlbialle1is(void); +void tlbialle2(void); +void tlbialle2is(void); +void tlbialle3(void); +void tlbialle3is(void); +void tlbivmalle1(void); /******************************************************************************* * Cache maintenance accessor prototypes ******************************************************************************/ -extern void dcisw(unsigned long); -extern void dccisw(unsigned long); -extern void dccsw(unsigned long); -extern void dccvac(unsigned long); -extern void dcivac(unsigned long); -extern void dccivac(unsigned long); -extern void dccvau(unsigned long); -extern void dczva(unsigned long); -extern void flush_dcache_range(unsigned long, unsigned long); -extern void inv_dcache_range(unsigned long, unsigned long); -extern void dcsw_op_louis(unsigned int); -extern void dcsw_op_all(unsigned int); +void dcisw(unsigned long); +void dccisw(unsigned long); +void dccsw(unsigned long); +void dccvac(unsigned long); +void dcivac(unsigned long); +void dccivac(unsigned long); +void dccvau(unsigned long); +void dczva(unsigned long); +void flush_dcache_range(unsigned long, unsigned long); +void inv_dcache_range(unsigned long, unsigned long); +void dcsw_op_louis(unsigned int); +void dcsw_op_all(unsigned int); -extern void disable_mmu_el3(void); -extern void disable_mmu_icache_el3(void); +void disable_mmu_el3(void); +void disable_mmu_icache_el3(void); /******************************************************************************* * Misc. accessor prototypes ******************************************************************************/ -extern void enable_irq(void); -extern void enable_fiq(void); -extern void enable_serror(void); -extern void enable_debug_exceptions(void); +void enable_irq(void); +void enable_fiq(void); +void enable_serror(void); +void enable_debug_exceptions(void); -extern void disable_irq(void); -extern void disable_fiq(void); -extern void disable_serror(void); -extern void disable_debug_exceptions(void); +void disable_irq(void); +void disable_fiq(void); +void disable_serror(void); +void disable_debug_exceptions(void); -extern unsigned long read_id_pfr1_el1(void); -extern unsigned long read_id_aa64pfr0_el1(void); -extern unsigned long read_current_el(void); -extern unsigned long read_daif(void); -extern unsigned long read_spsr_el1(void); -extern unsigned long read_spsr_el2(void); -extern unsigned long read_spsr_el3(void); -extern unsigned long read_elr_el1(void); -extern unsigned long read_elr_el2(void); -extern unsigned long read_elr_el3(void); +unsigned long read_id_pfr1_el1(void); +unsigned long read_id_aa64pfr0_el1(void); +unsigned long read_current_el(void); +unsigned long read_daif(void); +unsigned long read_spsr_el1(void); +unsigned long read_spsr_el2(void); +unsigned long read_spsr_el3(void); +unsigned long read_elr_el1(void); +unsigned long read_elr_el2(void); +unsigned long read_elr_el3(void); -extern void write_daif(unsigned long); -extern void write_spsr_el1(unsigned long); -extern void write_spsr_el2(unsigned long); -extern void write_spsr_el3(unsigned long); -extern void write_elr_el1(unsigned long); -extern void write_elr_el2(unsigned long); -extern void write_elr_el3(unsigned long); +void write_daif(unsigned long); +void write_spsr_el1(unsigned long); +void write_spsr_el2(unsigned long); +void write_spsr_el3(unsigned long); +void write_elr_el1(unsigned long); +void write_elr_el2(unsigned long); +void write_elr_el3(unsigned long); -extern void wfi(void); -extern void wfe(void); -extern void rfe(void); -extern void sev(void); -extern void dsb(void); -extern void isb(void); +void wfi(void); +void wfe(void); +void rfe(void); +void sev(void); +void dsb(void); +void isb(void); -extern unsigned int get_afflvl_shift(unsigned int); -extern unsigned int mpidr_mask_lower_afflvls(unsigned long, unsigned int); +unsigned int get_afflvl_shift(unsigned int); +unsigned int mpidr_mask_lower_afflvls(unsigned long, unsigned int); -extern void __dead2 eret(unsigned long, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long); +void __dead2 eret(unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long); -extern void __dead2 smc(unsigned long, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long); +void __dead2 smc(unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long); /******************************************************************************* * System register accessor prototypes ******************************************************************************/ -extern unsigned long read_midr(void); -extern unsigned long read_mpidr(void); +unsigned long read_midr(void); +unsigned long read_mpidr(void); -extern unsigned long read_scr(void); -extern unsigned long read_hcr(void); +unsigned long read_scr(void); +unsigned long read_hcr(void); -extern unsigned long read_vbar_el1(void); -extern unsigned long read_vbar_el2(void); -extern unsigned long read_vbar_el3(void); +unsigned long read_vbar_el1(void); +unsigned long read_vbar_el2(void); +unsigned long read_vbar_el3(void); -extern unsigned long read_sctlr_el1(void); -extern unsigned long read_sctlr_el2(void); -extern unsigned long read_sctlr_el3(void); +unsigned long read_sctlr_el1(void); +unsigned long read_sctlr_el2(void); +unsigned long read_sctlr_el3(void); -extern unsigned long read_actlr_el1(void); -extern unsigned long read_actlr_el2(void); -extern unsigned long read_actlr_el3(void); +unsigned long read_actlr_el1(void); +unsigned long read_actlr_el2(void); +unsigned long read_actlr_el3(void); -extern unsigned long read_esr_el1(void); -extern unsigned long read_esr_el2(void); -extern unsigned long read_esr_el3(void); +unsigned long read_esr_el1(void); +unsigned long read_esr_el2(void); +unsigned long read_esr_el3(void); -extern unsigned long read_afsr0_el1(void); -extern unsigned long read_afsr0_el2(void); -extern unsigned long read_afsr0_el3(void); +unsigned long read_afsr0_el1(void); +unsigned long read_afsr0_el2(void); +unsigned long read_afsr0_el3(void); -extern unsigned long read_afsr1_el1(void); -extern unsigned long read_afsr1_el2(void); -extern unsigned long read_afsr1_el3(void); +unsigned long read_afsr1_el1(void); +unsigned long read_afsr1_el2(void); +unsigned long read_afsr1_el3(void); -extern unsigned long read_far_el1(void); -extern unsigned long read_far_el2(void); -extern unsigned long read_far_el3(void); +unsigned long read_far_el1(void); +unsigned long read_far_el2(void); +unsigned long read_far_el3(void); -extern unsigned long read_mair_el1(void); -extern unsigned long read_mair_el2(void); -extern unsigned long read_mair_el3(void); +unsigned long read_mair_el1(void); +unsigned long read_mair_el2(void); +unsigned long read_mair_el3(void); -extern unsigned long read_amair_el1(void); -extern unsigned long read_amair_el2(void); -extern unsigned long read_amair_el3(void); +unsigned long read_amair_el1(void); +unsigned long read_amair_el2(void); +unsigned long read_amair_el3(void); -extern unsigned long read_rvbar_el1(void); -extern unsigned long read_rvbar_el2(void); -extern unsigned long read_rvbar_el3(void); +unsigned long read_rvbar_el1(void); +unsigned long read_rvbar_el2(void); +unsigned long read_rvbar_el3(void); -extern unsigned long read_rmr_el1(void); -extern unsigned long read_rmr_el2(void); -extern unsigned long read_rmr_el3(void); +unsigned long read_rmr_el1(void); +unsigned long read_rmr_el2(void); +unsigned long read_rmr_el3(void); -extern unsigned long read_tcr_el1(void); -extern unsigned long read_tcr_el2(void); -extern unsigned long read_tcr_el3(void); +unsigned long read_tcr_el1(void); +unsigned long read_tcr_el2(void); +unsigned long read_tcr_el3(void); -extern unsigned long read_ttbr0_el1(void); -extern unsigned long read_ttbr0_el2(void); -extern unsigned long read_ttbr0_el3(void); +unsigned long read_ttbr0_el1(void); +unsigned long read_ttbr0_el2(void); +unsigned long read_ttbr0_el3(void); -extern unsigned long read_ttbr1_el1(void); +unsigned long read_ttbr1_el1(void); -extern unsigned long read_cptr_el2(void); -extern unsigned long read_cptr_el3(void); +unsigned long read_cptr_el2(void); +unsigned long read_cptr_el3(void); -extern unsigned long read_cpacr(void); -extern unsigned long read_cpuectlr(void); -extern unsigned int read_cntfrq_el0(void); -extern unsigned int read_cntps_ctl_el1(void); -extern unsigned int read_cntps_tval_el1(void); -extern unsigned long read_cntps_cval_el1(void); -extern unsigned long read_cntpct_el0(void); -extern unsigned long read_cnthctl_el2(void); +unsigned long read_cpacr(void); +unsigned long read_cpuectlr(void); +unsigned int read_cntfrq_el0(void); +unsigned int read_cntps_ctl_el1(void); +unsigned int read_cntps_tval_el1(void); +unsigned long read_cntps_cval_el1(void); +unsigned long read_cntpct_el0(void); +unsigned long read_cnthctl_el2(void); -extern unsigned long read_tpidr_el3(void); +unsigned long read_tpidr_el3(void); -extern void write_scr(unsigned long); -extern void write_hcr(unsigned long); -extern void write_cpacr(unsigned long); -extern void write_cntfrq_el0(unsigned int); -extern void write_cntps_ctl_el1(unsigned int); -extern void write_cntps_tval_el1(unsigned int); -extern void write_cntps_cval_el1(unsigned long); -extern void write_cnthctl_el2(unsigned long); +void write_scr(unsigned long); +void write_hcr(unsigned long); +void write_cpacr(unsigned long); +void write_cntfrq_el0(unsigned int); +void write_cntps_ctl_el1(unsigned int); +void write_cntps_tval_el1(unsigned int); +void write_cntps_cval_el1(unsigned long); +void write_cnthctl_el2(unsigned long); -extern void write_vbar_el1(unsigned long); -extern void write_vbar_el2(unsigned long); -extern void write_vbar_el3(unsigned long); +void write_vbar_el1(unsigned long); +void write_vbar_el2(unsigned long); +void write_vbar_el3(unsigned long); -extern void write_sctlr_el1(unsigned long); -extern void write_sctlr_el2(unsigned long); -extern void write_sctlr_el3(unsigned long); +void write_sctlr_el1(unsigned long); +void write_sctlr_el2(unsigned long); +void write_sctlr_el3(unsigned long); -extern void write_actlr_el1(unsigned long); -extern void write_actlr_el2(unsigned long); -extern void write_actlr_el3(unsigned long); +void write_actlr_el1(unsigned long); +void write_actlr_el2(unsigned long); +void write_actlr_el3(unsigned long); -extern void write_esr_el1(unsigned long); -extern void write_esr_el2(unsigned long); -extern void write_esr_el3(unsigned long); +void write_esr_el1(unsigned long); +void write_esr_el2(unsigned long); +void write_esr_el3(unsigned long); -extern void write_afsr0_el1(unsigned long); -extern void write_afsr0_el2(unsigned long); -extern void write_afsr0_el3(unsigned long); +void write_afsr0_el1(unsigned long); +void write_afsr0_el2(unsigned long); +void write_afsr0_el3(unsigned long); -extern void write_afsr1_el1(unsigned long); -extern void write_afsr1_el2(unsigned long); -extern void write_afsr1_el3(unsigned long); +void write_afsr1_el1(unsigned long); +void write_afsr1_el2(unsigned long); +void write_afsr1_el3(unsigned long); -extern void write_far_el1(unsigned long); -extern void write_far_el2(unsigned long); -extern void write_far_el3(unsigned long); +void write_far_el1(unsigned long); +void write_far_el2(unsigned long); +void write_far_el3(unsigned long); -extern void write_mair_el1(unsigned long); -extern void write_mair_el2(unsigned long); -extern void write_mair_el3(unsigned long); +void write_mair_el1(unsigned long); +void write_mair_el2(unsigned long); +void write_mair_el3(unsigned long); -extern void write_amair_el1(unsigned long); -extern void write_amair_el2(unsigned long); -extern void write_amair_el3(unsigned long); +void write_amair_el1(unsigned long); +void write_amair_el2(unsigned long); +void write_amair_el3(unsigned long); -extern void write_rmr_el1(unsigned long); -extern void write_rmr_el2(unsigned long); -extern void write_rmr_el3(unsigned long); +void write_rmr_el1(unsigned long); +void write_rmr_el2(unsigned long); +void write_rmr_el3(unsigned long); -extern void write_tcr_el1(unsigned long); -extern void write_tcr_el2(unsigned long); -extern void write_tcr_el3(unsigned long); +void write_tcr_el1(unsigned long); +void write_tcr_el2(unsigned long); +void write_tcr_el3(unsigned long); -extern void write_ttbr0_el1(unsigned long); -extern void write_ttbr0_el2(unsigned long); -extern void write_ttbr0_el3(unsigned long); +void write_ttbr0_el1(unsigned long); +void write_ttbr0_el2(unsigned long); +void write_ttbr0_el3(unsigned long); -extern void write_ttbr1_el1(unsigned long); +void write_ttbr1_el1(unsigned long); -extern void write_cpuectlr(unsigned long); -extern void write_cptr_el2(unsigned long); -extern void write_cptr_el3(unsigned long); +void write_cpuectlr(unsigned long); +void write_cptr_el2(unsigned long); +void write_cptr_el3(unsigned long); -extern void write_tpidr_el3(unsigned long); +void write_tpidr_el3(unsigned long); #define IS_IN_EL(x) \ (GET_EL(read_current_el()) == MODE_EL##x) diff --git a/include/lib/aarch64/xlat_tables.h b/include/lib/aarch64/xlat_tables.h index d7e1c60b1a..a500f03355 100644 --- a/include/lib/aarch64/xlat_tables.h +++ b/include/lib/aarch64/xlat_tables.h @@ -60,11 +60,11 @@ typedef struct mmap_region { mmap_attr_t attr; } mmap_region_t; -extern void mmap_add_region(unsigned long base, unsigned long size, - unsigned attr); -extern void mmap_add(const mmap_region_t *mm); +void mmap_add_region(unsigned long base, unsigned long size, + unsigned attr); +void mmap_add(const mmap_region_t *mm); -extern void init_xlat_tables(void); +void init_xlat_tables(void); extern uint64_t l1_xlation_table[]; diff --git a/include/lib/mmio.h b/include/lib/mmio.h index d3c2cae515..5d33c5977a 100644 --- a/include/lib/mmio.h +++ b/include/lib/mmio.h @@ -33,13 +33,13 @@ #include -extern void mmio_write_8(uintptr_t addr, uint8_t value); -extern uint8_t mmio_read_8(uintptr_t addr); +void mmio_write_8(uintptr_t addr, uint8_t value); +uint8_t mmio_read_8(uintptr_t addr); -extern void mmio_write_32(uintptr_t addr, uint32_t value); -extern uint32_t mmio_read_32(uintptr_t addr); +void mmio_write_32(uintptr_t addr, uint32_t value); +uint32_t mmio_read_32(uintptr_t addr); -extern void mmio_write_64(uintptr_t addr, uint64_t value); -extern uint64_t mmio_read_64(uintptr_t addr); +void mmio_write_64(uintptr_t addr, uint64_t value); +uint64_t mmio_read_64(uintptr_t addr); #endif /* __MMIO_H__ */ diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c index 3c9db2217b..849ec1207e 100644 --- a/lib/semihosting/semihosting.c +++ b/lib/semihosting/semihosting.c @@ -37,8 +37,8 @@ #define SEMIHOSTING_SUPPORTED 1 #endif -extern long semihosting_call(unsigned long operation, - void *system_block_address); +long semihosting_call(unsigned long operation, + void *system_block_address); typedef struct { const char *file_name; diff --git a/plat/fvp/drivers/pwrc/fvp_pwrc.h b/plat/fvp/drivers/pwrc/fvp_pwrc.h index f600a24136..ad1ea85b34 100644 --- a/plat/fvp/drivers/pwrc/fvp_pwrc.h +++ b/plat/fvp/drivers/pwrc/fvp_pwrc.h @@ -63,14 +63,14 @@ /******************************************************************************* * Function & variable prototypes ******************************************************************************/ -extern int fvp_pwrc_setup(void); -extern void fvp_pwrc_write_pcoffr(unsigned long); -extern void fvp_pwrc_write_ppoffr(unsigned long); -extern void fvp_pwrc_write_pponr(unsigned long); -extern void fvp_pwrc_set_wen(unsigned long); -extern void fvp_pwrc_clr_wen(unsigned long); -extern unsigned int fvp_pwrc_read_psysr(unsigned long); -extern unsigned int fvp_pwrc_get_cpu_wkr(unsigned long); +int fvp_pwrc_setup(void); +void fvp_pwrc_write_pcoffr(unsigned long); +void fvp_pwrc_write_ppoffr(unsigned long); +void fvp_pwrc_write_pponr(unsigned long); +void fvp_pwrc_set_wen(unsigned long); +void fvp_pwrc_clr_wen(unsigned long); +unsigned int fvp_pwrc_read_psysr(unsigned long); +unsigned int fvp_pwrc_get_cpu_wkr(unsigned long); #endif /*__ASSEMBLY__*/ diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h index 786988c048..36a3b33aa2 100644 --- a/plat/fvp/platform.h +++ b/plat/fvp/platform.h @@ -423,77 +423,77 @@ typedef struct bl2_to_bl31_params_mem { /******************************************************************************* * Function and variable prototypes ******************************************************************************/ -extern unsigned long *bl1_normal_ram_base; -extern unsigned long *bl1_normal_ram_len; -extern unsigned long *bl1_normal_ram_limit; -extern unsigned long *bl1_normal_ram_zi_base; -extern unsigned long *bl1_normal_ram_zi_len; +unsigned long *bl1_normal_ram_base; +unsigned long *bl1_normal_ram_len; +unsigned long *bl1_normal_ram_limit; +unsigned long *bl1_normal_ram_zi_base; +unsigned long *bl1_normal_ram_zi_len; -extern unsigned long *bl1_coherent_ram_base; -extern unsigned long *bl1_coherent_ram_len; -extern unsigned long *bl1_coherent_ram_limit; -extern unsigned long *bl1_coherent_ram_zi_base; -extern unsigned long *bl1_coherent_ram_zi_len; -extern unsigned long warm_boot_entrypoint; +unsigned long *bl1_coherent_ram_base; +unsigned long *bl1_coherent_ram_len; +unsigned long *bl1_coherent_ram_limit; +unsigned long *bl1_coherent_ram_zi_base; +unsigned long *bl1_coherent_ram_zi_len; +unsigned long warm_boot_entrypoint; -extern void bl1_plat_arch_setup(void); -extern void bl2_plat_arch_setup(void); -extern void bl31_plat_arch_setup(void); -extern int platform_setup_pm(const struct plat_pm_ops **); -extern unsigned int platform_get_core_pos(unsigned long mpidr); -extern void enable_mmu_el1(void); -extern void enable_mmu_el3(void); -extern void configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); -extern void configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); -extern unsigned long platform_get_cfgvar(unsigned int); -extern int platform_config_setup(void); -extern void plat_report_exception(unsigned long); -extern unsigned long plat_get_ns_image_entrypoint(void); -extern unsigned long platform_get_stack(unsigned long mpidr); -extern uint64_t plat_get_syscnt_freq(void); +void bl1_plat_arch_setup(void); +void bl2_plat_arch_setup(void); +void bl31_plat_arch_setup(void); +int platform_setup_pm(const struct plat_pm_ops **); +unsigned int platform_get_core_pos(unsigned long mpidr); +void enable_mmu_el1(void); +void enable_mmu_el3(void); +void configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit, + unsigned long coh_start, + unsigned long coh_limit); +void configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit, + unsigned long coh_start, + unsigned long coh_limit); +unsigned long platform_get_cfgvar(unsigned int); +int platform_config_setup(void); +void plat_report_exception(unsigned long); +unsigned long plat_get_ns_image_entrypoint(void); +unsigned long platform_get_stack(unsigned long mpidr); +uint64_t plat_get_syscnt_freq(void); #if RESET_TO_BL31 -extern void plat_get_entry_point_info(unsigned long target_security, - struct entry_point_info *target_entry_info); +void plat_get_entry_point_info(unsigned long target_security, + el_change_info_t *target_entry_info); #endif - -extern void fvp_cci_setup(void); +void fvp_cci_setup(void); /* Declarations for plat_gic.c */ -extern uint32_t ic_get_pending_interrupt_id(void); -extern uint32_t ic_get_pending_interrupt_type(void); -extern uint32_t ic_acknowledge_interrupt(void); -extern uint32_t ic_get_interrupt_type(uint32_t id); -extern void ic_end_of_interrupt(uint32_t id); -extern void gic_cpuif_deactivate(unsigned int); -extern void gic_cpuif_setup(unsigned int); -extern void gic_pcpu_distif_setup(unsigned int); -extern void gic_setup(void); -extern uint32_t plat_interrupt_type_to_line(uint32_t type, +uint32_t ic_get_pending_interrupt_id(void); +uint32_t ic_get_pending_interrupt_type(void); +uint32_t ic_acknowledge_interrupt(void); +uint32_t ic_get_interrupt_type(uint32_t id); +void ic_end_of_interrupt(uint32_t id); +void gic_cpuif_deactivate(unsigned int); +void gic_cpuif_setup(unsigned int); +void gic_pcpu_distif_setup(unsigned int); +void gic_setup(void); +uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state); /* Declarations for plat_topology.c */ -extern int plat_setup_topology(void); -extern int plat_get_max_afflvl(void); -extern unsigned int plat_get_aff_count(unsigned int, unsigned long); -extern unsigned int plat_get_aff_state(unsigned int, unsigned long); +int plat_setup_topology(void); +int plat_get_max_afflvl(void); +unsigned int plat_get_aff_count(unsigned int, unsigned long); +unsigned int plat_get_aff_state(unsigned int, unsigned long); /* Declarations for plat_io_storage.c */ -extern void io_setup(void); -extern int plat_get_image_source(const char *image_name, - uintptr_t *dev_handle, uintptr_t *image_spec); +void io_setup(void); +int plat_get_image_source(const char *image_name, + uintptr_t *dev_handle, + uintptr_t *image_spec); /* Declarations for plat_security.c */ -extern void plat_security_setup(void); +void plat_security_setup(void); /* * Before calling this function BL2 is loaded in memory and its entrypoint @@ -501,8 +501,8 @@ extern void plat_security_setup(void); * the entrypoint of BL2 and set SPSR and security state. * On FVP we are only setting the security state, entrypoint */ -extern void bl1_plat_set_bl2_ep_info(struct image_info *image, - struct entry_point_info *ep); +void bl1_plat_set_bl2_ep_info(struct image_info *image, + struct entry_point_info *ep); /* * Before calling this function BL31 is loaded in memory and its entrypoint @@ -510,8 +510,8 @@ extern void bl1_plat_set_bl2_ep_info(struct image_info *image, * the entrypoint of BL31 and set SPSR and security state. * On FVP we are only setting the security state, entrypoint */ -extern void bl2_plat_set_bl31_ep_info(struct image_info *image, - struct entry_point_info *ep); +void bl2_plat_set_bl31_ep_info(struct image_info *image, + struct entry_point_info *ep); /* * Before calling this function BL32 is loaded in memory and its entrypoint @@ -519,8 +519,8 @@ extern void bl2_plat_set_bl31_ep_info(struct image_info *image, * the entrypoint of BL32 and set SPSR and security state. * On FVP we are only setting the security state, entrypoint */ -extern void bl2_plat_set_bl32_ep_info(struct image_info *image, - struct entry_point_info *ep); +void bl2_plat_set_bl32_ep_info(struct image_info *image, + struct entry_point_info *ep); /* * Before calling this function BL33 is loaded in memory and its entrypoint @@ -528,20 +528,20 @@ extern void bl2_plat_set_bl32_ep_info(struct image_info *image, * the entrypoint of BL33 and set SPSR and security state. * On FVP we are only setting the security state, entrypoint */ -extern void bl2_plat_set_bl33_ep_info(struct image_info *image, - struct entry_point_info *ep); +void bl2_plat_set_bl33_ep_info(struct image_info *image, + struct entry_point_info *ep); /* Gets the memory layout for BL32 */ -extern void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); +void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); /* Gets the memory layout for BL33 */ -extern void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); +void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); /* Sets the entrypoint for BL32 */ -extern void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep_info); +void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep_info); /* Sets the entrypoint for BL33 */ -extern void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep_info); +void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep_info); #endif /*__ASSEMBLY__*/ diff --git a/services/spd/tspd/tspd_private.h b/services/spd/tspd/tspd_private.h index fbb0388710..fb71922512 100644 --- a/services/spd/tspd/tspd_private.h +++ b/services/spd/tspd/tspd_private.h @@ -188,11 +188,11 @@ struct tsp_vectors; /******************************************************************************* * Function & Data prototypes ******************************************************************************/ -extern uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); -extern void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); -extern uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); -extern void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); -extern int32_t tspd_init_secure_context(uint64_t entrypoint, +uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); +void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); +uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); +void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); +int32_t tspd_init_secure_context(uint64_t entrypoint, uint32_t rw, uint64_t mpidr, tsp_context_t *tsp_ctx); diff --git a/services/std_svc/psci/psci_private.h b/services/std_svc/psci/psci_private.h index a57095842f..1210b7ebf5 100644 --- a/services/std_svc/psci/psci_private.h +++ b/services/std_svc/psci/psci_private.h @@ -102,59 +102,59 @@ extern const spd_pm_ops_t *psci_spd_pm; * Function prototypes ******************************************************************************/ /* Private exported functions from psci_common.c */ -extern int get_max_afflvl(void); -extern unsigned short psci_get_state(aff_map_node_t *node); -extern unsigned short psci_get_phys_state(aff_map_node_t *node); -extern void psci_set_state(aff_map_node_t *node, unsigned short state); -extern void psci_get_ns_entry_info(unsigned int index); -extern unsigned long mpidr_set_aff_inst(unsigned long, unsigned char, int); -extern int psci_validate_mpidr(unsigned long, int); -extern int get_power_on_target_afflvl(unsigned long mpidr); -extern void psci_afflvl_power_on_finish(unsigned long, - int, - int, - afflvl_power_on_finisher_t *); -extern int psci_set_ns_entry_info(unsigned int index, - unsigned long entrypoint, - unsigned long context_id); -extern int psci_check_afflvl_range(int start_afflvl, int end_afflvl); -extern void psci_acquire_afflvl_locks(unsigned long mpidr, - int start_afflvl, - int end_afflvl, - mpidr_aff_map_nodes_t mpidr_nodes); -extern void psci_release_afflvl_locks(unsigned long mpidr, - int start_afflvl, - int end_afflvl, - mpidr_aff_map_nodes_t mpidr_nodes); +int get_max_afflvl(void); +unsigned short psci_get_state(aff_map_node_t *node); +unsigned short psci_get_phys_state(aff_map_node_t *node); +void psci_set_state(aff_map_node_t *node, unsigned short state); +void psci_get_ns_entry_info(unsigned int index); +unsigned long mpidr_set_aff_inst(unsigned long, unsigned char, int); +int psci_validate_mpidr(unsigned long, int); +int get_power_on_target_afflvl(unsigned long mpidr); +void psci_afflvl_power_on_finish(unsigned long, + int, + int, + afflvl_power_on_finisher_t *); +int psci_set_ns_entry_info(unsigned int index, + unsigned long entrypoint, + unsigned long context_id); +int psci_check_afflvl_range(int start_afflvl, int end_afflvl); +void psci_acquire_afflvl_locks(unsigned long mpidr, + int start_afflvl, + int end_afflvl, + mpidr_aff_map_nodes_t mpidr_nodes); +void psci_release_afflvl_locks(unsigned long mpidr, + int start_afflvl, + int end_afflvl, + mpidr_aff_map_nodes_t mpidr_nodes); /* Private exported functions from psci_setup.c */ -extern int psci_get_aff_map_nodes(unsigned long mpidr, - int start_afflvl, - int end_afflvl, - mpidr_aff_map_nodes_t mpidr_nodes); -extern aff_map_node_t *psci_get_aff_map_node(unsigned long, int); +int psci_get_aff_map_nodes(unsigned long mpidr, + int start_afflvl, + int end_afflvl, + mpidr_aff_map_nodes_t mpidr_nodes); +aff_map_node_t *psci_get_aff_map_node(unsigned long, int); /* Private exported functions from psci_affinity_on.c */ -extern int psci_afflvl_on(unsigned long, - unsigned long, - unsigned long, - int, - int); +int psci_afflvl_on(unsigned long, + unsigned long, + unsigned long, + int, + int); /* Private exported functions from psci_affinity_off.c */ -extern int psci_afflvl_off(unsigned long, int, int); +int psci_afflvl_off(unsigned long, int, int); /* Private exported functions from psci_affinity_suspend.c */ -extern void psci_set_suspend_power_state(aff_map_node_t *node, - unsigned int power_state); -extern int psci_get_aff_map_node_suspend_afflvl(aff_map_node_t *node); -extern int psci_afflvl_suspend(unsigned long, - unsigned long, - unsigned long, - unsigned int, - int, - int); -extern unsigned int psci_afflvl_suspend_finish(unsigned long, int, int); +void psci_set_suspend_power_state(aff_map_node_t *node, + unsigned int power_state); +int psci_get_aff_map_node_suspend_afflvl(aff_map_node_t *node); +int psci_afflvl_suspend(unsigned long, + unsigned long, + unsigned long, + unsigned int, + int, + int); +unsigned int psci_afflvl_suspend_finish(unsigned long, int, int); #endif /* __PSCI_PRIVATE_H__ */ From 7a9a5f2d22c4f76ae95300fe52129603d29bccc1 Mon Sep 17 00:00:00 2001 From: Dan Handley Date: Wed, 14 May 2014 15:13:16 +0100 Subject: [PATCH 2/8] Remove unused data declarations Some data variables were declared but not used. These have been removed. Change-Id: I038632af3c32d88984cd25b886c43ff763269bf9 --- include/bl2/bl2.h | 5 ----- include/bl31/bl31.h | 5 ----- plat/fvp/platform.h | 13 ------------- services/std_svc/psci/psci_common.c | 16 ++-------------- services/std_svc/psci/psci_private.h | 4 ---- services/std_svc/psci/psci_setup.c | 16 ++++++++++++++++ 6 files changed, 18 insertions(+), 41 deletions(-) diff --git a/include/bl2/bl2.h b/include/bl2/bl2.h index b028faa0f8..fffe5a63b8 100644 --- a/include/bl2/bl2.h +++ b/include/bl2/bl2.h @@ -31,11 +31,6 @@ #ifndef __BL2_H__ #define __BL2_H__ -/****************************************** - * Data declarations - *****************************************/ -extern unsigned long long bl2_entrypoint; - /****************************************** * Forward declarations *****************************************/ diff --git a/include/bl31/bl31.h b/include/bl31/bl31.h index 744dcc29dc..ef32568738 100644 --- a/include/bl31/bl31.h +++ b/include/bl31/bl31.h @@ -33,11 +33,6 @@ #include -/******************************************************************************* - * Data declarations - ******************************************************************************/ -extern unsigned long bl31_entrypoint; - /****************************************** * Forward declarations *****************************************/ diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h index 36a3b33aa2..0e3de5fc10 100644 --- a/plat/fvp/platform.h +++ b/plat/fvp/platform.h @@ -423,19 +423,6 @@ typedef struct bl2_to_bl31_params_mem { /******************************************************************************* * Function and variable prototypes ******************************************************************************/ -unsigned long *bl1_normal_ram_base; -unsigned long *bl1_normal_ram_len; -unsigned long *bl1_normal_ram_limit; -unsigned long *bl1_normal_ram_zi_base; -unsigned long *bl1_normal_ram_zi_len; - -unsigned long *bl1_coherent_ram_base; -unsigned long *bl1_coherent_ram_len; -unsigned long *bl1_coherent_ram_limit; -unsigned long *bl1_coherent_ram_zi_base; -unsigned long *bl1_coherent_ram_zi_len; -unsigned long warm_boot_entrypoint; - void bl1_plat_arch_setup(void); void bl2_plat_arch_setup(void); void bl31_plat_arch_setup(void); diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c index 025d8b434a..c61e87adfb 100644 --- a/services/std_svc/psci/psci_common.c +++ b/services/std_svc/psci/psci_common.c @@ -45,13 +45,11 @@ const spd_pm_ops_t *psci_spd_pm; /******************************************************************************* * Arrays that contains information needs to resume a cpu's execution when woken - * out of suspend or off states. 'psci_ns_einfo_idx' keeps track of the next - * free index in the 'psci_ns_entry_info' & 'psci_suspend_context' arrays. Each - * cpu is allocated a single entry in each array during startup. + * out of suspend or off states. Each cpu is allocated a single entry in each + * array during startup. ******************************************************************************/ suspend_context_t psci_suspend_context[PSCI_NUM_AFFS]; ns_entry_info_t psci_ns_entry_info[PSCI_NUM_AFFS]; -unsigned int psci_ns_einfo_idx; /******************************************************************************* * Grand array that holds the platform's topology information for state @@ -61,16 +59,6 @@ unsigned int psci_ns_einfo_idx; aff_map_node_t psci_aff_map[PSCI_NUM_AFFS] __attribute__ ((section("tzfw_coherent_mem"))); -/******************************************************************************* - * In a system, a certain number of affinity instances are present at an - * affinity level. The cumulative number of instances across all levels are - * stored in 'psci_aff_map'. The topology tree has been flattenned into this - * array. To retrieve nodes, information about the extents of each affinity - * level i.e. start index and end index needs to be present. 'psci_aff_limits' - * stores this information. - ******************************************************************************/ -aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1]; - /******************************************************************************* * Pointer to functions exported by the platform to complete power mgmt. ops ******************************************************************************/ diff --git a/services/std_svc/psci/psci_private.h b/services/std_svc/psci/psci_private.h index 1210b7ebf5..747a2d4e64 100644 --- a/services/std_svc/psci/psci_private.h +++ b/services/std_svc/psci/psci_private.h @@ -86,12 +86,8 @@ typedef unsigned int (*afflvl_power_on_finisher_t)(unsigned long, ******************************************************************************/ extern suspend_context_t psci_suspend_context[PSCI_NUM_AFFS]; extern ns_entry_info_t psci_ns_entry_info[PSCI_NUM_AFFS]; -extern unsigned int psci_ns_einfo_idx; -extern aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1]; extern const plat_pm_ops_t *psci_plat_pm_ops; extern aff_map_node_t psci_aff_map[PSCI_NUM_AFFS]; -extern afflvl_power_on_finisher_t psci_afflvl_off_finish_handlers[]; -extern afflvl_power_on_finisher_t psci_afflvl_sus_finish_handlers[]; /******************************************************************************* * SPD's power management hooks registered with PSCI diff --git a/services/std_svc/psci/psci_setup.c b/services/std_svc/psci/psci_setup.c index b958fa2e60..a1587b7f3a 100644 --- a/services/std_svc/psci/psci_setup.c +++ b/services/std_svc/psci/psci_setup.c @@ -47,6 +47,22 @@ ******************************************************************************/ static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT]; +/******************************************************************************* + * In a system, a certain number of affinity instances are present at an + * affinity level. The cumulative number of instances across all levels are + * stored in 'psci_aff_map'. The topology tree has been flattenned into this + * array. To retrieve nodes, information about the extents of each affinity + * level i.e. start index and end index needs to be present. 'psci_aff_limits' + * stores this information. + ******************************************************************************/ +static aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1]; + +/******************************************************************************* + * 'psci_ns_einfo_idx' keeps track of the next free index in the + * 'psci_ns_entry_info' & 'psci_suspend_context' arrays. + ******************************************************************************/ +static unsigned int psci_ns_einfo_idx; + /******************************************************************************* * Routines for retrieving the node corresponding to an affinity level instance * in the mpidr. The first one uses binary search to find the node corresponding From 5f0cdb059d7d5c3a8a834074a7f236b85d014dde Mon Sep 17 00:00:00 2001 From: Dan Handley Date: Wed, 14 May 2014 17:44:19 +0100 Subject: [PATCH 3/8] Split platform.h into separate headers Previously, platform.h contained many declarations and definitions used for different purposes. This file has been split so that: * Platform definitions used by common code that must be defined by the platform are now in platform_def.h. The exact include path is exported through $PLAT_INCLUDES in the platform makefile. * Platform definitions specific to the FVP platform are now in /plat/fvp/fvp_def.h. * Platform API declarations specific to the FVP platform are now in /plat/fvp/fvp_private.h. * The remaining platform API declarations that must be ported by each platform are still in platform.h but this file has been moved to /include/plat/common since this can be shared by all platforms. Change-Id: Ieb3bb22fbab3ee8027413c6b39a783534aee474a --- Makefile | 2 +- bl1/bl1.ld.S | 2 +- bl1/bl1_main.c | 1 + bl2/bl2.ld.S | 2 +- bl2/bl2_main.c | 1 + bl31/aarch64/runtime_exceptions.S | 2 +- bl31/bl31.ld.S | 2 +- bl31/context_mgmt.c | 1 + bl32/tsp/tsp.ld.S | 2 +- bl32/tsp/tsp_interrupt.c | 1 + bl32/tsp/tsp_main.c | 1 + bl32/tsp/tsp_timer.c | 1 + drivers/arm/cci400/cci400.c | 2 +- drivers/arm/pl011/pl011.c | 1 - drivers/arm/pl011/pl011_console.c | 1 - drivers/io/io_fip.c | 2 + include/bl32/payloads/tsp.h | 2 +- include/drivers/io_driver.h | 2 +- include/lib/aarch64/arch.h | 15 + include/lib/bakery_lock.h | 2 +- include/plat/common/platform.h | 129 ++++++ lib/aarch64/xlat_tables.c | 2 +- lib/locks/bakery/bakery_lock.c | 1 + plat/common/aarch64/platform_helpers.S | 2 +- plat/common/aarch64/platform_mp_stack.S | 2 +- plat/common/aarch64/platform_up_stack.S | 2 +- plat/fvp/aarch64/plat_common.c | 1 + plat/fvp/aarch64/plat_helpers.S | 2 +- plat/fvp/bl1_plat_setup.c | 3 + plat/fvp/bl2_plat_setup.c | 3 + plat/fvp/bl31_plat_setup.c | 2 + plat/fvp/bl32_plat_setup.c | 2 + plat/fvp/drivers/pwrc/fvp_pwrc.c | 1 + plat/fvp/fvp_def.h | 234 +++++++++++ plat/fvp/fvp_private.h | 92 ++++ plat/fvp/include/plat_macros.S | 2 +- plat/fvp/include/platform_def.h | 180 ++++++++ plat/fvp/plat_gic.c | 2 + plat/fvp/plat_io_storage.c | 2 +- plat/fvp/plat_pm.c | 3 + plat/fvp/plat_security.c | 5 +- plat/fvp/plat_topology.c | 2 +- plat/fvp/platform.h | 536 ------------------------ services/spd/tspd/tspd_common.c | 1 - services/spd/tspd/tspd_pm.c | 1 + services/spd/tspd/tspd_private.h | 2 +- services/std_svc/psci/psci_afflvl_on.c | 1 + services/std_svc/psci/psci_common.c | 1 + 48 files changed, 701 insertions(+), 560 deletions(-) create mode 100644 include/plat/common/platform.h create mode 100644 plat/fvp/fvp_def.h create mode 100644 plat/fvp/fvp_private.h create mode 100644 plat/fvp/include/platform_def.h delete mode 100644 plat/fvp/platform.h diff --git a/Makefile b/Makefile index 1069cd5ae0..22f1fd6bf4 100644 --- a/Makefile +++ b/Makefile @@ -160,9 +160,9 @@ INCLUDES += -Iinclude/bl1 \ -Iinclude/drivers/arm \ -Iinclude/lib \ -Iinclude/lib/aarch64 \ + -Iinclude/plat/common \ -Iinclude/stdlib \ -Iinclude/stdlib/sys \ - -Iplat/${PLAT} \ ${PLAT_INCLUDES} \ ${SPD_INCLUDES} diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index 1af2a32deb..967ba328c3 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index da81839b8d..6028f4f12e 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include "bl1_private.h" diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index 9f02e92c9c..e348d4fc9f 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c index 81fecd676e..55ae3c0e05 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include "bl2_private.h" diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 4789b33ba3..7e119c58cb 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include .globl runtime_exceptions diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 068d318162..15017429b8 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) diff --git a/bl31/context_mgmt.c b/bl31/context_mgmt.c index 2e7e62d7bb..b3dcf2d11d 100644 --- a/bl31/context_mgmt.c +++ b/bl31/context_mgmt.c @@ -37,6 +37,7 @@ #include #include #include +#include #include /******************************************************************************* diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index c72fefbdae..187915b612 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c index 5719c063ef..ac45d7afa6 100644 --- a/bl32/tsp/tsp_interrupt.c +++ b/bl32/tsp/tsp_interrupt.c @@ -34,6 +34,7 @@ #include #include #include +#include /******************************************************************************* * This function updates the TSP statistics for FIQs handled synchronously i.e diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index ad7ee0a207..05737aef6f 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c index f66ff9fa5a..366640f40c 100644 --- a/bl32/tsp/tsp_timer.c +++ b/bl32/tsp/tsp_timer.c @@ -29,6 +29,7 @@ */ #include #include +#include #include /******************************************************************************* diff --git a/drivers/arm/cci400/cci400.c b/drivers/arm/cci400/cci400.c index 02f7f9556e..af10f21427 100644 --- a/drivers/arm/cci400/cci400.c +++ b/drivers/arm/cci400/cci400.c @@ -30,7 +30,7 @@ #include #include -#include +#include static inline unsigned long get_slave_iface_base(unsigned long mpidr) { diff --git a/drivers/arm/pl011/pl011.c b/drivers/arm/pl011/pl011.c index f12bd23d0c..e296c23fee 100644 --- a/drivers/arm/pl011/pl011.c +++ b/drivers/arm/pl011/pl011.c @@ -29,7 +29,6 @@ */ #include -#include #include void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate) diff --git a/drivers/arm/pl011/pl011_console.c b/drivers/arm/pl011/pl011_console.c index 06e357f9e6..0e82aa21b7 100644 --- a/drivers/arm/pl011/pl011_console.c +++ b/drivers/arm/pl011/pl011_console.c @@ -30,7 +30,6 @@ #include #include -#include #include static unsigned long uart_base; diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c index 8ed7f47314..36788a2485 100644 --- a/drivers/io/io_fip.c +++ b/drivers/io/io_fip.c @@ -29,6 +29,7 @@ */ #include +#include #include #include #include @@ -36,6 +37,7 @@ #include #include #include +#include #include #include #include diff --git a/include/bl32/payloads/tsp.h b/include/bl32/payloads/tsp.h index 237ad48304..2db3b34676 100644 --- a/include/bl32/payloads/tsp.h +++ b/include/bl32/payloads/tsp.h @@ -113,7 +113,7 @@ #ifndef __ASSEMBLY__ #include -#include /* For CACHE_WRITEBACK_GRANULE */ +#include /* For CACHE_WRITEBACK_GRANULE */ #include #include diff --git a/include/drivers/io_driver.h b/include/drivers/io_driver.h index f34c71d554..867abbfa32 100644 --- a/include/drivers/io_driver.h +++ b/include/drivers/io_driver.h @@ -32,7 +32,7 @@ #define __IO_DRIVER_H__ #include -#include /* For MAX_IO_DEVICES */ +#include /* For MAX_IO_DEVICES */ #include diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 920dfc9bbc..d89b4fe9db 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -394,4 +394,19 @@ #define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK +/******************************************************************************* + * Definitions of register offsets and fields in the CNTCTLBase Frame of the + * system level implementation of the Generic Timer. + ******************************************************************************/ +#define CNTNSAR 0x4 +#define CNTNSAR_NS_SHIFT(x) x + +#define CNTACR_BASE(x) (0x40 + (x << 2)) +#define CNTACR_RPCT_SHIFT 0x0 +#define CNTACR_RVCT_SHIFT 0x1 +#define CNTACR_RFRQ_SHIFT 0x2 +#define CNTACR_RVOFF_SHIFT 0x3 +#define CNTACR_RWVT_SHIFT 0x4 +#define CNTACR_RWPT_SHIFT 0x5 + #endif /* __ARCH_H__ */ diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h index e6744a51ef..037fa7d184 100644 --- a/include/lib/bakery_lock.h +++ b/include/lib/bakery_lock.h @@ -31,7 +31,7 @@ #ifndef __BAKERY_LOCK_H__ #define __BAKERY_LOCK_H__ -#include +#include #define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h new file mode 100644 index 0000000000..b3f6806eff --- /dev/null +++ b/include/plat/common/platform.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +#include + + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct plat_pm_ops; +struct meminfo; +struct image_info; +struct entry_point_info; + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void bl1_plat_arch_setup(void); +void bl2_plat_arch_setup(void); +void bl31_plat_arch_setup(void); +int platform_setup_pm(const struct plat_pm_ops **); +unsigned int platform_get_core_pos(unsigned long mpidr); +void enable_mmu_el1(void); +void enable_mmu_el3(void); +void configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); +void configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); +void plat_report_exception(unsigned long); +unsigned long plat_get_ns_image_entrypoint(void); +unsigned long platform_get_stack(unsigned long mpidr); +uint64_t plat_get_syscnt_freq(void); +uint32_t ic_get_pending_interrupt_id(void); +uint32_t ic_get_pending_interrupt_type(void); +uint32_t ic_acknowledge_interrupt(void); +uint32_t ic_get_interrupt_type(uint32_t id); +void ic_end_of_interrupt(uint32_t id); +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state); + +int plat_get_max_afflvl(void); +unsigned int plat_get_aff_count(unsigned int, unsigned long); +unsigned int plat_get_aff_state(unsigned int, unsigned long); +int plat_get_image_source(const char *image_name, + uintptr_t *dev_handle, + uintptr_t *image_spec); + +/* + * Before calling this function BL2 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL2 and set SPSR and security state. + * On FVP we are only setting the security state, entrypoint + */ +void bl1_plat_set_bl2_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* + * Before calling this function BL31 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL31 and set SPSR and security state. + * On FVP we are only setting the security state, entrypoint + */ +void bl2_plat_set_bl31_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* + * Before calling this function BL32 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL32 and set SPSR and security state. + * On FVP we are only setting the security state, entrypoint + */ +void bl2_plat_set_bl32_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* + * Before calling this function BL33 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL33 and set SPSR and security state. + * On FVP we are only setting the security state, entrypoint + */ +void bl2_plat_set_bl33_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL32 */ +void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); + +/* Gets the memory layout for BL33 */ +void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); + + +#endif /* __PLATFORM_H__ */ diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c index 48b07149be..4e935a50e3 100644 --- a/lib/aarch64/xlat_tables.c +++ b/lib/aarch64/xlat_tables.c @@ -29,7 +29,7 @@ */ #include -#include +#include #include #include diff --git a/lib/locks/bakery/bakery_lock.c b/lib/locks/bakery/bakery_lock.c index 6d4ab87bb0..4e148b5aab 100644 --- a/lib/locks/bakery/bakery_lock.c +++ b/lib/locks/bakery/bakery_lock.c @@ -31,6 +31,7 @@ #include #include #include +#include #include /* diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S index 7e201213fe..f6ac13ebb0 100644 --- a/plat/common/aarch64/platform_helpers.S +++ b/plat/common/aarch64/platform_helpers.S @@ -30,7 +30,7 @@ #include #include -#include +#include .weak platform_get_core_pos diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S index ebbf509b4b..801ec7fab6 100644 --- a/plat/common/aarch64/platform_mp_stack.S +++ b/plat/common/aarch64/platform_mp_stack.S @@ -30,7 +30,7 @@ #include #include -#include +#include .local pcpu_dv_mem_stack diff --git a/plat/common/aarch64/platform_up_stack.S b/plat/common/aarch64/platform_up_stack.S index 880793d890..45a96a6469 100644 --- a/plat/common/aarch64/platform_up_stack.S +++ b/plat/common/aarch64/platform_up_stack.S @@ -30,7 +30,7 @@ #include #include -#include +#include .local pcpu_dv_mem_stack diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/plat_common.c index 2845f3e4fb..f0a06d83e4 100644 --- a/plat/fvp/aarch64/plat_common.c +++ b/plat/fvp/aarch64/plat_common.c @@ -37,6 +37,7 @@ #include #include #include +#include "../fvp_def.h" /******************************************************************************* * This array holds the characteristics of the differences between the three diff --git a/plat/fvp/aarch64/plat_helpers.S b/plat/fvp/aarch64/plat_helpers.S index f1c2c09b6f..fbb2fce36a 100644 --- a/plat/fvp/aarch64/plat_helpers.S +++ b/plat/fvp/aarch64/plat_helpers.S @@ -32,8 +32,8 @@ #include #include #include -#include #include "../drivers/pwrc/fvp_pwrc.h" +#include "../fvp_def.h" .globl platform_get_entrypoint .globl plat_secondary_cold_boot_setup diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_plat_setup.c index 45eb754005..5fbebc163c 100644 --- a/plat/fvp/bl1_plat_setup.c +++ b/plat/fvp/bl1_plat_setup.c @@ -35,6 +35,9 @@ #include #include #include +#include +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c index cf987ff7c4..87efe28f96 100644 --- a/plat/fvp/bl2_plat_setup.c +++ b/plat/fvp/bl2_plat_setup.c @@ -34,7 +34,10 @@ #include #include #include +#include #include +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c index 7b60a780a0..d1e16bd522 100644 --- a/plat/fvp/bl31_plat_setup.c +++ b/plat/fvp/bl31_plat_setup.c @@ -38,6 +38,8 @@ #include #include #include "drivers/pwrc/fvp_pwrc.h" +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout diff --git a/plat/fvp/bl32_plat_setup.c b/plat/fvp/bl32_plat_setup.c index 772e972fa0..7930314278 100644 --- a/plat/fvp/bl32_plat_setup.c +++ b/plat/fvp/bl32_plat_setup.c @@ -33,6 +33,8 @@ #include #include #include +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout diff --git a/plat/fvp/drivers/pwrc/fvp_pwrc.c b/plat/fvp/drivers/pwrc/fvp_pwrc.c index 7a7f5168ad..d1feecef42 100644 --- a/plat/fvp/drivers/pwrc/fvp_pwrc.c +++ b/plat/fvp/drivers/pwrc/fvp_pwrc.c @@ -30,6 +30,7 @@ #include #include +#include "../../fvp_def.h" #include "fvp_pwrc.h" /* diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h new file mode 100644 index 0000000000..9072a220b0 --- /dev/null +++ b/plat/fvp/fvp_def.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_DEF_H__ +#define __FVP_DEF_H__ + +#include /* for TZROM_SIZE */ + + +/* Firmware Image Package */ +#define FIP_IMAGE_NAME "fip.bin" + +/* Constants for accessing platform configuration */ +#define CONFIG_GICD_ADDR 0 +#define CONFIG_GICC_ADDR 1 +#define CONFIG_GICH_ADDR 2 +#define CONFIG_GICV_ADDR 3 +#define CONFIG_MAX_AFF0 4 +#define CONFIG_MAX_AFF1 5 +/* Indicate whether the CPUECTLR SMP bit should be enabled. */ +#define CONFIG_CPU_SETUP 6 +#define CONFIG_BASE_MMAP 7 +/* Indicates whether CCI should be enabled on the platform. */ +#define CONFIG_HAS_CCI 8 +#define CONFIG_HAS_TZC 9 +#define CONFIG_LIMIT 10 + +/******************************************************************************* + * FVP memory map related constants + ******************************************************************************/ + +#define FLASH0_BASE 0x08000000 +#define FLASH0_SIZE TZROM_SIZE + +#define FLASH1_BASE 0x0c000000 +#define FLASH1_SIZE 0x04000000 + +#define PSRAM_BASE 0x14000000 +#define PSRAM_SIZE 0x04000000 + +#define VRAM_BASE 0x18000000 +#define VRAM_SIZE 0x02000000 + +/* Aggregate of all devices in the first GB */ +#define DEVICE0_BASE 0x1a000000 +#define DEVICE0_SIZE 0x12200000 + +#define DEVICE1_BASE 0x2f000000 +#define DEVICE1_SIZE 0x200000 + +#define NSRAM_BASE 0x2e000000 +#define NSRAM_SIZE 0x10000 + +#define MBOX_OFF 0x1000 + +/* Base address where parameters to BL31 are stored */ +#define PARAMS_BASE TZDRAM_BASE + +#define DRAM1_BASE 0x80000000ull +#define DRAM1_SIZE 0x80000000ull +#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1) +#define DRAM1_SEC_SIZE 0x01000000ull + +#define DRAM_BASE DRAM1_BASE +#define DRAM_SIZE DRAM1_SIZE + +#define DRAM2_BASE 0x880000000ull +#define DRAM2_SIZE 0x780000000ull +#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1) + +#define PCIE_EXP_BASE 0x40000000 +#define TZRNG_BASE 0x7fe60000 +#define TZNVCTR_BASE 0x7fe70000 +#define TZROOTKEY_BASE 0x7fe80000 + +/* Memory mapped Generic timer interfaces */ +#define SYS_CNTCTL_BASE 0x2a430000 +#define SYS_CNTREAD_BASE 0x2a800000 +#define SYS_TIMCTL_BASE 0x2a810000 + +/* V2M motherboard system registers & offsets */ +#define VE_SYSREGS_BASE 0x1c010000 +#define V2M_SYS_ID 0x0 +#define V2M_SYS_LED 0x8 +#define V2M_SYS_CFGDATA 0xa0 +#define V2M_SYS_CFGCTRL 0xa4 + +/* Load address of BL33 in the FVP port */ +#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */ + +/* + * V2M sysled bit definitions. The values written to this + * register are defined in arch.h & runtime_svc.h. Only + * used by the primary cpu to diagnose any cold boot issues. + * + * SYS_LED[0] - Security state (S=0/NS=1) + * SYS_LED[2:1] - Exception Level (EL3-EL0) + * SYS_LED[7:3] - Exception Class (Sync/Async & origin) + * + */ +#define SYS_LED_SS_SHIFT 0x0 +#define SYS_LED_EL_SHIFT 0x1 +#define SYS_LED_EC_SHIFT 0x3 + +#define SYS_LED_SS_MASK 0x1 +#define SYS_LED_EL_MASK 0x3 +#define SYS_LED_EC_MASK 0x1f + +/* V2M sysid register bits */ +#define SYS_ID_REV_SHIFT 27 +#define SYS_ID_HBI_SHIFT 16 +#define SYS_ID_BLD_SHIFT 12 +#define SYS_ID_ARCH_SHIFT 8 +#define SYS_ID_FPGA_SHIFT 0 + +#define SYS_ID_REV_MASK 0xf +#define SYS_ID_HBI_MASK 0xfff +#define SYS_ID_BLD_MASK 0xf +#define SYS_ID_ARCH_MASK 0xf +#define SYS_ID_FPGA_MASK 0xff + +#define SYS_ID_BLD_LENGTH 4 + +#define REV_FVP 0x0 +#define HBI_FVP_BASE 0x020 +#define HBI_FOUNDATION 0x010 + +#define BLD_GIC_VE_MMAP 0x0 +#define BLD_GIC_A53A57_MMAP 0x1 + +#define ARCH_MODEL 0x1 + +/* FVP Power controller base address*/ +#define PWRC_BASE 0x1c100000 + + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define CCI400_BASE 0x2c090000 +#define CCI400_SL_IFACE_CLUSTER0 3 +#define CCI400_SL_IFACE_CLUSTER1 4 +#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ + CCI400_SL_IFACE_CLUSTER1 : \ + CCI400_SL_IFACE_CLUSTER0) + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +/* VE compatible GIC memory map */ +#define VE_GICD_BASE 0x2c001000 +#define VE_GICC_BASE 0x2c002000 +#define VE_GICH_BASE 0x2c004000 +#define VE_GICV_BASE 0x2c006000 + +/* Base FVP compatible GIC memory map */ +#define BASE_GICD_BASE 0x2f000000 +#define BASE_GICR_BASE 0x2f100000 +#define BASE_GICC_BASE 0x2c000000 +#define BASE_GICH_BASE 0x2c010000 +#define BASE_GICV_BASE 0x2c02f000 + +#define IRQ_TZ_WDOG 56 +#define IRQ_SEC_PHY_TIMER 29 +#define IRQ_SEC_SGI_0 8 +#define IRQ_SEC_SGI_1 9 +#define IRQ_SEC_SGI_2 10 +#define IRQ_SEC_SGI_3 11 +#define IRQ_SEC_SGI_4 12 +#define IRQ_SEC_SGI_5 13 +#define IRQ_SEC_SGI_6 14 +#define IRQ_SEC_SGI_7 15 +#define IRQ_SEC_SGI_8 16 + +/******************************************************************************* + * PL011 related constants + ******************************************************************************/ +#define PL011_UART0_BASE 0x1c090000 +#define PL011_UART1_BASE 0x1c0a0000 +#define PL011_UART2_BASE 0x1c0b0000 +#define PL011_UART3_BASE 0x1c0c0000 + +/******************************************************************************* + * TrustZone address space controller related constants + ******************************************************************************/ +#define TZC400_BASE 0x2a4a0000 + +/* + * The NSAIDs for this platform as used to program the TZC400. + */ + +/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */ +#define FVP_AID_WIDTH 4 + +/* NSAIDs used by devices in TZC filter 0 on FVP */ +#define FVP_NSAID_DEFAULT 0 +#define FVP_NSAID_PCI 1 +#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ +#define FVP_NSAID_AP 9 /* Application Processors */ +#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ + +/* NSAIDs used by devices in TZC filter 2 on FVP */ +#define FVP_NSAID_HDLCD0 2 +#define FVP_NSAID_CLCD 7 + + +#endif /* __FVP_DEF_H__ */ diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h new file mode 100644 index 0000000000..cde1fd0abc --- /dev/null +++ b/plat/fvp/fvp_private.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_PRIVATE_H__ +#define __FVP_PRIVATE_H__ + +#include +#include + + +typedef volatile struct mailbox { + unsigned long value + __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE))); +} mailbox_t; + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL31 e.g. while passing control to it from BL2 which is bl31_params + * and bl31_plat_params and its elements + ******************************************************************************/ +typedef struct bl2_to_bl31_params_mem { + bl31_params_t bl31_params; + image_info_t bl31_image_info; + image_info_t bl32_image_info; + image_info_t bl33_image_info; + entry_point_info_t bl33_ep_info; + entry_point_info_t bl32_ep_info; + entry_point_info_t bl31_ep_info; +} bl2_to_bl31_params_mem_t; + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +unsigned long platform_get_cfgvar(unsigned int); +int platform_config_setup(void); + +#if RESET_TO_BL31 +void plat_get_entry_point_info(unsigned long target_security, + struct entry_point_info *target_entry_info); +#endif +void fvp_cci_setup(void); + +/* Declarations for fvp_gic.c */ +void gic_cpuif_deactivate(unsigned int); +void gic_cpuif_setup(unsigned int); +void gic_pcpu_distif_setup(unsigned int); +void gic_setup(void); + +/* Declarations for fvp_topology.c */ +int plat_setup_topology(void); + +/* Declarations for plat_io_storage.c */ +void io_setup(void); + +/* Declarations for plat_security.c */ +void plat_security_setup(void); + +/* Sets the entrypoint for BL32 */ +void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep); + +/* Sets the entrypoint for BL33 */ +void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep); + + +#endif /* __FVP_PRIVATE_H__ */ diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S index 0b9b2e2669..1fa50fd14f 100644 --- a/plat/fvp/include/plat_macros.S +++ b/plat/fvp/include/plat_macros.S @@ -29,7 +29,7 @@ */ #include -#include +#include "../fvp_def.h" .section .rodata.gic_reg_name, "aS" gic_regs: .asciz "gic_iar", "gic_ctlr", "" diff --git a/plat/fvp/include/platform_def.h b/plat/fvp/include/platform_def.h new file mode 100644 index 0000000000..46a9f24c22 --- /dev/null +++ b/plat/fvp/include/platform_def.h @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include + + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#define PLATFORM_STACK_SIZE 0x800 + +/* Size of coherent stacks for debug and release builds */ +#if DEBUG +#define PCPU_DV_MEM_STACK_SIZE 0x400 +#else +#define PCPU_DV_MEM_STACK_SIZE 0x300 +#endif + +#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r" + +/* Trusted Boot Firmware BL2 */ +#define BL2_IMAGE_NAME "bl2.bin" + +/* EL3 Runtime Firmware BL31 */ +#define BL31_IMAGE_NAME "bl31.bin" + +/* Secure Payload BL32 (Trusted OS) */ +#define BL32_IMAGE_NAME "bl32.bin" + +/* Non-Trusted Firmware BL33 */ +#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ + +#define PLATFORM_CACHE_LINE_SIZE 64 +#define PLATFORM_CLUSTER_COUNT 2ull +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PRIMARY_CPU 0x0 +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define TZROM_BASE 0x00000000 +#define TZROM_SIZE 0x04000000 + +#define TZRAM_BASE 0x04000000 +#define TZRAM_SIZE 0x40000 + +/* Location of trusted dram on the base fvp */ +#define TZDRAM_BASE 0x06000000 +#define TZDRAM_SIZE 0x02000000 + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE TZROM_BASE +#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) +#define BL1_RW_BASE TZRAM_BASE +#define BL1_RW_LIMIT BL31_BASE + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000) +#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#define BL31_BASE (TZRAM_BASE + 0x6000) +#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM +#define BL31_LIMIT BL32_BASE +#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM +#define BL31_LIMIT BL2_BASE +#endif + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +/* + * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM. + */ +#define TSP_IN_TZRAM 0 +#define TSP_IN_TZDRAM 1 + +#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM +# define TSP_SEC_MEM_BASE TZRAM_BASE +# define TSP_SEC_MEM_SIZE TZRAM_SIZE +# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000) +# define BL32_LIMIT BL2_BASE +#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM +# define TSP_SEC_MEM_BASE TZDRAM_BASE +# define TSP_SEC_MEM_SIZE TZDRAM_SIZE +# define BL32_BASE (TZDRAM_BASE + 0x2000) +# define BL32_LIMIT (TZDRAM_BASE + (1 << 21)) +#else +# error "Unsupported TSP_RAM_LOCATION_ID value" +#endif + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 3 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * ID of the secure physical generic timer interrupt. + ******************************************************************************/ +#define IRQ_SEC_PHY_TIMER 29 + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define CCI400_BASE 0x2c090000 +#define CCI400_SL_IFACE_CLUSTER0 3 +#define CCI400_SL_IFACE_CLUSTER1 4 +#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ + CCI400_SL_IFACE_CLUSTER1 : \ + CCI400_SL_IFACE_CLUSTER0) + + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/fvp/plat_gic.c b/plat/fvp/plat_gic.c index 7dec404f8e..6b29723bb0 100644 --- a/plat/fvp/plat_gic.c +++ b/plat/fvp/plat_gic.c @@ -37,6 +37,8 @@ #include #include #include +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * This function does some minimal GICv3 configuration. The Firmware itself does diff --git a/plat/fvp/plat_io_storage.c b/plat/fvp/plat_io_storage.c index aac8a9604f..baa98ffe9e 100644 --- a/plat/fvp/plat_io_storage.c +++ b/plat/fvp/plat_io_storage.c @@ -35,9 +35,9 @@ #include #include #include -#include #include /* For FOPEN_MODE_... */ #include +#include "fvp_def.h" /* IO devices */ static io_plat_data_t io_data; diff --git a/plat/fvp/plat_pm.c b/plat/fvp/plat_pm.c index c47cdb0fc5..ad4ce7939e 100644 --- a/plat/fvp/plat_pm.c +++ b/plat/fvp/plat_pm.c @@ -34,8 +34,11 @@ #include #include #include +#include #include #include "drivers/pwrc/fvp_pwrc.h" +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * FVP handler called when an affinity instance is about to enter standby. diff --git a/plat/fvp/plat_security.c b/plat/fvp/plat_security.c index 9da5612203..976f75e98e 100644 --- a/plat/fvp/plat_security.c +++ b/plat/fvp/plat_security.c @@ -29,9 +29,10 @@ */ #include -#include -#include #include +#include +#include "fvp_def.h" +#include "fvp_private.h" /* Used to improve readability for configuring regions. */ #define FILTER_SHIFT(filter) (1 << filter) diff --git a/plat/fvp/plat_topology.c b/plat/fvp/plat_topology.c index 04b409ecb1..f06b4f7470 100644 --- a/plat/fvp/plat_topology.c +++ b/plat/fvp/plat_topology.c @@ -29,7 +29,7 @@ */ #include -#include +#include /* TODO: Reusing psci error codes & state information. Get our own! */ #include #include "drivers/pwrc/fvp_pwrc.h" diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h deleted file mode 100644 index 0e3de5fc10..0000000000 --- a/plat/fvp/platform.h +++ /dev/null @@ -1,536 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __PLATFORM_H__ -#define __PLATFORM_H__ - -#include -#include - - -/******************************************************************************* - * Platform binary types for linking - ******************************************************************************/ -#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" -#define PLATFORM_LINKER_ARCH aarch64 - -/******************************************************************************* - * Generic platform constants - ******************************************************************************/ - -/* Size of cacheable stacks */ -#define PLATFORM_STACK_SIZE 0x800 - -/* Size of coherent stacks for debug and release builds */ -#if DEBUG -#define PCPU_DV_MEM_STACK_SIZE 0x400 -#else -#define PCPU_DV_MEM_STACK_SIZE 0x300 -#endif - -#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r" - -/* Trusted Boot Firmware BL2 */ -#define BL2_IMAGE_NAME "bl2.bin" - -/* EL3 Runtime Firmware BL31 */ -#define BL31_IMAGE_NAME "bl31.bin" - -/* Secure Payload BL32 (Trusted OS) */ -#define BL32_IMAGE_NAME "bl32.bin" - -/* Non-Trusted Firmware BL33 and its load address */ -#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ -#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */ - -/* Firmware Image Package */ -#define FIP_IMAGE_NAME "fip.bin" - -#define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_CLUSTER_COUNT 2ull -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 4 -#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ - PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PRIMARY_CPU 0x0 -#define MAX_IO_DEVICES 3 -#define MAX_IO_HANDLES 4 - -/* Constants for accessing platform configuration */ -#define CONFIG_GICD_ADDR 0 -#define CONFIG_GICC_ADDR 1 -#define CONFIG_GICH_ADDR 2 -#define CONFIG_GICV_ADDR 3 -#define CONFIG_MAX_AFF0 4 -#define CONFIG_MAX_AFF1 5 -/* Indicate whether the CPUECTLR SMP bit should be enabled. */ -#define CONFIG_CPU_SETUP 6 -#define CONFIG_BASE_MMAP 7 -/* Indicates whether CCI should be enabled on the platform. */ -#define CONFIG_HAS_CCI 8 -#define CONFIG_HAS_TZC 9 -#define CONFIG_LIMIT 10 - -/******************************************************************************* - * Platform memory map related constants - ******************************************************************************/ -#define TZROM_BASE 0x00000000 -#define TZROM_SIZE 0x04000000 - -#define TZRAM_BASE 0x04000000 -#define TZRAM_SIZE 0x40000 - -#define FLASH0_BASE 0x08000000 -#define FLASH0_SIZE TZROM_SIZE - -#define FLASH1_BASE 0x0c000000 -#define FLASH1_SIZE 0x04000000 - -#define PSRAM_BASE 0x14000000 -#define PSRAM_SIZE 0x04000000 - -#define VRAM_BASE 0x18000000 -#define VRAM_SIZE 0x02000000 - -/* Aggregate of all devices in the first GB */ -#define DEVICE0_BASE 0x1a000000 -#define DEVICE0_SIZE 0x12200000 - -#define DEVICE1_BASE 0x2f000000 -#define DEVICE1_SIZE 0x200000 - -#define NSRAM_BASE 0x2e000000 -#define NSRAM_SIZE 0x10000 - -/* Location of trusted dram on the base fvp */ -#define TZDRAM_BASE 0x06000000 -#define TZDRAM_SIZE 0x02000000 -#define MBOX_OFF 0x1000 - -/* Base address where parameters to BL31 are stored */ -#define PARAMS_BASE TZDRAM_BASE - - -#define DRAM1_BASE 0x80000000ull -#define DRAM1_SIZE 0x80000000ull -#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1) -#define DRAM1_SEC_SIZE 0x01000000ull - -#define DRAM_BASE DRAM1_BASE -#define DRAM_SIZE DRAM1_SIZE - -#define DRAM2_BASE 0x880000000ull -#define DRAM2_SIZE 0x780000000ull -#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1) - -#define PCIE_EXP_BASE 0x40000000 -#define TZRNG_BASE 0x7fe60000 -#define TZNVCTR_BASE 0x7fe70000 -#define TZROOTKEY_BASE 0x7fe80000 - -/* Memory mapped Generic timer interfaces */ -#define SYS_CNTCTL_BASE 0x2a430000 -#define SYS_CNTREAD_BASE 0x2a800000 -#define SYS_TIMCTL_BASE 0x2a810000 - -/* Counter timer module offsets */ -#define CNTNSAR 0x4 -#define CNTNSAR_NS_SHIFT(x) x - -#define CNTACR_BASE(x) (0x40 + (x << 2)) -#define CNTACR_RPCT_SHIFT 0x0 -#define CNTACR_RVCT_SHIFT 0x1 -#define CNTACR_RFRQ_SHIFT 0x2 -#define CNTACR_RVOFF_SHIFT 0x3 -#define CNTACR_RWVT_SHIFT 0x4 -#define CNTACR_RWPT_SHIFT 0x5 - -/* V2M motherboard system registers & offsets */ -#define VE_SYSREGS_BASE 0x1c010000 -#define V2M_SYS_ID 0x0 -#define V2M_SYS_LED 0x8 -#define V2M_SYS_CFGDATA 0xa0 -#define V2M_SYS_CFGCTRL 0xa4 - -/* - * V2M sysled bit definitions. The values written to this - * register are defined in arch.h & runtime_svc.h. Only - * used by the primary cpu to diagnose any cold boot issues. - * - * SYS_LED[0] - Security state (S=0/NS=1) - * SYS_LED[2:1] - Exception Level (EL3-EL0) - * SYS_LED[7:3] - Exception Class (Sync/Async & origin) - * - */ -#define SYS_LED_SS_SHIFT 0x0 -#define SYS_LED_EL_SHIFT 0x1 -#define SYS_LED_EC_SHIFT 0x3 - -#define SYS_LED_SS_MASK 0x1 -#define SYS_LED_EL_MASK 0x3 -#define SYS_LED_EC_MASK 0x1f - -/* V2M sysid register bits */ -#define SYS_ID_REV_SHIFT 27 -#define SYS_ID_HBI_SHIFT 16 -#define SYS_ID_BLD_SHIFT 12 -#define SYS_ID_ARCH_SHIFT 8 -#define SYS_ID_FPGA_SHIFT 0 - -#define SYS_ID_REV_MASK 0xf -#define SYS_ID_HBI_MASK 0xfff -#define SYS_ID_BLD_MASK 0xf -#define SYS_ID_ARCH_MASK 0xf -#define SYS_ID_FPGA_MASK 0xff - -#define SYS_ID_BLD_LENGTH 4 - -#define REV_FVP 0x0 -#define HBI_FVP_BASE 0x020 -#define HBI_FOUNDATION 0x010 - -#define BLD_GIC_VE_MMAP 0x0 -#define BLD_GIC_A53A57_MMAP 0x1 - -#define ARCH_MODEL 0x1 - -/* FVP Power controller base address*/ -#define PWRC_BASE 0x1c100000 - -/******************************************************************************* - * Platform specific per affinity states. Distinction between off and suspend - * is made to allow reporting of a suspended cpu as still being on e.g. in the - * affinity_info psci call. - ******************************************************************************/ -#define PLATFORM_MAX_AFF0 4 -#define PLATFORM_MAX_AFF1 2 -#define PLAT_AFF_UNK 0xff - -#define PLAT_AFF0_OFF 0x0 -#define PLAT_AFF0_ONPENDING 0x1 -#define PLAT_AFF0_SUSPEND 0x2 -#define PLAT_AFF0_ON 0x3 - -#define PLAT_AFF1_OFF 0x0 -#define PLAT_AFF1_ONPENDING 0x1 -#define PLAT_AFF1_SUSPEND 0x2 -#define PLAT_AFF1_ON 0x3 - -/******************************************************************************* - * BL1 specific defines. - * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of - * addresses. - ******************************************************************************/ -#define BL1_RO_BASE TZROM_BASE -#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) -#define BL1_RW_BASE TZRAM_BASE -#define BL1_RW_LIMIT BL31_BASE - -/******************************************************************************* - * BL2 specific defines. - ******************************************************************************/ -#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000) -#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE) - -/******************************************************************************* - * BL31 specific defines. - ******************************************************************************/ -#define BL31_BASE (TZRAM_BASE + 0x6000) -#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM -#define BL31_LIMIT BL32_BASE -#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM -#define BL31_LIMIT BL2_BASE -#endif - -/******************************************************************************* - * BL32 specific defines. - ******************************************************************************/ -/* - * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM. - */ -#define TSP_IN_TZRAM 0 -#define TSP_IN_TZDRAM 1 - -#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM -# define TSP_SEC_MEM_BASE TZRAM_BASE -# define TSP_SEC_MEM_SIZE TZRAM_SIZE -# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000) -# define BL32_LIMIT BL2_BASE -#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM -# define TSP_SEC_MEM_BASE TZDRAM_BASE -# define TSP_SEC_MEM_SIZE TZDRAM_SIZE -# define BL32_BASE (TZDRAM_BASE + 0x2000) -# define BL32_LIMIT (TZDRAM_BASE + (1 << 21)) -#else -# error "Unsupported TSP_RAM_LOCATION_ID value" -#endif - -/******************************************************************************* - * Platform specific page table and MMU setup constants - ******************************************************************************/ -#define ADDR_SPACE_SIZE (1ull << 32) -#define MAX_XLAT_TABLES 3 -#define MAX_MMAP_REGIONS 16 - - -/******************************************************************************* - * CCI-400 related constants - ******************************************************************************/ -#define CCI400_BASE 0x2c090000 -#define CCI400_SL_IFACE_CLUSTER0 3 -#define CCI400_SL_IFACE_CLUSTER1 4 -#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ - CCI400_SL_IFACE_CLUSTER1 : \ - CCI400_SL_IFACE_CLUSTER0) - -/******************************************************************************* - * GIC-400 & interrupt handling related constants - ******************************************************************************/ -/* VE compatible GIC memory map */ -#define VE_GICD_BASE 0x2c001000 -#define VE_GICC_BASE 0x2c002000 -#define VE_GICH_BASE 0x2c004000 -#define VE_GICV_BASE 0x2c006000 - -/* Base FVP compatible GIC memory map */ -#define BASE_GICD_BASE 0x2f000000 -#define BASE_GICR_BASE 0x2f100000 -#define BASE_GICC_BASE 0x2c000000 -#define BASE_GICH_BASE 0x2c010000 -#define BASE_GICV_BASE 0x2c02f000 - -#define IRQ_TZ_WDOG 56 -#define IRQ_SEC_PHY_TIMER 29 -#define IRQ_SEC_SGI_0 8 -#define IRQ_SEC_SGI_1 9 -#define IRQ_SEC_SGI_2 10 -#define IRQ_SEC_SGI_3 11 -#define IRQ_SEC_SGI_4 12 -#define IRQ_SEC_SGI_5 13 -#define IRQ_SEC_SGI_6 14 -#define IRQ_SEC_SGI_7 15 -#define IRQ_SEC_SGI_8 16 - -/******************************************************************************* - * PL011 related constants - ******************************************************************************/ -#define PL011_UART0_BASE 0x1c090000 -#define PL011_UART1_BASE 0x1c0a0000 -#define PL011_UART2_BASE 0x1c0b0000 -#define PL011_UART3_BASE 0x1c0c0000 - - -/******************************************************************************* - * TrustZone address space controller related constants - ******************************************************************************/ -#define TZC400_BASE 0x2a4a0000 - -/* - * The NSAIDs for this platform as used to program the TZC400. - */ - -/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */ -#define FVP_AID_WIDTH 4 - -/* NSAIDs used by devices in TZC filter 0 on FVP */ -#define FVP_NSAID_DEFAULT 0 -#define FVP_NSAID_PCI 1 -#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ -#define FVP_NSAID_AP 9 /* Application Processors */ -#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ - -/* NSAIDs used by devices in TZC filter 2 on FVP */ -#define FVP_NSAID_HDLCD0 2 -#define FVP_NSAID_CLCD 7 - - -/******************************************************************************* - * Declarations and constants to access the mailboxes safely. Each mailbox is - * aligned on the biggest cache line size in the platform. This is known only - * to the platform as it might have a combination of integrated and external - * caches. Such alignment ensures that two maiboxes do not sit on the same cache - * line at any cache level. They could belong to different cpus/clusters & - * get written while being protected by different locks causing corruption of - * a valid mailbox address. - ******************************************************************************/ -#define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -#ifndef __ASSEMBLY__ - -#include -#include - -typedef volatile struct mailbox { - unsigned long value - __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE))); -} mailbox_t; - -/******************************************************************************* - * Forward declarations - ******************************************************************************/ -struct plat_pm_ops; -struct meminfo; -struct bl31_params; -struct image_info; -struct entry_point_info; - - -/******************************************************************************* - * This structure represents the superset of information that is passed to - * BL31 e.g. while passing control to it from BL2 which is bl31_params - * and another platform specific params - ******************************************************************************/ -typedef struct bl2_to_bl31_params_mem { - struct bl31_params bl31_params; - struct image_info bl31_image_info; - struct image_info bl32_image_info; - struct image_info bl33_image_info; - struct entry_point_info bl33_ep_info; - struct entry_point_info bl32_ep_info; - struct entry_point_info bl31_ep_info; -} bl2_to_bl31_params_mem_t; - - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ -void bl1_plat_arch_setup(void); -void bl2_plat_arch_setup(void); -void bl31_plat_arch_setup(void); -int platform_setup_pm(const struct plat_pm_ops **); -unsigned int platform_get_core_pos(unsigned long mpidr); -void enable_mmu_el1(void); -void enable_mmu_el3(void); -void configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); -void configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); -unsigned long platform_get_cfgvar(unsigned int); -int platform_config_setup(void); -void plat_report_exception(unsigned long); -unsigned long plat_get_ns_image_entrypoint(void); -unsigned long platform_get_stack(unsigned long mpidr); -uint64_t plat_get_syscnt_freq(void); -#if RESET_TO_BL31 -void plat_get_entry_point_info(unsigned long target_security, - el_change_info_t *target_entry_info); -#endif -void fvp_cci_setup(void); - -/* Declarations for plat_gic.c */ -uint32_t ic_get_pending_interrupt_id(void); -uint32_t ic_get_pending_interrupt_type(void); -uint32_t ic_acknowledge_interrupt(void); -uint32_t ic_get_interrupt_type(uint32_t id); -void ic_end_of_interrupt(uint32_t id); -void gic_cpuif_deactivate(unsigned int); -void gic_cpuif_setup(unsigned int); -void gic_pcpu_distif_setup(unsigned int); -void gic_setup(void); -uint32_t plat_interrupt_type_to_line(uint32_t type, - uint32_t security_state); - -/* Declarations for plat_topology.c */ -int plat_setup_topology(void); -int plat_get_max_afflvl(void); -unsigned int plat_get_aff_count(unsigned int, unsigned long); -unsigned int plat_get_aff_state(unsigned int, unsigned long); - -/* Declarations for plat_io_storage.c */ -void io_setup(void); -int plat_get_image_source(const char *image_name, - uintptr_t *dev_handle, - uintptr_t *image_spec); - -/* Declarations for plat_security.c */ -void plat_security_setup(void); - -/* - * Before calling this function BL2 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL2 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ -void bl1_plat_set_bl2_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* - * Before calling this function BL31 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL31 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ -void bl2_plat_set_bl31_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* - * Before calling this function BL32 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL32 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ -void bl2_plat_set_bl32_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* - * Before calling this function BL33 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL33 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ -void bl2_plat_set_bl33_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* Gets the memory layout for BL32 */ -void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); - -/* Gets the memory layout for BL33 */ -void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); - -/* Sets the entrypoint for BL32 */ -void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep_info); - -/* Sets the entrypoint for BL33 */ -void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep_info); - - -#endif /*__ASSEMBLY__*/ - -#endif /* __PLATFORM_H__ */ diff --git a/services/spd/tspd/tspd_common.c b/services/spd/tspd/tspd_common.c index 2ca6a56af2..6b3592e3f0 100644 --- a/services/spd/tspd/tspd_common.c +++ b/services/spd/tspd/tspd_common.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include "tspd_private.h" diff --git a/services/spd/tspd/tspd_pm.c b/services/spd/tspd/tspd_pm.c index 2f20449452..ec4989df19 100644 --- a/services/spd/tspd/tspd_pm.c +++ b/services/spd/tspd/tspd_pm.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "tspd_private.h" diff --git a/services/spd/tspd/tspd_private.h b/services/spd/tspd/tspd_private.h index fb71922512..5d7bf4b6f4 100644 --- a/services/spd/tspd/tspd_private.h +++ b/services/spd/tspd/tspd_private.h @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include /******************************************************************************* diff --git a/services/std_svc/psci/psci_afflvl_on.c b/services/std_svc/psci/psci_afflvl_on.c index 360b2860f4..1e5828caca 100644 --- a/services/std_svc/psci/psci_afflvl_on.c +++ b/services/std_svc/psci/psci_afflvl_on.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include "psci_private.h" diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c index c61e87adfb..b1ee10da2e 100644 --- a/services/std_svc/psci/psci_common.c +++ b/services/std_svc/psci/psci_common.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "psci_private.h" /* From dec5e0d1da9fdfe68cea4fbeb096f93e43860493 Mon Sep 17 00:00:00 2001 From: Dan Handley Date: Thu, 15 May 2014 14:11:36 +0100 Subject: [PATCH 4/8] Move BL porting functions into platform.h Some platform porting functions were in BL specific header files. These have been moved to platform.h so that all porting functions are in the same place. The functions are now grouped by BL. Obsolete BL headers files have been removed. Also, the weak declaration of the init_bl2_mem_layout() function has been moved out the header file and into the source file (bl_common.c) using the more succinct #pragma syntax. This mitigates the risk of 2 weak definitions being created and the wrong one being picked up by the compiler. Change-Id: Ib19934939fd755f3e5a5a5bceec88da684308a83 --- bl1/bl1_main.c | 1 - bl2/bl2_main.c | 1 - bl31/bl31_main.c | 1 + bl32/tsp/tsp_main.c | 1 - common/bl_common.c | 5 +- include/bl1/bl1.h | 46 -------------- include/bl2/bl2.h | 66 ------------------- include/bl31/bl31.h | 4 -- include/bl32/bl32.h | 48 -------------- include/common/bl_common.h | 8 --- include/plat/common/platform.h | 112 +++++++++++++++++++++++++-------- plat/fvp/bl1_plat_setup.c | 1 - plat/fvp/bl2_plat_setup.c | 1 - plat/fvp/bl32_plat_setup.c | 2 - plat/fvp/fvp_private.h | 17 +++++ 15 files changed, 106 insertions(+), 208 deletions(-) delete mode 100644 include/bl1/bl1.h delete mode 100644 include/bl2/bl2.h delete mode 100644 include/bl32/bl32.h diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index 6028f4f12e..6771142e44 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c index 55ae3c0e05..46c70a1232 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index ff7caf1ddd..71c64643ef 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index 05737aef6f..eaabe613c4 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -30,7 +30,6 @@ #include #include -#include #include #include #include diff --git a/common/bl_common.c b/common/bl_common.c index 911ad4c129..3bc314c6ea 100644 --- a/common/bl_common.c +++ b/common/bl_common.c @@ -74,9 +74,10 @@ void change_security_state(unsigned int target_security_state) /******************************************************************************* - * The next function is a weak definition. Platform specific - * code can override it if it wishes to. + * The next function has a weak definition. Platform specific code can override + * it if it wishes to. ******************************************************************************/ +#pragma weak init_bl2_mem_layout /******************************************************************************* * Function that takes a memory layout into which BL2 has been either top or diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h deleted file mode 100644 index b1bbf244f9..0000000000 --- a/include/bl1/bl1.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL1_H__ -#define __BL1_H__ - - -/****************************************** - * Forward declarations - *****************************************/ -struct meminfo; - -/****************************************** - * Function prototypes - *****************************************/ -void bl1_platform_setup(void); -struct meminfo *bl1_plat_sec_mem_layout(void); - -#endif /* __BL1_H__ */ diff --git a/include/bl2/bl2.h b/include/bl2/bl2.h deleted file mode 100644 index fffe5a63b8..0000000000 --- a/include/bl2/bl2.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL2_H__ -#define __BL2_H__ - -/****************************************** - * Forward declarations - *****************************************/ -struct meminfo; -struct bl31_params; -struct entry_point_info; - -/****************************************** - * Function prototypes - *****************************************/ -void bl2_platform_setup(void); -struct meminfo *bl2_plat_sec_mem_layout(void); - -/******************************************************************************* - * This function returns a pointer to the shared memory that the platform has - * kept aside to pass trusted firmware related information that BL3-1 - * could need - ******************************************************************************/ -struct bl31_params *bl2_plat_get_bl31_params(void); - -/******************************************************************************* - * This function returns a pointer to the shared memory that the platform - * has kept to point to entry point information of BL31 to BL2 - ******************************************************************************/ -struct entry_point_info *bl2_plat_get_bl31_ep_info(void); - -/************************************************************************ - * This function flushes to main memory all the params that are - * passed to BL3-1 - **************************************************************************/ -void bl2_plat_flush_bl31_params(void); - -#endif /* __BL2_H__ */ diff --git a/include/bl31/bl31.h b/include/bl31/bl31.h index ef32568738..8d22dc98bb 100644 --- a/include/bl31/bl31.h +++ b/include/bl31/bl31.h @@ -37,7 +37,6 @@ * Forward declarations *****************************************/ struct entry_point_info; -struct bl31_parms; /******************************************************************************* * Function prototypes @@ -48,9 +47,6 @@ void bl31_set_next_image_type(uint32_t type); uint32_t bl31_get_next_image_type(void); void bl31_prepare_next_image_entry(); struct entry_point_info *bl31_get_next_image_info(uint32_t type); -void bl31_early_platform_setup(struct bl31_params *from_bl2, - void *plat_params_from_bl2); -void bl31_platform_setup(void); void bl31_register_bl32_init(int32_t (*)(void)); #endif /* __BL31_H__ */ diff --git a/include/bl32/bl32.h b/include/bl32/bl32.h deleted file mode 100644 index ede7c48e01..0000000000 --- a/include/bl32/bl32.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL32_H__ -#define __BL32_H__ - -#include - -/****************************************** - * Forward declarations - *****************************************/ -struct meminfo; - -/****************************************** - * Function prototypes - *****************************************/ -void bl32_platform_setup(void); -struct meminfo *bl32_plat_sec_mem_layout(void); -uint64_t bl32_main(void); - -#endif /* __BL32_H__ */ diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 79f2329b7b..2f3bade1ad 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -196,13 +196,6 @@ CASSERT(sizeof(unsigned long) == ******************************************************************************/ unsigned long page_align(unsigned long, unsigned); void change_security_state(unsigned int); -void init_bl2_mem_layout(meminfo_t *, - meminfo_t *, - unsigned int, - unsigned long) __attribute__((weak)); -void init_bl31_mem_layout(const meminfo_t *, - meminfo_t *, - unsigned int) __attribute__((weak)); unsigned long image_size(const char *); int load_image(meminfo_t *, const char *, @@ -210,7 +203,6 @@ int load_image(meminfo_t *, unsigned long, image_info_t *, entry_point_info_t *); -unsigned long *get_el_change_mem_ptr(void); extern const char build_message[]; #endif /*__ASSEMBLY__*/ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index b3f6806eff..7e2e91201f 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -41,33 +41,25 @@ struct plat_pm_ops; struct meminfo; struct image_info; struct entry_point_info; +struct bl31_params; /******************************************************************************* - * Function and variable prototypes + * Function declarations ******************************************************************************/ -void bl1_plat_arch_setup(void); -void bl2_plat_arch_setup(void); -void bl31_plat_arch_setup(void); -int platform_setup_pm(const struct plat_pm_ops **); -unsigned int platform_get_core_pos(unsigned long mpidr); +/******************************************************************************* + * Mandatory common functions + ******************************************************************************/ +uint64_t plat_get_syscnt_freq(void); void enable_mmu_el1(void); void enable_mmu_el3(void); -void configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long, - unsigned long, - unsigned long, - unsigned long); -void configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long, - unsigned long, - unsigned long, - unsigned long); -void plat_report_exception(unsigned long); +int plat_get_image_source(const char *image_name, + uintptr_t *dev_handle, + uintptr_t *image_spec); unsigned long plat_get_ns_image_entrypoint(void); -unsigned long platform_get_stack(unsigned long mpidr); -uint64_t plat_get_syscnt_freq(void); + +/******************************************************************************* + * Mandatory interrupt management functions + ******************************************************************************/ uint32_t ic_get_pending_interrupt_id(void); uint32_t ic_get_pending_interrupt_type(void); uint32_t ic_acknowledge_interrupt(void); @@ -76,12 +68,19 @@ void ic_end_of_interrupt(uint32_t id); uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state); -int plat_get_max_afflvl(void); -unsigned int plat_get_aff_count(unsigned int, unsigned long); -unsigned int plat_get_aff_state(unsigned int, unsigned long); -int plat_get_image_source(const char *image_name, - uintptr_t *dev_handle, - uintptr_t *image_spec); +/******************************************************************************* + * Optional common functions (may be overridden) + ******************************************************************************/ +unsigned int platform_get_core_pos(unsigned long mpidr); +unsigned long platform_get_stack(unsigned long mpidr); +void plat_report_exception(unsigned long); + +/******************************************************************************* + * Mandatory BL1 functions + ******************************************************************************/ +void bl1_plat_arch_setup(void); +void bl1_platform_setup(void); +struct meminfo *bl1_plat_sec_mem_layout(void); /* * Before calling this function BL2 is loaded in memory and its entrypoint @@ -92,6 +91,40 @@ int plat_get_image_source(const char *image_name, void bl1_plat_set_bl2_ep_info(struct image_info *image, struct entry_point_info *ep); +/******************************************************************************* + * Optional BL1 functions (may be overridden) + ******************************************************************************/ +void init_bl2_mem_layout(struct meminfo *, + struct meminfo *, + unsigned int, + unsigned long); + +/******************************************************************************* + * Mandatory BL2 functions + ******************************************************************************/ +void bl2_plat_arch_setup(void); +void bl2_platform_setup(void); +struct meminfo *bl2_plat_sec_mem_layout(void); + +/* + * This function returns a pointer to the shared memory that the platform has + * kept aside to pass trusted firmware related information that BL3-1 + * could need + */ +struct bl31_params *bl2_plat_get_bl31_params(void); + +/* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + */ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void); + +/* + * This function flushes to main memory all the params that are + * passed to BL3-1 + */ +void bl2_plat_flush_bl31_params(void); + /* * Before calling this function BL31 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change @@ -125,5 +158,30 @@ void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); /* Gets the memory layout for BL33 */ void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); +/******************************************************************************* + * Optional BL2 functions (may be overridden) + ******************************************************************************/ + +/******************************************************************************* + * Mandatory BL3-1 functions + ******************************************************************************/ +void bl31_early_platform_setup(struct bl31_params *from_bl2, + void *plat_params_from_bl2); +void bl31_plat_arch_setup(void); +void bl31_platform_setup(void); +struct entry_point_info *bl31_get_next_image_info(uint32_t type); + +/******************************************************************************* + * Mandatory PSCI functions (BL3-1) + ******************************************************************************/ +int platform_setup_pm(const struct plat_pm_ops **); +int plat_get_max_afflvl(void); +unsigned int plat_get_aff_count(unsigned int, unsigned long); +unsigned int plat_get_aff_state(unsigned int, unsigned long); + +/******************************************************************************* + * Mandatory BL3-2 functions (only if platform contains a BL3-2) + ******************************************************************************/ +void bl32_platform_setup(void); #endif /* __PLATFORM_H__ */ diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_plat_setup.c index 5fbebc163c..34e74e259a 100644 --- a/plat/fvp/bl1_plat_setup.c +++ b/plat/fvp/bl1_plat_setup.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c index 87efe28f96..2cfb8bca9d 100644 --- a/plat/fvp/bl2_plat_setup.c +++ b/plat/fvp/bl2_plat_setup.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/plat/fvp/bl32_plat_setup.c b/plat/fvp/bl32_plat_setup.c index 7930314278..b583349fcc 100644 --- a/plat/fvp/bl32_plat_setup.c +++ b/plat/fvp/bl32_plat_setup.c @@ -28,9 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include #include -#include #include #include #include "fvp_def.h" diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h index cde1fd0abc..04e8b81825 100644 --- a/plat/fvp/fvp_private.h +++ b/plat/fvp/fvp_private.h @@ -55,9 +55,26 @@ typedef struct bl2_to_bl31_params_mem { entry_point_info_t bl31_ep_info; } bl2_to_bl31_params_mem_t; +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct meminfo; + /******************************************************************************* * Function and variable prototypes ******************************************************************************/ +void configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); +void configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); unsigned long platform_get_cfgvar(unsigned int); int platform_config_setup(void); From 17a387ad5af5beacd8406f3f35cbf697e4ac3698 Mon Sep 17 00:00:00 2001 From: Dan Handley Date: Thu, 15 May 2014 14:53:30 +0100 Subject: [PATCH 5/8] Rename FVP specific files and functions FVP specific files and functions containing the word "plat" have been renamed to use the word "fvp" to distinguish them from the common platform functionality and porting functions. Change-Id: I39f9673dab3ee9c74bd18b3e62b7c21027232f7d --- bl32/tsp/tsp-fvp.mk | 8 +-- .../aarch64/{plat_common.c => fvp_common.c} | 54 +++++++++---------- .../aarch64/{plat_helpers.S => fvp_helpers.S} | 4 +- .../fvp/{bl1_plat_setup.c => bl1_fvp_setup.c} | 16 +++--- .../fvp/{bl2_plat_setup.c => bl2_fvp_setup.c} | 18 +++---- .../{bl31_plat_setup.c => bl31_fvp_setup.c} | 26 ++++----- .../{bl32_plat_setup.c => bl32_fvp_setup.c} | 14 ++--- plat/fvp/{plat_gic.c => fvp_gic.c} | 16 +++--- .../{plat_io_storage.c => fvp_io_storage.c} | 2 +- plat/fvp/{plat_pm.c => fvp_pm.c} | 18 +++---- plat/fvp/fvp_private.h | 40 +++++++------- plat/fvp/{plat_security.c => fvp_security.c} | 4 +- plat/fvp/{plat_topology.c => fvp_topology.c} | 2 +- plat/fvp/include/plat_macros.S | 2 +- plat/fvp/platform.mk | 32 +++++------ 15 files changed, 128 insertions(+), 128 deletions(-) rename plat/fvp/aarch64/{plat_common.c => fvp_common.c} (89%) rename plat/fvp/aarch64/{plat_helpers.S => fvp_helpers.S} (98%) rename plat/fvp/{bl1_plat_setup.c => bl1_fvp_setup.c} (95%) rename plat/fvp/{bl2_plat_setup.c => bl2_fvp_setup.c} (97%) rename plat/fvp/{bl31_plat_setup.c => bl31_fvp_setup.c} (95%) rename plat/fvp/{bl32_plat_setup.c => bl32_fvp_setup.c} (94%) rename plat/fvp/{plat_gic.c => fvp_gic.c} (96%) rename plat/fvp/{plat_io_storage.c => fvp_io_storage.c} (99%) rename plat/fvp/{plat_pm.c => fvp_pm.c} (96%) rename plat/fvp/{plat_security.c => fvp_security.c} (98%) rename plat/fvp/{plat_topology.c => fvp_topology.c} (99%) diff --git a/bl32/tsp/tsp-fvp.mk b/bl32/tsp/tsp-fvp.mk index b1d0afef1b..21864d68da 100644 --- a/bl32/tsp/tsp-fvp.mk +++ b/bl32/tsp/tsp-fvp.mk @@ -31,7 +31,7 @@ # TSP source files specific to FVP platform BL32_SOURCES += drivers/arm/gic/gic_v2.c \ plat/common/aarch64/platform_mp_stack.S \ - plat/fvp/aarch64/plat_common.c \ - plat/fvp/aarch64/plat_helpers.S \ - plat/fvp/bl32_plat_setup.c \ - plat/fvp/plat_gic.c + plat/fvp/aarch64/fvp_common.c \ + plat/fvp/aarch64/fvp_helpers.S \ + plat/fvp/bl32_fvp_setup.c \ + plat/fvp/fvp_gic.c diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/fvp_common.c similarity index 89% rename from plat/fvp/aarch64/plat_common.c rename to plat/fvp/aarch64/fvp_common.c index f0a06d83e4..acfb75287e 100644 --- a/plat/fvp/aarch64/plat_common.c +++ b/plat/fvp/aarch64/fvp_common.c @@ -46,7 +46,7 @@ * configuration) & used thereafter. Each BL will have its own copy to allow * independent operation. ******************************************************************************/ -static unsigned long platform_config[CONFIG_LIMIT]; +static unsigned long fvp_config[CONFIG_LIMIT]; /******************************************************************************* * Macro generating the code for the function enabling the MMU in the given @@ -132,7 +132,7 @@ const mmap_region_t fvp_mmap[] = { * the platform memory map & initialize the mmu, for the given exception level ******************************************************************************/ #define DEFINE_CONFIGURE_MMU_EL(_el) \ - void configure_mmu_el##_el(unsigned long total_base, \ + void fvp_configure_mmu_el##_el(unsigned long total_base, \ unsigned long total_size, \ unsigned long ro_start, \ unsigned long ro_limit, \ @@ -157,10 +157,10 @@ DEFINE_CONFIGURE_MMU_EL(1) DEFINE_CONFIGURE_MMU_EL(3) /* Simple routine which returns a configuration variable value */ -unsigned long platform_get_cfgvar(unsigned int var_id) +unsigned long fvp_get_cfgvar(unsigned int var_id) { assert(var_id < CONFIG_LIMIT); - return platform_config[var_id]; + return fvp_config[var_id]; } /******************************************************************************* @@ -170,7 +170,7 @@ unsigned long platform_get_cfgvar(unsigned int var_id) * these platforms. This information is stored in a per-BL array to allow the * code to take the correct path.Per BL platform configuration. ******************************************************************************/ -int platform_config_setup(void) +int fvp_config_setup(void) { unsigned int rev, hbi, bld, arch, sys_id, midr_pn; @@ -189,16 +189,16 @@ int platform_config_setup(void) */ switch (bld) { case BLD_GIC_VE_MMAP: - platform_config[CONFIG_GICD_ADDR] = VE_GICD_BASE; - platform_config[CONFIG_GICC_ADDR] = VE_GICC_BASE; - platform_config[CONFIG_GICH_ADDR] = VE_GICH_BASE; - platform_config[CONFIG_GICV_ADDR] = VE_GICV_BASE; + fvp_config[CONFIG_GICD_ADDR] = VE_GICD_BASE; + fvp_config[CONFIG_GICC_ADDR] = VE_GICC_BASE; + fvp_config[CONFIG_GICH_ADDR] = VE_GICH_BASE; + fvp_config[CONFIG_GICV_ADDR] = VE_GICV_BASE; break; case BLD_GIC_A53A57_MMAP: - platform_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE; - platform_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE; - platform_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE; - platform_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE; + fvp_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE; + fvp_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE; + fvp_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE; + fvp_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE; break; default: assert(0); @@ -210,25 +210,25 @@ int platform_config_setup(void) */ switch (hbi) { case HBI_FOUNDATION: - platform_config[CONFIG_MAX_AFF0] = 4; - platform_config[CONFIG_MAX_AFF1] = 1; - platform_config[CONFIG_CPU_SETUP] = 0; - platform_config[CONFIG_BASE_MMAP] = 0; - platform_config[CONFIG_HAS_CCI] = 0; - platform_config[CONFIG_HAS_TZC] = 0; + fvp_config[CONFIG_MAX_AFF0] = 4; + fvp_config[CONFIG_MAX_AFF1] = 1; + fvp_config[CONFIG_CPU_SETUP] = 0; + fvp_config[CONFIG_BASE_MMAP] = 0; + fvp_config[CONFIG_HAS_CCI] = 0; + fvp_config[CONFIG_HAS_TZC] = 0; break; case HBI_FVP_BASE: midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK; if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53)) - platform_config[CONFIG_CPU_SETUP] = 1; + fvp_config[CONFIG_CPU_SETUP] = 1; else - platform_config[CONFIG_CPU_SETUP] = 0; + fvp_config[CONFIG_CPU_SETUP] = 0; - platform_config[CONFIG_MAX_AFF0] = 4; - platform_config[CONFIG_MAX_AFF1] = 2; - platform_config[CONFIG_BASE_MMAP] = 1; - platform_config[CONFIG_HAS_CCI] = 1; - platform_config[CONFIG_HAS_TZC] = 1; + fvp_config[CONFIG_MAX_AFF0] = 4; + fvp_config[CONFIG_MAX_AFF1] = 2; + fvp_config[CONFIG_BASE_MMAP] = 1; + fvp_config[CONFIG_HAS_CCI] = 1; + fvp_config[CONFIG_HAS_TZC] = 1; break; default: assert(0); @@ -264,7 +264,7 @@ void fvp_cci_setup(void) * for locks as no other cpu is active at the * moment */ - cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); + cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI); if (cci_setup) cci_enable_coherency(read_mpidr()); } diff --git a/plat/fvp/aarch64/plat_helpers.S b/plat/fvp/aarch64/fvp_helpers.S similarity index 98% rename from plat/fvp/aarch64/plat_helpers.S rename to plat/fvp/aarch64/fvp_helpers.S index fbb2fce36a..f856f46057 100644 --- a/plat/fvp/aarch64/plat_helpers.S +++ b/plat/fvp/aarch64/fvp_helpers.S @@ -40,7 +40,7 @@ .globl platform_mem_init .globl plat_report_exception - .macro platform_choose_gicmmap param1, param2, x_tmp, w_tmp, res + .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID ldr \w_tmp, [\x_tmp] ubfx \w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH @@ -78,7 +78,7 @@ func plat_secondary_cold_boot_setup */ ldr x0, =VE_GICC_BASE ldr x1, =BASE_GICC_BASE - platform_choose_gicmmap x0, x1, x2, w2, x1 + fvp_choose_gicmmap x0, x1, x2, w2, x1 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) str w0, [x1, #GICC_CTLR] diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_fvp_setup.c similarity index 95% rename from plat/fvp/bl1_plat_setup.c rename to plat/fvp/bl1_fvp_setup.c index 34e74e259a..f758082c59 100644 --- a/plat/fvp/bl1_plat_setup.c +++ b/plat/fvp/bl1_fvp_setup.c @@ -105,7 +105,7 @@ void bl1_early_platform_setup(void) } /* Initialize the platform config for future decision making */ - platform_config_setup(); + fvp_config_setup(); } /******************************************************************************* @@ -116,7 +116,7 @@ void bl1_early_platform_setup(void) void bl1_platform_setup(void) { /* Initialise the IO layer and register platform IO devices */ - io_setup(); + fvp_io_setup(); } @@ -129,12 +129,12 @@ void bl1_plat_arch_setup(void) { fvp_cci_setup(); - configure_mmu_el3(bl1_tzram_layout.total_base, - bl1_tzram_layout.total_size, - TZROM_BASE, - TZROM_BASE + TZROM_SIZE, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + fvp_configure_mmu_el3(bl1_tzram_layout.total_base, + bl1_tzram_layout.total_size, + TZROM_BASE, + TZROM_BASE + TZROM_SIZE, + BL1_COHERENT_RAM_BASE, + BL1_COHERENT_RAM_LIMIT); } diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_fvp_setup.c similarity index 97% rename from plat/fvp/bl2_plat_setup.c rename to plat/fvp/bl2_fvp_setup.c index 2cfb8bca9d..e18cf7ddb4 100644 --- a/plat/fvp/bl2_plat_setup.c +++ b/plat/fvp/bl2_fvp_setup.c @@ -179,7 +179,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) bl2_tzram_layout.next = 0; /* Initialize the platform config for future decision making */ - platform_config_setup(); + fvp_config_setup(); } /******************************************************************************* @@ -194,10 +194,10 @@ void bl2_platform_setup(void) * other platforms might have more programmable security devices * present. */ - plat_security_setup(); + fvp_security_setup(); /* Initialise the IO layer and register platform IO devices */ - io_setup(); + fvp_io_setup(); } /* Flush the TF params and the TF plat params */ @@ -214,12 +214,12 @@ void bl2_plat_flush_bl31_params(void) ******************************************************************************/ void bl2_plat_arch_setup() { - configure_mmu_el1(bl2_tzram_layout.total_base, - bl2_tzram_layout.total_size, - BL2_RO_BASE, - BL2_RO_LIMIT, - BL2_COHERENT_RAM_BASE, - BL2_COHERENT_RAM_LIMIT); + fvp_configure_mmu_el1(bl2_tzram_layout.total_base, + bl2_tzram_layout.total_size, + BL2_RO_BASE, + BL2_RO_LIMIT, + BL2_COHERENT_RAM_BASE, + BL2_COHERENT_RAM_LIMIT); } /******************************************************************************* diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_fvp_setup.c similarity index 95% rename from plat/fvp/bl31_plat_setup.c rename to plat/fvp/bl31_fvp_setup.c index d1e16bd522..d867fbac90 100644 --- a/plat/fvp/bl31_plat_setup.c +++ b/plat/fvp/bl31_fvp_setup.c @@ -95,9 +95,9 @@ entry_point_info_t *bl31_get_next_image_info(uint32_t type) #if RESET_TO_BL31 if (type == NON_SECURE) - plat_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info); + fvp_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info); else - plat_get_entry_point_info(SECURE, &bl32_entrypoint_info); + fvp_get_entry_point_info(SECURE, &bl32_entrypoint_info); next_image_info = (type == NON_SECURE) ? &bl33_entrypoint_info : @@ -134,7 +134,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, console_init(PL011_UART0_BASE); /* Initialize the platform config for future decision making */ - platform_config_setup(); + fvp_config_setup(); #if RESET_TO_BL31 /* There are no parameters from BL2 if BL31 is a reset vector */ @@ -148,7 +148,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, * other platforms might have more programmable security devices * present. */ - plat_security_setup(); + fvp_security_setup(); #else /* Check params passed from BL2 should not be NULL, * We are not checking plat_params_from_bl2 as NULL as we are not @@ -199,7 +199,7 @@ void bl31_platform_setup() fvp_pwrc_setup(); /* Topologies are best known to the platform. */ - plat_setup_topology(); + fvp_setup_topology(); } /******************************************************************************* @@ -210,14 +210,14 @@ void bl31_plat_arch_setup() { #if RESET_TO_BL31 fvp_cci_setup(); -#endif - configure_mmu_el3(BL31_RO_BASE, - (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), - BL31_RO_BASE, - BL31_RO_LIMIT, - BL31_COHERENT_RAM_BASE, - BL31_COHERENT_RAM_LIMIT); +#endif + fvp_configure_mmu_el3(BL31_RO_BASE, + (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), + BL31_RO_BASE, + BL31_RO_LIMIT, + BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT); } #if RESET_TO_BL31 @@ -225,7 +225,7 @@ void bl31_plat_arch_setup() * Generate the entry point info for Non Secure and Secure images * for transferring control from BL31 ******************************************************************************/ -void plat_get_entry_point_info(unsigned long target_security, +void fvp_get_entry_point_info(unsigned long target_security, entry_point_info_t *target_entry_info) { if (target_security == NON_SECURE) { diff --git a/plat/fvp/bl32_plat_setup.c b/plat/fvp/bl32_fvp_setup.c similarity index 94% rename from plat/fvp/bl32_plat_setup.c rename to plat/fvp/bl32_fvp_setup.c index b583349fcc..f8dc3c73db 100644 --- a/plat/fvp/bl32_plat_setup.c +++ b/plat/fvp/bl32_fvp_setup.c @@ -75,7 +75,7 @@ void bl32_early_platform_setup(void) console_init(PL011_UART1_BASE); /* Initialize the platform config for future decision making */ - platform_config_setup(); + fvp_config_setup(); } /******************************************************************************* @@ -92,10 +92,10 @@ void bl32_platform_setup() ******************************************************************************/ void bl32_plat_arch_setup() { - configure_mmu_el1(BL32_RO_BASE, - (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE), - BL32_RO_BASE, - BL32_RO_LIMIT, - BL32_COHERENT_RAM_BASE, - BL32_COHERENT_RAM_LIMIT); + fvp_configure_mmu_el1(BL32_RO_BASE, + (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE), + BL32_RO_BASE, + BL32_RO_LIMIT, + BL32_COHERENT_RAM_BASE, + BL32_COHERENT_RAM_LIMIT); } diff --git a/plat/fvp/plat_gic.c b/plat/fvp/fvp_gic.c similarity index 96% rename from plat/fvp/plat_gic.c rename to plat/fvp/fvp_gic.c index 6b29723bb0..fed2fca1f4 100644 --- a/plat/fvp/plat_gic.c +++ b/plat/fvp/fvp_gic.c @@ -277,8 +277,8 @@ void gic_setup(void) { unsigned int gicd_base, gicc_base; - gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR); - gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); + gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR); + gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR); gic_cpuif_setup(gicc_base); gic_distif_setup(gicd_base); @@ -298,7 +298,7 @@ void gic_setup(void) ******************************************************************************/ uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) { - uint32_t gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); + uint32_t gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR); assert(type == INTR_TYPE_S_EL1 || type == INTR_TYPE_EL3 || @@ -328,7 +328,7 @@ uint32_t ic_get_pending_interrupt_type() { uint32_t id, gicc_base; - gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); + gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR); id = gicc_read_hppir(gicc_base); /* Assume that all secure interrupts are S-EL1 interrupts */ @@ -350,7 +350,7 @@ uint32_t ic_get_pending_interrupt_id() { uint32_t id, gicc_base; - gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); + gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR); id = gicc_read_hppir(gicc_base); if (id < 1022) @@ -372,7 +372,7 @@ uint32_t ic_get_pending_interrupt_id() ******************************************************************************/ uint32_t ic_acknowledge_interrupt() { - return gicc_read_IAR(platform_get_cfgvar(CONFIG_GICC_ADDR)); + return gicc_read_IAR(fvp_get_cfgvar(CONFIG_GICC_ADDR)); } /******************************************************************************* @@ -381,7 +381,7 @@ uint32_t ic_acknowledge_interrupt() ******************************************************************************/ void ic_end_of_interrupt(uint32_t id) { - gicc_write_EOIR(platform_get_cfgvar(CONFIG_GICC_ADDR), id); + gicc_write_EOIR(fvp_get_cfgvar(CONFIG_GICC_ADDR), id); return; } @@ -394,7 +394,7 @@ uint32_t ic_get_interrupt_type(uint32_t id) { uint32_t group; - group = gicd_get_igroupr(platform_get_cfgvar(CONFIG_GICD_ADDR), id); + group = gicd_get_igroupr(fvp_get_cfgvar(CONFIG_GICD_ADDR), id); /* Assume that all secure interrupts are S-EL1 interrupts */ if (group == GRP0) diff --git a/plat/fvp/plat_io_storage.c b/plat/fvp/fvp_io_storage.c similarity index 99% rename from plat/fvp/plat_io_storage.c rename to plat/fvp/fvp_io_storage.c index baa98ffe9e..c32cca9289 100644 --- a/plat/fvp/plat_io_storage.c +++ b/plat/fvp/fvp_io_storage.c @@ -168,7 +168,7 @@ static int open_semihosting(const uintptr_t spec) return result; } -void io_setup (void) +void fvp_io_setup (void) { int io_result = IO_FAIL; diff --git a/plat/fvp/plat_pm.c b/plat/fvp/fvp_pm.c similarity index 96% rename from plat/fvp/plat_pm.c rename to plat/fvp/fvp_pm.c index ad4ce7939e..d70264304a 100644 --- a/plat/fvp/plat_pm.c +++ b/plat/fvp/fvp_pm.c @@ -139,7 +139,7 @@ int fvp_affinst_off(unsigned long mpidr, * Disable coherency if this cluster is to be * turned off */ - cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); + cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI); if (cci_setup) { cci_disable_coherency(mpidr); } @@ -160,7 +160,7 @@ int fvp_affinst_off(unsigned long mpidr, * Take this cpu out of intra-cluster coherency if * the FVP flavour supports the SMP bit. */ - cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP); + cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP); if (cpu_setup) { ectlr = read_cpuectlr(); ectlr &= ~CPUECTLR_SMP_BIT; @@ -171,7 +171,7 @@ int fvp_affinst_off(unsigned long mpidr, * Prevent interrupts from spuriously waking up * this cpu */ - gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); + gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR); gic_cpuif_deactivate(gicc_base); /* @@ -219,7 +219,7 @@ int fvp_affinst_suspend(unsigned long mpidr, * Disable coherency if this cluster is to be * turned off */ - cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); + cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI); if (cci_setup) { cci_disable_coherency(mpidr); } @@ -239,7 +239,7 @@ int fvp_affinst_suspend(unsigned long mpidr, * Take this cpu out of intra-cluster coherency if * the FVP flavour supports the SMP bit. */ - cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP); + cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP); if (cpu_setup) { ectlr = read_cpuectlr(); ectlr &= ~CPUECTLR_SMP_BIT; @@ -257,7 +257,7 @@ int fvp_affinst_suspend(unsigned long mpidr, * Prevent interrupts from spuriously waking up * this cpu */ - gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); + gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR); gic_cpuif_deactivate(gicc_base); /* @@ -325,7 +325,7 @@ int fvp_affinst_on_finish(unsigned long mpidr, * Turn on intra-cluster coherency if the FVP flavour supports * it. */ - cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP); + cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP); if (cpu_setup) { ectlr = read_cpuectlr(); ectlr |= CPUECTLR_SMP_BIT; @@ -345,8 +345,8 @@ int fvp_affinst_on_finish(unsigned long mpidr, flush_dcache_range((unsigned long) &fvp_mboxes[linear_id], sizeof(unsigned long)); - gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR); - gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); + gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR); + gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR); /* Enable the gic cpu interface */ gic_cpuif_setup(gicc_base); diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h index 04e8b81825..2331bb7eb6 100644 --- a/plat/fvp/fvp_private.h +++ b/plat/fvp/fvp_private.h @@ -63,23 +63,23 @@ struct meminfo; /******************************************************************************* * Function and variable prototypes ******************************************************************************/ -void configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long, - unsigned long, - unsigned long, - unsigned long); -void configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long, - unsigned long, - unsigned long, - unsigned long); -unsigned long platform_get_cfgvar(unsigned int); -int platform_config_setup(void); +void fvp_configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); +void fvp_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); +unsigned long fvp_get_cfgvar(unsigned int); +int fvp_config_setup(void); #if RESET_TO_BL31 -void plat_get_entry_point_info(unsigned long target_security, +void fvp_get_entry_point_info(unsigned long target_security, struct entry_point_info *target_entry_info); #endif void fvp_cci_setup(void); @@ -91,13 +91,13 @@ void gic_pcpu_distif_setup(unsigned int); void gic_setup(void); /* Declarations for fvp_topology.c */ -int plat_setup_topology(void); +int fvp_setup_topology(void); -/* Declarations for plat_io_storage.c */ -void io_setup(void); +/* Declarations for fvp_io_storage.c */ +void fvp_io_setup(void); -/* Declarations for plat_security.c */ -void plat_security_setup(void); +/* Declarations for fvp_security.c */ +void fvp_security_setup(void); /* Sets the entrypoint for BL32 */ void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep); diff --git a/plat/fvp/plat_security.c b/plat/fvp/fvp_security.c similarity index 98% rename from plat/fvp/plat_security.c rename to plat/fvp/fvp_security.c index 976f75e98e..76c45413fb 100644 --- a/plat/fvp/plat_security.c +++ b/plat/fvp/fvp_security.c @@ -43,7 +43,7 @@ * TODO: * Might want to enable interrupt on violations when supported? */ -void plat_security_setup(void) +void fvp_security_setup(void) { tzc_instance_t controller; @@ -56,7 +56,7 @@ void plat_security_setup(void) * configurations, those would be configured here. */ - if (!platform_get_cfgvar(CONFIG_HAS_TZC)) + if (!fvp_get_cfgvar(CONFIG_HAS_TZC)) return; /* diff --git a/plat/fvp/plat_topology.c b/plat/fvp/fvp_topology.c similarity index 99% rename from plat/fvp/plat_topology.c rename to plat/fvp/fvp_topology.c index f06b4f7470..cf21503773 100644 --- a/plat/fvp/plat_topology.c +++ b/plat/fvp/fvp_topology.c @@ -190,7 +190,7 @@ int plat_get_max_afflvl() * the FVP flavour its running on. We construct all the mpidrs we can handle * and rely on the PWRC.PSYSR to flag absent cpus when their status is queried. ******************************************************************************/ -int plat_setup_topology() +int fvp_setup_topology() { unsigned char aff0, aff1, aff_state, aff0_offset = 0; unsigned long mpidr; diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S index 1fa50fd14f..bdd402dc07 100644 --- a/plat/fvp/include/plat_macros.S +++ b/plat/fvp/include/plat_macros.S @@ -44,7 +44,7 @@ gic_regs: .asciz "gic_iar", "gic_ctlr", "" */ .macro plat_print_gic_regs mov x0, #CONFIG_GICC_ADDR - bl platform_get_cfgvar + bl fvp_get_cfgvar /* gic base address is now in x0 */ ldr w1, [x0, #GICC_IAR] ldr w2, [x0, #GICD_CTLR] diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk index f1d6f878d6..105cdfa4a8 100644 --- a/plat/fvp/platform.mk +++ b/plat/fvp/platform.mk @@ -51,40 +51,40 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \ drivers/io/io_memmap.c \ drivers/io/io_semihosting.c \ lib/mmio.c \ - lib/aarch64/sysreg_helpers.S \ + lib/aarch64/sysreg_helpers.S \ lib/aarch64/xlat_tables.c \ lib/semihosting/semihosting.c \ lib/semihosting/aarch64/semihosting_call.S \ - plat/fvp/plat_io_storage.c + plat/fvp/fvp_io_storage.c BL1_SOURCES += drivers/arm/cci400/cci400.c \ plat/common/aarch64/platform_up_stack.S \ - plat/fvp/bl1_plat_setup.c \ - plat/fvp/aarch64/plat_common.c \ - plat/fvp/aarch64/plat_helpers.S + plat/fvp/bl1_fvp_setup.c \ + plat/fvp/aarch64/fvp_common.c \ + plat/fvp/aarch64/fvp_helpers.S BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ plat/common/aarch64/platform_up_stack.S \ - plat/fvp/bl2_plat_setup.c \ - plat/fvp/plat_security.c \ - plat/fvp/aarch64/plat_common.c + plat/fvp/bl2_fvp_setup.c \ + plat/fvp/fvp_security.c \ + plat/fvp/aarch64/fvp_common.c BL31_SOURCES += drivers/arm/gic/gic_v2.c \ drivers/arm/gic/gic_v3.c \ drivers/arm/gic/aarch64/gic_v3_sysregs.S \ drivers/arm/cci400/cci400.c \ plat/common/aarch64/platform_mp_stack.S \ - plat/fvp/bl31_plat_setup.c \ - plat/fvp/plat_gic.c \ - plat/fvp/plat_pm.c \ - plat/fvp/plat_topology.c \ - plat/fvp/aarch64/plat_helpers.S \ - plat/fvp/aarch64/plat_common.c \ + plat/fvp/bl31_fvp_setup.c \ + plat/fvp/fvp_gic.c \ + plat/fvp/fvp_pm.c \ + plat/fvp/fvp_topology.c \ + plat/fvp/aarch64/fvp_helpers.S \ + plat/fvp/aarch64/fvp_common.c \ plat/fvp/drivers/pwrc/fvp_pwrc.c ifeq (${RESET_TO_BL31}, 1) - BL31_SOURCES += drivers/arm/tzc400/tzc400.c \ - plat/fvp/plat_security.c +BL31_SOURCES += drivers/arm/tzc400/tzc400.c \ + plat/fvp/fvp_security.c endif # Flag used by the FVP port to determine the version of ARM GIC architecture From dff8e47a4b6797e862a20559d34a9e2a056ab6e1 Mon Sep 17 00:00:00 2001 From: Dan Handley Date: Fri, 16 May 2014 14:08:45 +0100 Subject: [PATCH 6/8] Add enable mmu platform porting interfaces Previously, the enable_mmu_elX() functions were implicitly part of the platform porting layer since they were included by generic code. These functions have been placed behind 2 new platform functions, bl31_plat_enable_mmu() and bl32_plat_enable_mmu(). These are weakly defined so that they can be optionally overridden by platform ports. Also, the enable_mmu_elX() functions have been moved to lib/aarch64/xlat_tables.c for optional re-use by platform ports. These functions are tightly coupled with the translation table initialization code. Fixes ARM-software/tf-issues#152 Change-Id: I0a2251ce76acfa3c27541f832a9efaa49135cc1c --- bl32/tsp/aarch64/tsp_entrypoint.S | 2 +- include/lib/aarch64/xlat_tables.h | 3 +- include/plat/common/platform.h | 12 ++++- lib/aarch64/xlat_tables.c | 63 +++++++++++++++++++++++++- plat/common/aarch64/plat_common.c | 49 ++++++++++++++++++++ plat/fvp/aarch64/fvp_common.c | 59 ------------------------ plat/fvp/platform.mk | 1 + services/std_svc/psci/psci_afflvl_on.c | 2 +- 8 files changed, 126 insertions(+), 65 deletions(-) create mode 100644 plat/common/aarch64/plat_common.c diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 8fdfbc396d..479ca59b39 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -220,7 +220,7 @@ func tsp_cpu_on_entry * Initialise the MMU * --------------------------------------------- */ - bl enable_mmu_el1 + bl bl32_plat_enable_mmu /* --------------------------------------------- * Give ourselves a stack allocated in Normal diff --git a/include/lib/aarch64/xlat_tables.h b/include/lib/aarch64/xlat_tables.h index a500f03355..5df655bd50 100644 --- a/include/lib/aarch64/xlat_tables.h +++ b/include/lib/aarch64/xlat_tables.h @@ -66,6 +66,7 @@ void mmap_add(const mmap_region_t *mm); void init_xlat_tables(void); -extern uint64_t l1_xlation_table[]; +void enable_mmu_el1(void); +void enable_mmu_el3(void); #endif /* __XLAT_TABLES_H__ */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index 7e2e91201f..e2ba11d3ec 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -50,8 +50,6 @@ struct bl31_params; * Mandatory common functions ******************************************************************************/ uint64_t plat_get_syscnt_freq(void); -void enable_mmu_el1(void); -void enable_mmu_el3(void); int plat_get_image_source(const char *image_name, uintptr_t *dev_handle, uintptr_t *image_spec); @@ -179,9 +177,19 @@ int plat_get_max_afflvl(void); unsigned int plat_get_aff_count(unsigned int, unsigned long); unsigned int plat_get_aff_state(unsigned int, unsigned long); +/******************************************************************************* + * Optional BL3-1 functions (may be overridden) + ******************************************************************************/ +void bl31_plat_enable_mmu(); + /******************************************************************************* * Mandatory BL3-2 functions (only if platform contains a BL3-2) ******************************************************************************/ void bl32_platform_setup(void); +/******************************************************************************* + * Optional BL3-2 functions (may be overridden) + ******************************************************************************/ +void bl32_plat_enable_mmu(); + #endif /* __PLATFORM_H__ */ diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c index 4e935a50e3..29b81dbd3c 100644 --- a/lib/aarch64/xlat_tables.c +++ b/lib/aarch64/xlat_tables.c @@ -28,6 +28,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include +#include #include #include #include @@ -49,7 +51,7 @@ #define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) -uint64_t l1_xlation_table[NUM_L1_ENTRIES] +static uint64_t l1_xlation_table[NUM_L1_ENTRIES] __aligned(NUM_L1_ENTRIES * sizeof(uint64_t)); static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] @@ -226,3 +228,62 @@ void init_xlat_tables(void) print_mmap(); init_xlation_table(mmap, 0, l1_xlation_table, 1); } + +/******************************************************************************* + * Macro generating the code for the function enabling the MMU in the given + * exception level, assuming that the pagetables have already been created. + * + * _el: Exception level at which the function will run + * _tcr_extra: Extra bits to set in the TCR register. This mask will + * be OR'ed with the default TCR value. + * _tlbi_fct: Function to invalidate the TLBs at the current + * exception level + ******************************************************************************/ +#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \ + void enable_mmu_el##_el(void) \ + { \ + uint64_t mair, tcr, ttbr; \ + uint32_t sctlr; \ + \ + assert(IS_IN_EL(_el)); \ + assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \ + \ + /* Set attributes in the right indices of the MAIR */ \ + mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \ + mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \ + ATTR_IWBWA_OWBWA_NTR_INDEX); \ + write_mair_el##_el(mair); \ + \ + /* Invalidate TLBs at the current exception level */ \ + _tlbi_fct(); \ + \ + /* Set TCR bits as well. */ \ + /* Inner & outer WBWA & shareable + T0SZ = 32 */ \ + tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \ + TCR_RGN_INNER_WBA | TCR_T0SZ_4GB; \ + tcr |= _tcr_extra; \ + write_tcr_el##_el(tcr); \ + \ + /* Set TTBR bits as well */ \ + ttbr = (uint64_t) l1_xlation_table; \ + write_ttbr0_el##_el(ttbr); \ + \ + /* Ensure all translation table writes have drained */ \ + /* into memory, the TLB invalidation is complete, */ \ + /* and translation register writes are committed */ \ + /* before enabling the MMU */ \ + dsb(); \ + isb(); \ + \ + sctlr = read_sctlr_el##_el(); \ + sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT; \ + sctlr |= SCTLR_A_BIT | SCTLR_C_BIT; \ + write_sctlr_el##_el(sctlr); \ + \ + /* Ensure the MMU enable takes effect immediately */ \ + isb(); \ + } + +/* Define EL1 and EL3 variants of the function enabling the MMU */ +DEFINE_ENABLE_MMU_EL(1, 0, tlbivmalle1) +DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1, tlbialle3) diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c new file mode 100644 index 0000000000..2abf29d977 --- /dev/null +++ b/plat/common/aarch64/plat_common.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* + * The following 2 platform setup functions are weakly defined. They + * provide typical implementations that may be re-used by multiple + * platforms but may also be overridden by a platform if required. + */ +#pragma weak bl31_plat_enable_mmu +#pragma weak bl32_plat_enable_mmu + +void bl31_plat_enable_mmu() +{ + enable_mmu_el3(); +} + +void bl32_plat_enable_mmu() +{ + enable_mmu_el1(); +} diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c index acfb75287e..3a078448c6 100644 --- a/plat/fvp/aarch64/fvp_common.c +++ b/plat/fvp/aarch64/fvp_common.c @@ -48,65 +48,6 @@ ******************************************************************************/ static unsigned long fvp_config[CONFIG_LIMIT]; -/******************************************************************************* - * Macro generating the code for the function enabling the MMU in the given - * exception level, assuming that the pagetables have already been created. - * - * _el: Exception level at which the function will run - * _tcr_extra: Extra bits to set in the TCR register. This mask will - * be OR'ed with the default TCR value. - * _tlbi_fct: Function to invalidate the TLBs at the current - * exception level - ******************************************************************************/ -#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \ - void enable_mmu_el##_el(void) \ - { \ - uint64_t mair, tcr, ttbr; \ - uint32_t sctlr; \ - \ - assert(IS_IN_EL(_el)); \ - assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \ - \ - /* Set attributes in the right indices of the MAIR */ \ - mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \ - mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \ - ATTR_IWBWA_OWBWA_NTR_INDEX); \ - write_mair_el##_el(mair); \ - \ - /* Invalidate TLBs at the current exception level */ \ - _tlbi_fct(); \ - \ - /* Set TCR bits as well. */ \ - /* Inner & outer WBWA & shareable + T0SZ = 32 */ \ - tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \ - TCR_RGN_INNER_WBA | TCR_T0SZ_4GB; \ - tcr |= _tcr_extra; \ - write_tcr_el##_el(tcr); \ - \ - /* Set TTBR bits as well */ \ - ttbr = (uint64_t) l1_xlation_table; \ - write_ttbr0_el##_el(ttbr); \ - \ - /* Ensure all translation table writes have drained */ \ - /* into memory, the TLB invalidation is complete, */ \ - /* and translation register writes are committed */ \ - /* before enabling the MMU */ \ - dsb(); \ - isb(); \ - \ - sctlr = read_sctlr_el##_el(); \ - sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT; \ - sctlr |= SCTLR_A_BIT | SCTLR_C_BIT; \ - write_sctlr_el##_el(sctlr); \ - \ - /* Ensure the MMU enable takes effect immediately */ \ - isb(); \ - } - -/* Define EL1 and EL3 variants of the function enabling the MMU */ -DEFINE_ENABLE_MMU_EL(1, 0, tlbivmalle1) -DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1, tlbialle3) - /* * Table of regions to map using the MMU. * This doesn't include TZRAM as the 'mem_layout' argument passed to diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk index 105cdfa4a8..4cc4d1eb4c 100644 --- a/plat/fvp/platform.mk +++ b/plat/fvp/platform.mk @@ -55,6 +55,7 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \ lib/aarch64/xlat_tables.c \ lib/semihosting/semihosting.c \ lib/semihosting/aarch64/semihosting_call.S \ + plat/common/aarch64/plat_common.c \ plat/fvp/fvp_io_storage.c BL1_SOURCES += drivers/arm/cci400/cci400.c \ diff --git a/services/std_svc/psci/psci_afflvl_on.c b/services/std_svc/psci/psci_afflvl_on.c index 1e5828caca..e3a1831c29 100644 --- a/services/std_svc/psci/psci_afflvl_on.c +++ b/services/std_svc/psci/psci_afflvl_on.c @@ -363,7 +363,7 @@ static unsigned int psci_afflvl0_on_finish(unsigned long mpidr, /* * Arch. management: Turn on mmu & restore architectural state */ - enable_mmu_el3(); + bl31_plat_enable_mmu(); /* * All the platform specific actions for turning this cpu From 0ad469110437196cfbb781b30233d62e2320f694 Mon Sep 17 00:00:00 2001 From: Dan Handley Date: Tue, 27 May 2014 15:39:41 +0100 Subject: [PATCH 7/8] Remove FVP specific comments in platform.h Remove the FVP specific comments in platform.h since this file is re-usable across all platforms. Change-Id: Ifd4a4f72562adb3ecf8b9078b0150f170ef22dba --- include/plat/common/platform.h | 25 +++++-------------------- 1 file changed, 5 insertions(+), 20 deletions(-) diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index e2ba11d3ec..ad0818028a 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -81,10 +81,8 @@ void bl1_platform_setup(void); struct meminfo *bl1_plat_sec_mem_layout(void); /* - * Before calling this function BL2 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL2 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint + * This function allows the platform to change the entrypoint information for + * BL2, after BL1 has loaded BL2 into memory but before BL2 is executed. */ void bl1_plat_set_bl2_ep_info(struct image_info *image, struct entry_point_info *ep); @@ -124,29 +122,16 @@ struct entry_point_info *bl2_plat_get_bl31_ep_info(void); void bl2_plat_flush_bl31_params(void); /* - * Before calling this function BL31 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL31 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint + * The next 3 functions allow the platform to change the entrypoint + * information for the 3rd level BL images, after BL2 has loaded the 3rd + * level BL images into memory but before BL3-1 is executed. */ void bl2_plat_set_bl31_ep_info(struct image_info *image, struct entry_point_info *ep); -/* - * Before calling this function BL32 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL32 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ void bl2_plat_set_bl32_ep_info(struct image_info *image, struct entry_point_info *ep); -/* - * Before calling this function BL33 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL33 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ void bl2_plat_set_bl33_ep_info(struct image_info *image, struct entry_point_info *ep); From 9865ac15765f260069047c0e7c56623eb1a70b9a Mon Sep 17 00:00:00 2001 From: Dan Handley Date: Tue, 27 May 2014 16:17:21 +0100 Subject: [PATCH 8/8] Further renames of platform porting functions Rename the ic_* platform porting functions to plat_ic_* to be consistent with the other functions in platform.h. Also rename bl31_get_next_image_info() to bl31_plat_get_next_image_ep_info() and remove the duplicate declaration in bl31.h. Change-Id: I4851842069d3cff14c0a468daacc0a891a7ede84 --- bl31/aarch64/runtime_exceptions.S | 4 ++-- bl31/bl31_main.c | 2 +- bl32/tsp/tsp_interrupt.c | 6 +++--- include/bl31/bl31.h | 6 ------ include/plat/common/platform.h | 12 ++++++------ plat/fvp/bl31_fvp_setup.c | 2 +- plat/fvp/fvp_gic.c | 10 +++++----- services/spd/tspd/tspd_main.c | 2 +- 8 files changed, 19 insertions(+), 25 deletions(-) diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 7e119c58cb..e3673f0d99 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -84,7 +84,7 @@ * interrupt controller reports a spurious interrupt then * return to where we came from. */ - bl ic_get_pending_interrupt_type + bl plat_ic_get_pending_interrupt_type cmp x0, #INTR_TYPE_INVAL b.eq interrupt_exit_\label @@ -105,7 +105,7 @@ * Read the id of the highest priority pending interrupt. If * no interrupt is asserted then return to where we came from. */ - bl ic_get_pending_interrupt_id + bl plat_ic_get_pending_interrupt_id cmp x0, #INTR_ID_UNAVAILABLE b.eq interrupt_exit_\label #endif diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index 71c64643ef..5117793406 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c @@ -165,7 +165,7 @@ void bl31_prepare_next_image_entry() bl31_next_el_arch_setup(image_type); /* Program EL3 registers to enable entry into the next EL */ - next_image_info = bl31_get_next_image_info(image_type); + next_image_info = bl31_plat_get_next_image_ep_info(image_type); assert(next_image_info); scr = read_scr(); diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c index ac45d7afa6..4a4b877e29 100644 --- a/bl32/tsp/tsp_interrupt.c +++ b/bl32/tsp/tsp_interrupt.c @@ -82,7 +82,7 @@ int32_t tsp_fiq_handler() * secure physical generic timer interrupt in which case, handle it. * Otherwise throw this interrupt at the EL3 firmware. */ - id = ic_get_pending_interrupt_id(); + id = plat_ic_get_pending_interrupt_id(); /* TSP can only handle the secure physical timer interrupt */ if (id != IRQ_SEC_PHY_TIMER) @@ -92,10 +92,10 @@ int32_t tsp_fiq_handler() * Handle the interrupt. Also sanity check if it has been preempted by * another secure interrupt through an assertion. */ - id = ic_acknowledge_interrupt(); + id = plat_ic_acknowledge_interrupt(); assert(id == IRQ_SEC_PHY_TIMER); tsp_generic_timer_handler(); - ic_end_of_interrupt(id); + plat_ic_end_of_interrupt(id); /* Update the statistics and print some messages */ tsp_stats[linear_id].fiq_count++; diff --git a/include/bl31/bl31.h b/include/bl31/bl31.h index 8d22dc98bb..33e4ecee06 100644 --- a/include/bl31/bl31.h +++ b/include/bl31/bl31.h @@ -33,11 +33,6 @@ #include -/****************************************** - * Forward declarations - *****************************************/ -struct entry_point_info; - /******************************************************************************* * Function prototypes ******************************************************************************/ @@ -46,7 +41,6 @@ void bl31_next_el_arch_setup(uint32_t security_state); void bl31_set_next_image_type(uint32_t type); uint32_t bl31_get_next_image_type(void); void bl31_prepare_next_image_entry(); -struct entry_point_info *bl31_get_next_image_info(uint32_t type); void bl31_register_bl32_init(int32_t (*)(void)); #endif /* __BL31_H__ */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index ad0818028a..714f6e0772 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -58,11 +58,11 @@ unsigned long plat_get_ns_image_entrypoint(void); /******************************************************************************* * Mandatory interrupt management functions ******************************************************************************/ -uint32_t ic_get_pending_interrupt_id(void); -uint32_t ic_get_pending_interrupt_type(void); -uint32_t ic_acknowledge_interrupt(void); -uint32_t ic_get_interrupt_type(uint32_t id); -void ic_end_of_interrupt(uint32_t id); +uint32_t plat_ic_get_pending_interrupt_id(void); +uint32_t plat_ic_get_pending_interrupt_type(void); +uint32_t plat_ic_acknowledge_interrupt(void); +uint32_t plat_ic_get_interrupt_type(uint32_t id); +void plat_ic_end_of_interrupt(uint32_t id); uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state); @@ -152,7 +152,7 @@ void bl31_early_platform_setup(struct bl31_params *from_bl2, void *plat_params_from_bl2); void bl31_plat_arch_setup(void); void bl31_platform_setup(void); -struct entry_point_info *bl31_get_next_image_info(uint32_t type); +struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type); /******************************************************************************* * Mandatory PSCI functions (BL3-1) diff --git a/plat/fvp/bl31_fvp_setup.c b/plat/fvp/bl31_fvp_setup.c index d867fbac90..5169bd76bd 100644 --- a/plat/fvp/bl31_fvp_setup.c +++ b/plat/fvp/bl31_fvp_setup.c @@ -88,7 +88,7 @@ static bl31_params_t *bl2_to_bl31_params; * while BL32 corresponds to the secure image type. A NULL pointer is returned * if the image does not exist. ******************************************************************************/ -entry_point_info_t *bl31_get_next_image_info(uint32_t type) +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) { entry_point_info_t *next_image_info; diff --git a/plat/fvp/fvp_gic.c b/plat/fvp/fvp_gic.c index fed2fca1f4..3156da9092 100644 --- a/plat/fvp/fvp_gic.c +++ b/plat/fvp/fvp_gic.c @@ -324,7 +324,7 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no * interrupt pending. ******************************************************************************/ -uint32_t ic_get_pending_interrupt_type() +uint32_t plat_ic_get_pending_interrupt_type() { uint32_t id, gicc_base; @@ -346,7 +346,7 @@ uint32_t ic_get_pending_interrupt_type() * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no * interrupt pending. ******************************************************************************/ -uint32_t ic_get_pending_interrupt_id() +uint32_t plat_ic_get_pending_interrupt_id() { uint32_t id, gicc_base; @@ -370,7 +370,7 @@ uint32_t ic_get_pending_interrupt_id() * This functions reads the GIC cpu interface Interrupt Acknowledge register * to start handling the pending interrupt. It returns the contents of the IAR. ******************************************************************************/ -uint32_t ic_acknowledge_interrupt() +uint32_t plat_ic_acknowledge_interrupt() { return gicc_read_IAR(fvp_get_cfgvar(CONFIG_GICC_ADDR)); } @@ -379,7 +379,7 @@ uint32_t ic_acknowledge_interrupt() * This functions writes the GIC cpu interface End Of Interrupt register with * the passed value to finish handling the active interrupt ******************************************************************************/ -void ic_end_of_interrupt(uint32_t id) +void plat_ic_end_of_interrupt(uint32_t id) { gicc_write_EOIR(fvp_get_cfgvar(CONFIG_GICC_ADDR), id); return; @@ -390,7 +390,7 @@ void ic_end_of_interrupt(uint32_t id) * this interrupt has been configured under by the interrupt controller i.e. * group0 or group1. ******************************************************************************/ -uint32_t ic_get_interrupt_type(uint32_t id) +uint32_t plat_ic_get_interrupt_type(uint32_t id) { uint32_t group; diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c index 1dbe6ba08f..da40ea3623 100644 --- a/services/spd/tspd/tspd_main.c +++ b/services/spd/tspd/tspd_main.c @@ -160,7 +160,7 @@ int32_t tspd_setup(void) * absence is a critical failure. TODO: Add support to * conditionally include the SPD service */ - image_info = bl31_get_next_image_info(SECURE); + image_info = bl31_plat_get_next_image_ep_info(SECURE); assert(image_info); /*