From 9784dbda1147458598f1d586d8242332ada19b44 Mon Sep 17 00:00:00 2001 From: Juan Castillo Date: Wed, 12 Aug 2015 12:53:02 +0100 Subject: [PATCH 1/3] Add basic NOR flash driver for ARM platforms FVP and Juno platforms include a NOR flash memory to store and load the FIP, the kernel or a ramdisk. This NOR flash is arranged as 2 x 16 bit flash devices and can be programmed using CFI standard commands. This patch provides a basic API to write single 32 bit words of data into the NOR flash. Functions to lock/unlock blocks against erase or write operations are also provided. Change-Id: I1da7ad3105b1ea409c976adc863954787cbd90d2 --- .../plat/arm/board/common/drivers/norflash.h | 68 ++++++++++ .../board/common/drivers/norflash/norflash.c | 124 ++++++++++++++++++ 2 files changed, 192 insertions(+) create mode 100644 include/plat/arm/board/common/drivers/norflash.h create mode 100644 plat/arm/board/common/drivers/norflash/norflash.c diff --git a/include/plat/arm/board/common/drivers/norflash.h b/include/plat/arm/board/common/drivers/norflash.h new file mode 100644 index 0000000000..0bf35a5063 --- /dev/null +++ b/include/plat/arm/board/common/drivers/norflash.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NORFLASH_H_ +#define __NORFLASH_H_ + +#include + +/* First bus cycle */ +#define NOR_CMD_READ_ARRAY 0xFF +#define NOR_CMD_READ_ID_CODE 0x90 +#define NOR_CMD_READ_QUERY 0x98 +#define NOR_CMD_READ_STATUS_REG 0x70 +#define NOR_CMD_CLEAR_STATUS_REG 0x50 +#define NOR_CMD_WRITE_TO_BUFFER 0xE8 +#define NOR_CMD_WORD_PROGRAM 0x40 +#define NOR_CMD_BLOCK_ERASE 0x20 +#define NOR_CMD_LOCK_UNLOCK 0x60 + +/* Second bus cycle */ +#define NOR_LOCK_BLOCK 0x01 +#define NOR_UNLOCK_BLOCK 0xD0 + +/* Status register bits */ +#define NOR_DWS (1 << 7) +#define NOR_ESS (1 << 6) +#define NOR_ES (1 << 5) +#define NOR_PS (1 << 4) +#define NOR_VPPS (1 << 3) +#define NOR_PSS (1 << 2) +#define NOR_BLS (1 << 1) +#define NOR_BWS (1 << 0) + +/* Public API */ +void nor_send_cmd(uintptr_t base_addr, unsigned long cmd); +int nor_word_program(uintptr_t base_addr, unsigned long data); +void nor_lock(uintptr_t base_addr); +void nor_unlock(uintptr_t base_addr); + +#endif /* __NORFLASH_H_ */ + diff --git a/plat/arm/board/common/drivers/norflash/norflash.c b/plat/arm/board/common/drivers/norflash/norflash.c new file mode 100644 index 0000000000..8895461404 --- /dev/null +++ b/plat/arm/board/common/drivers/norflash/norflash.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* Helper macros to access two flash banks in parallel */ +#define NOR_2X16(d) ((d << 16) | (d & 0xffff)) + +/* + * DWS ready poll retries. The number of retries in this driver have been + * obtained empirically from Juno. FVP implements a zero wait state NOR flash + * model + */ +#define DWS_WORD_PROGRAM_RETRIES 1000 + +/* + * Poll Write State Machine. Return values: + * 0 = WSM ready + * -EBUSY = WSM busy after the number of retries + */ +static int nor_poll_dws(uintptr_t base_addr, unsigned int retries) +{ + uint32_t status; + int ret; + + for (;;) { + nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG); + status = mmio_read_32(base_addr); + if ((status & NOR_DWS) && + (status & (NOR_DWS << 16))) { + ret = 0; + break; + } + if (retries-- == 0) { + ret = -EBUSY; + break; + } + } + + return ret; +} + +void nor_send_cmd(uintptr_t base_addr, unsigned long cmd) +{ + mmio_write_32(base_addr, NOR_2X16(cmd)); +} + +/* + * Return values: + * 0 = success + * -EBUSY = WSM not ready + * -EPERM = Device protected or Block locked + */ +int nor_word_program(uintptr_t base_addr, unsigned long data) +{ + uint32_t status; + int ret; + + /* Set the device in write word mode */ + nor_send_cmd(base_addr, NOR_CMD_WORD_PROGRAM); + mmio_write_32(base_addr, data); + + ret = nor_poll_dws(base_addr, DWS_WORD_PROGRAM_RETRIES); + if (ret != 0) { + goto word_program_end; + } + + /* Full status check */ + nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG); + status = mmio_read_32(base_addr); + + if (status & (NOR_PS | NOR_BLS)) { + nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG); + ret = -EPERM; + } + +word_program_end: + nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY); + return ret; +} + +void nor_lock(uintptr_t base_addr) +{ + nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK); + mmio_write_32(base_addr, NOR_2X16(NOR_LOCK_BLOCK)); + nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY); +} + +void nor_unlock(uintptr_t base_addr) +{ + nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK); + mmio_write_32(base_addr, NOR_2X16(NOR_UNLOCK_BLOCK)); + nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY); +} + From 380419738304533366ebc9fd3462351215fd0c6f Mon Sep 17 00:00:00 2001 From: Juan Castillo Date: Tue, 8 Jul 2014 17:20:41 +0100 Subject: [PATCH 2/3] Add a simple ARM SP805 watchdog driver Based on SP805 Programmer's model (ARM DDI 0270B). This driver provides three public APIs: void sp805_start(uintptr_t base, unsigned long ticks); void sp805_stop(uintptr_t base); void sp805_refresh(uintptr_t base, unsigned long ticks); Upon start, the watchdog starts counting down from the number of ticks specified. When the count reaches 0 an interrupt is triggered. The watchdog restarts counting down from the number of ticks specified. If the count reaches 0 again, the system is reset. A mechanism to handle the interrupt has not been implemented. Instead, the API to refresh the watchdog should be used instead to prevent a system reset. Change-Id: I799d53f8d1213b10b341a4a67fde6486e89a3dab --- drivers/arm/sp805/sp805.c | 74 +++++++++++++++++++++++++++++++++++++ include/drivers/arm/sp805.h | 58 +++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+) create mode 100644 drivers/arm/sp805/sp805.c create mode 100644 include/drivers/arm/sp805.h diff --git a/drivers/arm/sp805/sp805.c b/drivers/arm/sp805/sp805.c new file mode 100644 index 0000000000..4886e01fda --- /dev/null +++ b/drivers/arm/sp805/sp805.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* Inline register access functions */ + +static inline void sp805_write_wdog_load(uintptr_t base, unsigned long value) +{ + mmio_write_32(base + SP805_WDOG_LOAD_OFF, value); +} + +static inline void sp805_write_wdog_ctrl(uintptr_t base, unsigned long value) +{ + mmio_write_32(base + SP805_WDOG_CTR_OFF, value); +} + +static inline void sp805_write_wdog_lock(uintptr_t base, unsigned long value) +{ + mmio_write_32(base + SP805_WDOG_LOCK_OFF, value); +} + + +/* Public API implementation */ + +void sp805_start(uintptr_t base, unsigned long ticks) +{ + sp805_write_wdog_load(base, ticks); + sp805_write_wdog_ctrl(base, SP805_CTR_RESEN | SP805_CTR_INTEN); + /* Lock registers access */ + sp805_write_wdog_lock(base, 0); +} + +void sp805_stop(uintptr_t base) +{ + sp805_write_wdog_lock(base, WDOG_UNLOCK_KEY); + sp805_write_wdog_ctrl(base, 0); +} + +void sp805_refresh(uintptr_t base, unsigned long ticks) +{ + sp805_write_wdog_lock(base, WDOG_UNLOCK_KEY); + sp805_write_wdog_load(base, ticks); + sp805_write_wdog_lock(base, 0); +} diff --git a/include/drivers/arm/sp805.h b/include/drivers/arm/sp805.h new file mode 100644 index 0000000000..6bd8158731 --- /dev/null +++ b/include/drivers/arm/sp805.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SP805_H__ +#define __SP805_H__ + +/* SP805 register offset */ +#define SP805_WDOG_LOAD_OFF 0x000 +#define SP805_WDOG_CTR_OFF 0x008 +#define SP805_WDOG_LOCK_OFF 0xc00 + +/* Magic word to unlock the wd registers */ +#define WDOG_UNLOCK_KEY 0x1ACCE551 + +/* Register field definitions */ +#define SP805_CTR_RESEN (1 << 1) +#define SP805_CTR_INTEN (1 << 0) + +#ifndef __ASSEMBLY__ + +#include + +/* Public high level API */ + +void sp805_start(uintptr_t base, unsigned long ticks); +void sp805_stop(uintptr_t base); +void sp805_refresh(uintptr_t base, unsigned long ticks); + +#endif /* __ASSEMBLY__ */ + +#endif /* __SP805_H__ */ From 7b4c140514d83f2d78df00d94a09b4d5feb22480 Mon Sep 17 00:00:00 2001 From: Juan Castillo Date: Tue, 6 Oct 2015 14:01:35 +0100 Subject: [PATCH 3/3] TBB: add Trusted Watchdog support on ARM platforms This patch adds watchdog support on ARM platforms (FVP and Juno). A secure instance of SP805 is used as Trusted Watchdog. It is entirely managed in BL1, being enabled in the early platform setup hook and disabled in the exit hook. By default, the watchdog is enabled in every build (even when TBB is disabled). A new ARM platform specific build option `ARM_DISABLE_TRUSTED_WDOG` has been introduced to allow the user to disable the watchdog at build time. This feature may be used for testing or debugging purposes. Specific error handlers for Juno and FVP are also provided in this patch. These handlers will be called after an image load or authentication error. On FVP, the Table of Contents (ToC) in the FIP is erased. On Juno, the corresponding error code is stored in the V2M Non-Volatile flags register. In both cases, the CPU spins until a watchdog reset is generated after 256 seconds (as specified in the TBBR document). Change-Id: I9ca11dcb0fe15af5dbc5407ab3cf05add962f4b4 --- docs/user-guide.md | 8 +++ include/plat/arm/board/common/v2m_def.h | 9 +++- include/plat/arm/common/arm_def.h | 9 ++++ plat/arm/board/common/board_common.mk | 7 +-- plat/arm/board/common/board_css_common.c | 4 +- plat/arm/board/fvp/aarch64/fvp_common.c | 4 +- plat/arm/board/fvp/fvp_err.c | 65 ++++++++++++++++++++++++ plat/arm/board/fvp/platform.mk | 2 + plat/arm/board/juno/juno_err.c | 49 ++++++++++++++++++ plat/arm/board/juno/platform.mk | 4 +- plat/arm/common/arm_bl1_setup.c | 11 ++++ plat/arm/common/arm_common.mk | 10 ++++ 12 files changed, 173 insertions(+), 9 deletions(-) create mode 100644 plat/arm/board/fvp/fvp_err.c create mode 100644 plat/arm/board/juno/juno_err.c diff --git a/docs/user-guide.md b/docs/user-guide.md index 25f884efb9..9f9d0a5a5c 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -428,6 +428,14 @@ map is explained in the [Firmware Design]. in which case the platform is configured to expect NULL in the State-ID field of power-state parameter. +* `ARM_DISABLE_TRUSTED_WDOG`: boolean option to disable the Trusted Watchdog. + By default, ARM platforms use a watchdog to trigger a system reset in case + an error is encountered during the boot process (for example, when an image + could not be loaded or authenticated). The watchdog is enabled in the early + platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The + Trusted Watchdog may be disabled at build time for testing or development + purposes. + #### ARM CSS platform specific build options * `CSS_DETECT_PRE_1_7_0_SCP`: Boolean flag to detect SCP version diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h index 7a4ef5add1..7ed0af6c4a 100644 --- a/include/plat/arm/board/common/v2m_def.h +++ b/include/plat/arm/board/common/v2m_def.h @@ -38,6 +38,9 @@ #define V2M_SYS_ID 0x0 #define V2M_SYS_SWITCH 0x4 #define V2M_SYS_LED 0x8 +#define V2M_SYS_NVFLAGS 0x38 +#define V2M_SYS_NVFLAGSSET 0x38 +#define V2M_SYS_NVFLAGSCLR 0x3c #define V2M_SYS_CFGDATA 0xa0 #define V2M_SYS_CFGCTRL 0xa4 #define V2M_SYS_CFGSTATUS 0xa8 @@ -109,7 +112,11 @@ #define V2M_SP804_TIMER0_BASE 0x1C110000 #define V2M_SP804_TIMER1_BASE 0x1C120000 -#define V2M_MAP_FLASH0 MAP_REGION_FLAT(V2M_FLASH0_BASE,\ +#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ V2M_FLASH0_SIZE, \ MT_MEMORY | MT_RO | MT_SECURE) diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 452c38564d..4726d5e532 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -175,6 +175,15 @@ #define ARM_CONSOLE_BAUDRATE 115200 +/* Trusted Watchdog constants */ +#define ARM_SP805_TWDG_BASE 0x2a490000 +#define ARM_SP805_TWDG_CLK_HZ 32768 +/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 + * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ +#define ARM_TWDG_TIMEOUT_SEC 128 +#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ + ARM_TWDG_TIMEOUT_SEC) + /****************************************************************************** * Required platform porting definitions common to all ARM standard platforms *****************************************************************************/ diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk index bec49ed278..9e0c84843c 100644 --- a/plat/arm/board/common/board_common.mk +++ b/plat/arm/board/common/board_common.mk @@ -28,14 +28,15 @@ # POSSIBILITY OF SUCH DAMAGE. # -PLAT_INCLUDES += -Iinclude/plat/arm/board/common/ +PLAT_INCLUDES += -Iinclude/plat/arm/board/common/ \ + -Iinclude/plat/arm/board/common/drivers PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/pl011_console.S \ plat/arm/board/common/aarch64/board_arm_helpers.S -#BL1_SOURCES += +BL1_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c -#BL2_SOURCES += +BL2_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c #BL31_SOURCES += diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/common/board_css_common.c index 3bb3dd6fd4..7bf0273d14 100644 --- a/plat/arm/board/common/board_css_common.c +++ b/plat/arm/board/common/board_css_common.c @@ -38,7 +38,7 @@ #if IMAGE_BL1 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, - V2M_MAP_FLASH0, + V2M_MAP_FLASH0_RO, V2M_MAP_IOFPGA, CSS_MAP_DEVICE, SOC_CSS_MAP_DEVICE, @@ -48,7 +48,7 @@ const mmap_region_t plat_arm_mmap[] = { #if IMAGE_BL2 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, - V2M_MAP_FLASH0, + V2M_MAP_FLASH0_RO, V2M_MAP_IOFPGA, CSS_MAP_DEVICE, SOC_CSS_MAP_DEVICE, diff --git a/plat/arm/board/fvp/aarch64/fvp_common.c b/plat/arm/board/fvp/aarch64/fvp_common.c index 58b646a45c..8771e5b4fb 100644 --- a/plat/arm/board/fvp/aarch64/fvp_common.c +++ b/plat/arm/board/fvp/aarch64/fvp_common.c @@ -68,7 +68,7 @@ arm_config_t arm_config; #if IMAGE_BL1 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, - V2M_MAP_FLASH0, + V2M_MAP_FLASH0_RW, V2M_MAP_IOFPGA, MAP_DEVICE0, MAP_DEVICE1, @@ -79,7 +79,7 @@ const mmap_region_t plat_arm_mmap[] = { #if IMAGE_BL2 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, - V2M_MAP_FLASH0, + V2M_MAP_FLASH0_RW, V2M_MAP_IOFPGA, MAP_DEVICE0, MAP_DEVICE1, diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c new file mode 100644 index 0000000000..7867e49c46 --- /dev/null +++ b/plat/arm/board/fvp/fvp_err.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* + * FVP error handler + */ +void plat_error_handler(int err) +{ + int ret; + + switch (err) { + case -ENOENT: + case -EAUTH: + /* Image load or authentication error. Erase the ToC */ + INFO("Erasing FIP ToC from flash...\n"); + nor_unlock(PLAT_ARM_FIP_BASE); + ret = nor_word_program(PLAT_ARM_FIP_BASE, 0); + if (ret) { + ERROR("Cannot erase ToC\n"); + } else { + INFO("Done\n"); + } + break; + default: + /* Unexpected error */ + break; + } + + /* Loop until the watchdog resets the system */ + for (;;) + ; +} diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 51b718ee13..c46d3b7119 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -41,6 +41,7 @@ BL1_SOURCES += drivers/io/io_semihosting.c \ lib/semihosting/aarch64/semihosting_call.S \ plat/arm/board/fvp/aarch64/fvp_helpers.S \ plat/arm/board/fvp/fvp_bl1_setup.c \ + plat/arm/board/fvp/fvp_err.c \ plat/arm/board/fvp/fvp_io_storage.c BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \ @@ -49,6 +50,7 @@ BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \ lib/semihosting/semihosting.c \ lib/semihosting/aarch64/semihosting_call.S \ plat/arm/board/fvp/fvp_bl2_setup.c \ + plat/arm/board/fvp/fvp_err.c \ plat/arm/board/fvp/fvp_io_storage.c \ plat/arm/board/fvp/fvp_security.c diff --git a/plat/arm/board/juno/juno_err.c b/plat/arm/board/juno/juno_err.c new file mode 100644 index 0000000000..497cc7fa3c --- /dev/null +++ b/plat/arm/board/juno/juno_err.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS) + +/* + * Juno error handler + */ +void plat_error_handler(int err) +{ + uint32_t *flags_ptr = (uint32_t *)V2M_SYS_NVFLAGS_ADDR; + + /* Propagate the err code in the NV-flags register */ + *flags_ptr = err; + + /* Loop until the watchdog resets the system */ + for (;;) + ; +} diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index b711f3d5df..127dcbea86 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -34,9 +34,11 @@ PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ - lib/cpus/aarch64/cortex_a72.S + lib/cpus/aarch64/cortex_a72.S \ + plat/arm/board/juno/juno_err.c BL2_SOURCES += plat/arm/board/juno/juno_security.c \ + plat/arm/board/juno/juno_err.c BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index 887223cf4f..79c7d94409 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "../../../bl1/bl1_private.h" @@ -74,6 +75,11 @@ void arm_bl1_early_platform_setup(void) { const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; +#if !ARM_DISABLE_TRUSTED_WDOG + /* Enable watchdog */ + sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); +#endif + /* Initialize the console to provide early debug support */ console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE); @@ -147,6 +153,11 @@ void bl1_platform_setup(void) void bl1_plat_prepare_exit(entry_point_info_t *ep_info) { +#if !ARM_DISABLE_TRUSTED_WDOG + /* Disable watchdog before leaving BL1 */ + sp805_stop(ARM_SP805_TWDG_BASE); +#endif + #ifdef EL3_PAYLOAD_BASE /* * Program the EL3 payload's entry point address into the CPUs mailbox diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 7b23527598..1290cef3cc 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -63,6 +63,15 @@ endif $(eval $(call assert_boolean,ARM_RECOM_STATE_ID_ENC)) $(eval $(call add_define,ARM_RECOM_STATE_ID_ENC)) +# Process ARM_DISABLE_TRUSTED_WDOG flag +# By default, Trusted Watchdog is always enabled unless SPIN_ON_BL1_EXIT is set +ARM_DISABLE_TRUSTED_WDOG := 0 +ifeq (${SPIN_ON_BL1_EXIT}, 1) +ARM_DISABLE_TRUSTED_WDOG := 1 +endif +$(eval $(call assert_boolean,ARM_DISABLE_TRUSTED_WDOG)) +$(eval $(call add_define,ARM_DISABLE_TRUSTED_WDOG)) + PLAT_INCLUDES += -Iinclude/common/tbbr \ -Iinclude/plat/arm/common \ -Iinclude/plat/arm/common/aarch64 @@ -75,6 +84,7 @@ PLAT_BL_COMMON_SOURCES += lib/aarch64/xlat_tables.c \ BL1_SOURCES += drivers/arm/cci/cci.c \ drivers/arm/ccn/ccn.c \ + drivers/arm/sp805/sp805.c \ drivers/io/io_fip.c \ drivers/io/io_memmap.c \ drivers/io/io_storage.c \