From 3bcc4af4b6bb23280b3f87072b90162bb4ff73f5 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 15 May 2013 14:22:30 -0700 Subject: [PATCH] haswell: move 5V rail enable/disable actions The 5V rail should be enabled on S5->S3 transitions and disabled on S3->S5 transitions. BUG=chrome-os-partner:19398 BRANCH=none TEST=successful state transitions: S0,S3,S5,G3 Change-Id: If9fd7ef16f015136238dd18f64602ecf33d9ec4a Signed-off-by: Aaron Durbin Reviewed-on: https://gerrit.chromium.org/gerrit/51359 Reviewed-by: Duncan Laurie --- common/x86_power_haswell.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/common/x86_power_haswell.c b/common/x86_power_haswell.c index befad53954..9e7d973db9 100644 --- a/common/x86_power_haswell.c +++ b/common/x86_power_haswell.c @@ -499,13 +499,6 @@ void chipset_task(void) break; case X86_G3S5: - gpio_set_level(GPIO_PP5000_EN, 1); - if (wait_in_signals(IN_PGOOD_PP5000)) { - chipset_force_shutdown(); - state = X86_G3; - break; - } - /* * Wait 10ms after +3VALW good, since that powers * VccDSW and VccSUS. @@ -537,6 +530,14 @@ void chipset_task(void) break; case X86_S5S3: + /* Enable PP5000 (5V) rail. */ + gpio_set_level(GPIO_PP5000_EN, 1); + if (wait_in_signals(IN_PGOOD_PP5000)) { + chipset_force_shutdown(); + state = X86_G3; + break; + } + /* Wait for the always-on rails to be good */ if (wait_in_signals(IN_PGOOD_ALWAYS_ON)) { chipset_force_shutdown(); @@ -640,6 +641,9 @@ void chipset_task(void) /* Turn off power to RAM */ gpio_set_level(GPIO_PP1350_EN, 0); + /* Disable PP5000 (5V) rail. */ + gpio_set_level(GPIO_PP5000_EN, 0); + state = X86_S5; break; @@ -648,7 +652,6 @@ void chipset_task(void) gpio_set_level(GPIO_PCH_DPWROK, 0); gpio_set_level(GPIO_PCH_RSMRST_L, 0); - gpio_set_level(GPIO_PP5000_EN, 0); gpio_set_level(GPIO_SUSP_VR_EN, 0); /* Record the time we go into G3 */