From 40fd072548ab47ce21bc48dc8059513048693f4e Mon Sep 17 00:00:00 2001 From: Andrew Thoelke Date: Thu, 24 Apr 2014 15:33:24 +0100 Subject: [PATCH] Set processor endianness immediately after RESET SCTLR_EL3.EE is being configured too late in bl1_arch_setup() and bl31_arch_setup() after data accesses have already occured on the cold and warm boot paths. This control bit must be configured immediately on CPU reset to match the endian state of the firmware (little endian). Fixes ARM-software/tf-issues#145 Change-Id: Ie12e46fbbed6baf024c30beb50751591bb8c8655 --- bl1/aarch64/bl1_arch_setup.c | 3 +-- bl1/aarch64/bl1_entrypoint.S | 10 ++++++++++ bl31/aarch64/bl31_arch_setup.c | 3 +-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index 758b8e8feb..1b14246b70 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -39,10 +39,9 @@ void bl1_arch_setup(void) { unsigned long tmp_reg = 0; - /* Enable alignment checks and set the exception endianess to LE */ + /* Enable alignment checks */ tmp_reg = read_sctlr_el3(); tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - tmp_reg &= ~SCTLR_EE_BIT; write_sctlr_el3(tmp_reg); /* diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index 012b779c77..62e12181da 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -42,6 +42,16 @@ */ func bl1_entrypoint + /* --------------------------------------------- + * Set the CPU endianness before doing anything + * that might involve memory reads or writes + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + /* --------------------------------------------- * Perform any processor specific actions upon * reset e.g. cache, tlb invalidations etc. diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c index acaa6b5710..ad73de022e 100644 --- a/bl31/aarch64/bl31_arch_setup.c +++ b/bl31/aarch64/bl31_arch_setup.c @@ -45,10 +45,9 @@ void bl31_arch_setup(void) unsigned long tmp_reg = 0; uint64_t counter_freq; - /* Enable alignment checks and set the exception endianness to LE */ + /* Enable alignment checks */ tmp_reg = read_sctlr_el3(); tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - tmp_reg &= ~SCTLR_EE_BIT; write_sctlr_el3(tmp_reg); /*