From 4a7aceed59e1ff3df7078859aac4031befd64b11 Mon Sep 17 00:00:00 2001 From: Aseda Aboagye Date: Wed, 20 Dec 2017 11:29:51 -0800 Subject: [PATCH] power: cannonlake: SLP_SUS_L deasserted == S5. When SLP_SUS_L is deasserted, that means the chipset is in S5. BUG=None BRANCH=None TEST=Flash meowth; boot from AC only, verify that when SoC actually boots the power state is reported as S0 instead of G3. Change-Id: Ib9cd76aa9efd6f81df432205b8c1e8c342e32af6 Signed-off-by: Aseda Aboagye Reviewed-on: https://chromium-review.googlesource.com/837485 Commit-Ready: Aseda Aboagye Tested-by: Aseda Aboagye Reviewed-by: Aaron Durbin --- power/cannonlake.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/power/cannonlake.c b/power/cannonlake.c index b07114eced..7a1241363f 100644 --- a/power/cannonlake.c +++ b/power/cannonlake.c @@ -113,6 +113,12 @@ enum power_state power_handle_state(enum power_state state) } switch (state) { + case POWER_G3: + /* If SLP_SUS_L is deasserted, we're no longer in G3. */ + if (power_has_signals(IN_PCH_SLP_SUS_DEASSERTED)) + return POWER_S5; + break; + case POWER_G3S5: /* Turn on the PP3300_DSW rail. */ gpio_set_level(GPIO_EN_PP3300_DSW, 1);