diff --git a/docs/diagrams/default_reset_code.png b/docs/diagrams/default_reset_code.png index e7e0d85563..d8675e4a3f 100644 Binary files a/docs/diagrams/default_reset_code.png and b/docs/diagrams/default_reset_code.png differ diff --git a/docs/diagrams/reset_code_flow.dia b/docs/diagrams/reset_code_flow.dia index 5de00dad08..133c9cf69c 100644 Binary files a/docs/diagrams/reset_code_flow.dia and b/docs/diagrams/reset_code_flow.dia differ diff --git a/docs/diagrams/reset_code_no_boot_type_check.png b/docs/diagrams/reset_code_no_boot_type_check.png index 8ce7e97ac2..23e865f62f 100644 Binary files a/docs/diagrams/reset_code_no_boot_type_check.png and b/docs/diagrams/reset_code_no_boot_type_check.png differ diff --git a/docs/diagrams/reset_code_no_checks.png b/docs/diagrams/reset_code_no_checks.png index 8a02f0f828..26a179bc53 100644 Binary files a/docs/diagrams/reset_code_no_checks.png and b/docs/diagrams/reset_code_no_checks.png differ diff --git a/docs/diagrams/reset_code_no_cpu_check.png b/docs/diagrams/reset_code_no_cpu_check.png index 8b05ea4d88..4150dbefeb 100644 Binary files a/docs/diagrams/reset_code_no_cpu_check.png and b/docs/diagrams/reset_code_no_cpu_check.png differ diff --git a/include/common/el3_common_macros.S b/include/common/el3_common_macros.S index 6f7136f94e..32df7d7634 100644 --- a/include/common/el3_common_macros.S +++ b/include/common/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -171,9 +171,19 @@ do_cold_boot: .endif /* _warm_boot_mailbox */ + /* --------------------------------------------------------------------- + * It is a cold boot. + * Perform any processor specific actions upon reset e.g. cache, TLB + * invalidations etc. + * --------------------------------------------------------------------- + */ + bl reset_handler + + el3_arch_init_common \_exception_vectors + .if \_secondary_cold_boot /* ------------------------------------------------------------- - * It is a cold boot. + * Check if this is a primary or secondary CPU cold boot. * The primary CPU will set up the platform while the * secondaries are placed in a platform-specific state until the * primary CPU performs the necessary actions to bring them out @@ -193,13 +203,10 @@ .endif /* _secondary_cold_boot */ /* --------------------------------------------------------------------- - * Perform any processor specific actions upon reset e.g. cache, TLB - * invalidations etc. + * Initialize memory now. Secondary CPU initialization won't get to this + * point. * --------------------------------------------------------------------- */ - bl reset_handler - - el3_arch_init_common \_exception_vectors .if \_init_memory bl platform_mem_init