diff --git a/power/cannonlake.c b/power/cannonlake.c
index 18a20ebef0..535010c103 100644
--- a/power/cannonlake.c
+++ b/power/cannonlake.c
@@ -53,26 +53,28 @@ void chipset_handle_espi_reset_assert(void)
 
 void chipset_reset(int cold_reset)
 {
-	CPRINTS("%s(%d)", __func__, cold_reset);
+	/*
+	 * The EC cannot control warm vs cold reset of the chipset using
+	 * SYS_RESET_L;  it's more of a request.
+	 */
+	CPRINTS("%s()", __func__);
 
-	if (cold_reset) {
-		if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
-			return;
-		gpio_set_level(GPIO_SYS_RESET_L, 0);
-		/* Debounce time for SYS_RESET_L is 16 ms */
-		udelay(20 * MSEC);
-		gpio_set_level(GPIO_SYS_RESET_L, 1);
-	} else {
-		/* Warm reset. */
-		/*
-		 * TODO(aaboagye): something about platform reset??  But we
-		 * don't have that...
-		 */
-	}
+	if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
+		return;
+
+	/*
+	 * Debounce time for SYS_RESET_L is 16 ms.  Wait twice that period to be
+	 * safe.
+	 */
+	gpio_set_level(GPIO_SYS_RESET_L, 0);
+	udelay(32 * MSEC);
+	gpio_set_level(GPIO_SYS_RESET_L, 1);
 }
 
 enum power_state chipset_force_g3(void)
 {
+	chipset_force_shutdown();
+
 	CPRINTS("Faking G3.  (NOOP for now.)");
 	/* TODO(aaboagye): Do the right thing for real. */
 	/* TODO(aaboagye): maybe turn off DSW load switch. */
diff --git a/power/cannonlake.h b/power/cannonlake.h
index da67c7cbb8..404558441f 100644
--- a/power/cannonlake.h
+++ b/power/cannonlake.h
@@ -17,8 +17,7 @@
 				  IN_PCH_SLP_S4_DEASSERTED | \
 				  IN_PCH_SLP_SUS_DEASSERTED)
 
-/* TODO(aaboagye): Should this be PMIC_DPWROK ? */
-#define IN_PGOOD_ALL_CORE 0
+#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK)
 
 #define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)