diff --git a/board/snow/board.c b/board/snow/board.c
index 8c97c24790..0d10bbc6d3 100644
--- a/board/snow/board.c
+++ b/board/snow/board.c
@@ -49,8 +49,10 @@ const struct gpio_info gpio_list[GPIO_COUNT] = {
 	{"EN_PP5000",   GPIO_A, (1<<11),  GPIO_OUT_LOW, NULL},
 	{"EN_PP3300",   GPIO_A, (1<<8),  GPIO_OUT_LOW, NULL},
 	{"PMIC_PWRON_L",GPIO_A, (1<<12), GPIO_OUT_HIGH, NULL},
+	{"ENTERING_RW", GPIO_D, (1<<0),  GPIO_OUT_LOW, NULL},
 	{"CHARGER_EN",  GPIO_B, (1<<2),  GPIO_OUT_LOW, NULL},
 	{"EC_INT",      GPIO_B, (1<<9),  GPIO_HI_Z, NULL},
+	{"CODEC_INT",   GPIO_D, (1<<1),  GPIO_HI_Z, NULL},
 	{"KB_OUT00",    GPIO_B, (1<<0),  GPIO_KB_OUTPUT, NULL},
 	{"KB_OUT01",    GPIO_B, (1<<8),  GPIO_KB_OUTPUT, NULL},
 	{"KB_OUT02",    GPIO_B, (1<<12), GPIO_KB_OUTPUT, NULL},
@@ -80,6 +82,9 @@ void configure_board(void)
 	/* Enable SPI */
 	STM32_RCC_APB2ENR |= (1<<12);
 
+	/* remap OSC_IN/OSC_OUT to PD0/PD1 */
+	STM32_GPIO_AFIO_MAPR |= 1 << 15;
+
 	/* SPI1 on pins PA4-7 (alt. function push-pull, 10MHz) */
 	val = STM32_GPIO_CRL_OFF(GPIO_A) & ~0xffff0000;
 	val |= 0x99990000;
diff --git a/board/snow/board.h b/board/snow/board.h
index 0688c74b44..564ca29e59 100644
--- a/board/snow/board.h
+++ b/board/snow/board.h
@@ -56,8 +56,10 @@ enum gpio_signal {
 	GPIO_EN_PP5000,        /* 5.0v rail enable */
 	GPIO_EN_PP3300,        /* 3.3v rail enable */
 	GPIO_PMIC_PWRON_L,     /* 5v rail ready */
+	GPIO_EC_ENTERING_RW,   /* EC is R/W mode for the kbc mux */
 	GPIO_CHARGER_EN,
 	GPIO_EC_INT,
+	GPIO_CODEC_INT,        /* To audio codec (KB noise cancellation) */
 	GPIO_KB_OUT00,
 	GPIO_KB_OUT01,
 	GPIO_KB_OUT02,
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index e11364f60c..33b8c5c703 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -235,13 +235,9 @@
 
 #define STM32_AFIO_BASE             0x40010000
 #define STM32_AFIO_EXTICR(n)        REG32(STM32_AFIO_BASE + 8 + 4 * (n))
-#define STM32_GPIO_AFIO_EVCR_OFF(b) REG16((b) + 0x00)
-#define STM32_GPIO_AFIO_MAPR_OFF(b) REG32((b) + 0x04)
-#define STM32_GPIO_AFIO_EXTICR1(b)  REG16((b) + 0x08)
-#define STM32_GPIO_AFIO_EXTICR2(b)  REG16((b) + 0x0c)
-#define STM32_GPIO_AFIO_EXTICR3(b)  REG16((b) + 0x10)
-#define STM32_GPIO_AFIO_EXTICR4(b)  REG16((b) + 0x14)
-#define STM32_GPIO_AFIO_MAPR2(b)    REG16((b) + 0x1c)
+#define STM32_GPIO_AFIO_EVCR        REG32(STM32_AFIO_BASE + 0x00)
+#define STM32_GPIO_AFIO_MAPR        REG32(STM32_AFIO_BASE + 0x04)
+#define STM32_GPIO_AFIO_MAPR2       REG32(STM32_AFIO_BASE + 0x1c)
 
 #else
 #error Unsupported chip variant