From 68eb480a882627b5477c39eddde95656dd568758 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Wed, 17 Aug 2016 13:08:27 -0700 Subject: [PATCH] reef: Drive PMU_RSTBTN_N manually for proto boards Due to what appaers to be a leakage issue, this patch drives the SYS_RST_ODL (aka PMU_RSTBTN_N) pin low for 1sec while the power state transitions from S3 to S0. This is a workaround for a proto board issue that prevents the SoC from booting. BUG=chrome-os-partner:53791 BRANCH=none TEST=SoC boots with CL:347754 applied on proto and EVT boards Change-Id: I88c3ccf18280acf5dfe3b99f99483dc4e4e27873 Signed-off-by: David Hendricks Reviewed-on: https://chromium-review.googlesource.com/372044 Reviewed-by: Martin Roth --- board/reef/board.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/reef/board.c b/board/reef/board.c index bb0aa55df9..93dcb2dfeb 100644 --- a/board/reef/board.c +++ b/board/reef/board.c @@ -560,6 +560,22 @@ static void board_chipset_startup(void) } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); +#if IS_PROTO == 1 +/* + * FIXME: This is a workaround for chrome-os-partner:53791. As per comment #53 + * this issue should not occur on boards newer than proto. + */ +static void drive_sys_rst_odl_high(void) +{ + gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_OUT_HIGH); + CPRINTS("SYS_RST_ODL driven high"); + msleep(1000); + gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_ODR_HIGH); + CPRINTS("SYS_RST_ODL left floating (open-drain)"); +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, drive_sys_rst_odl_high, HOOK_PRIO_DEFAULT); +#endif + /* Called on AP S3 -> S5 transition */ static void board_chipset_shutdown(void) {