From 72b8d6f199e32a88a89f343b7ec2cf17243b4f6f Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Wed, 20 Jul 2016 17:59:34 -0700 Subject: [PATCH] npcx: shi: Properly mux pins as GPIO when disabling SHI MODULE_SHI is used for the SPI master interface pins, so don't reconfigure those. Instead manually configure the SHI pins using the appropriate DEVALT bit. BUG=chrome-os-partner:54328 BRANCH=None TEST=Manual on kevin. Verify SHI continues to function on cold boot, sysjump and resume from S3. Verify SPI sensors now function on resume from S3 - `accelinit 0` succeeds. Signed-off-by: Shawn Nematbakhsh Change-Id: I63f028968f3d0dbc9d7ca7dacc70c9c399f7a180 Reviewed-on: https://chromium-review.googlesource.com/362061 Commit-Ready: Shawn N Tested-by: Caesar Wang Tested-by: Shawn N Reviewed-by: Aseda Aboagye Reviewed-by: Mulin Chao --- chip/npcx/shi.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c index 482d0b74b8..4698740c19 100644 --- a/chip/npcx/shi.c +++ b/chip/npcx/shi.c @@ -742,6 +742,12 @@ static void shi_enable(void) #endif gpio_set_flags(GPIO_SHI_CS_L, gpio_flags); + /* + * Mux SHI related pins + * SHI_SDI SHI_SDO SHI_CS# SHI_SCLK are selected to device pins + */ + SET_BIT(NPCX_DEVALT(ALT_GROUP_C), NPCX_DEVALTC_SHI_SL); + /* Enable SHI_CS_L interrupt */ gpio_enable_interrupt(GPIO_SHI_CS_L); } @@ -770,8 +776,12 @@ static void shi_disable(void) /* Disable pullup and interrupts on SHI_CS_L */ gpio_set_flags(GPIO_SHI_CS_L, GPIO_INPUT); - /* Set SPI pins to inputs so we don't leak power when AP is off */ - gpio_config_module(MODULE_SPI, 0); + /* + * Mux SHI related pins + * SHI_SDI SHI_SDO SHI_CS# SHI_SCLK are selected to GPIO + * (Default GPIO config = input) + */ + CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_C), NPCX_DEVALTC_SHI_SL); } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, shi_disable, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_SYSJUMP, shi_disable, HOOK_PRIO_DEFAULT); @@ -780,11 +790,6 @@ static void shi_init(void) { /* Power on SHI module first */ CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_SHI_PD); - /* - * Mux SHI related pins - * SHI_SDI SHI_SDO SHI_CS# SHI_SCLK are selected to device pins - */ - SET_BIT(NPCX_DEVALT(ALT_GROUP_C), NPCX_DEVALTC_SHI_SL); /* * SHICFG1 (SHI Configuration 1) setting