diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c
index a0a02791ca..2274f256dc 100644
--- a/chip/npcx/flash.c
+++ b/chip/npcx/flash.c
@@ -40,6 +40,7 @@ static struct mutex flash_lock;
 
 /*****************************************************************************/
 /* flash internal functions */
+#if !defined(NPCX_INT_FLASH_SUPPORT)
 static void flash_pinmux(int enable)
 {
 	/* Select pin-mux for FIU*/
@@ -57,6 +58,7 @@ static void flash_pinmux(int enable)
 		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
 	}
 }
+#endif
 
 static void flash_execute_cmd(uint8_t code, uint8_t cts)
 {
@@ -683,8 +685,10 @@ int flash_pre_init(void)
 	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
 #endif
 
+#if !defined(NPCX_INT_FLASH_SUPPORT)
 	/* Enable FIU interface */
 	flash_pinmux(1);
+#endif
 
 #ifdef CONFIG_EXTERNAL_STORAGE
 	/* Disable tristate all the time */
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index efc4458ecb..c06aff4d32 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -367,7 +367,9 @@ void gpio_pre_init(void)
 
 	/* Pin_Mux for FIU/SPI (set to GPIO) */
 	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
+#if defined(NPCX_INT_FLASH_SUPPORT)
 	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
+#endif
 
 	/* Pin_Mux for PWRGD */
 	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_NO_PWRGD);