From 097b787a0e6dc65ff4bf7c6e1da966858036e22a Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Thu, 14 Apr 2016 12:59:42 +0100 Subject: [PATCH 1/7] Fix wording in cpu-ops.mk comments The CPU errata build flags don't enable errata, they enable errata workarounds. Change-Id: Ica65689d1205fc54eee9081a73442144b973400f --- lib/cpus/cpu-ops.mk | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index a3a08e155f..1ed7d140f3 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -53,24 +53,25 @@ $(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT)) $(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT)) -# CPU Errata Build flags. These should be enabled by the -# platform if the errata needs to be applied. +# CPU Errata Build flags. +# These should be enabled by the platform if the erratum workaround needs to be +# applied. -# Flag to apply errata 826319 during reset. This errata applies only to -# revision <= r0p2 of the Cortex A53 cpu. +# Flag to apply erratum 826319 workaround during reset. This erratum applies +# only to revision <= r0p2 of the Cortex A53 cpu. ERRATA_A53_826319 ?=0 -# Flag to apply errata 836870 during reset. This errata applies only to -# revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this -# errata is enabled by default. +# Flag to apply erratum 836870 workaround during reset. This erratum applies +# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this +# erratum workaround is enabled by default. ERRATA_A53_836870 ?=0 -# Flag to apply errata 806969 during reset. This errata applies only to -# revision r0p0 of the Cortex A57 cpu. +# Flag to apply erratum 806969 workaround during reset. This erratum applies +# only to revision r0p0 of the Cortex A57 cpu. ERRATA_A57_806969 ?=0 -# Flag to apply errata 813420 during reset. This errata applies only to -# revision r0p0 of the Cortex A57 cpu. +# Flag to apply erratum 813420 workaround during reset. This erratum applies +# only to revision r0p0 of the Cortex A57 cpu. ERRATA_A57_813420 ?=0 # Process ERRATA_A53_826319 flag From df22d602b6b1ee00a0cb31e88bb63e7152f2cf6a Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Thu, 14 Apr 2016 13:32:31 +0100 Subject: [PATCH 2/7] Add support for Cortex-A57 erratum 826974 workaround Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4 --- docs/cpu-specific-build-macros.md | 3 +++ include/lib/cpus/aarch64/cortex_a57.h | 1 + lib/cpus/aarch64/cortex_a57.S | 32 +++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++++ 4 files changed, 44 insertions(+) diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index c57dc7ee54..408af36bfe 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -60,6 +60,9 @@ For Cortex-A57, following errata build flags are defined : * `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU. +* `ERRATA_A57_826974`: This applies errata 826974 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p1 of the CPU. + 3. CPU Specific optimizations ------------------------------ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index c512129a17..7711e690aa 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -61,6 +61,7 @@ ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ +#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) #define CPUACTLR_DIS_OVERREAD (1 << 52) #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 4c0b8ce381..d992f98b72 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -167,6 +167,33 @@ disable_hint: ret endfunc a57_disable_ldnp_overread + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #826974. + * This applies only to revision <= r1p1 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_826974_wa + /* + * Compare x0 against revision r1p1 + */ + cmp x0, #0x11 + b.ls apply_826974 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_826974: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_826974_wa + + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Clobbers: x0-x5, x15, x19, x30 @@ -200,6 +227,11 @@ func cortex_a57_reset_func bl a57_disable_ldnp_overread #endif +#if ERRATA_A57_826974 + mov x0, x15 + bl errata_a57_826974_wa +#endif + /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 1ed7d140f3..3ea462bb62 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -74,6 +74,10 @@ ERRATA_A57_806969 ?=0 # only to revision r0p0 of the Cortex A57 cpu. ERRATA_A57_813420 ?=0 +# Flag to apply erratum 826974 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A57 cpu. +ERRATA_A57_826974 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -89,3 +93,7 @@ $(eval $(call add_define,ERRATA_A57_806969)) # Process ERRATA_A57_813420 flag $(eval $(call assert_boolean,ERRATA_A57_813420)) $(eval $(call add_define,ERRATA_A57_813420)) + +# Process ERRATA_A57_826974 flag +$(eval $(call assert_boolean,ERRATA_A57_826974)) +$(eval $(call add_define,ERRATA_A57_826974)) From a8b1c769361c63a69fd73afe37bb4799446ec045 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Thu, 14 Apr 2016 14:04:48 +0100 Subject: [PATCH 3/7] Add support for Cortex-A57 erratum 828024 workaround Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d --- docs/cpu-specific-build-macros.md | 3 +++ include/lib/cpus/aarch64/cortex_a57.h | 2 ++ lib/cpus/aarch64/cortex_a57.S | 35 +++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 4 files changed, 48 insertions(+) diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index 408af36bfe..5d34409fd1 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -63,6 +63,9 @@ For Cortex-A57, following errata build flags are defined : * `ERRATA_A57_826974`: This applies errata 826974 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. +* `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p1 of the CPU. + 3. CPU Specific optimizations ------------------------------ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 7711e690aa..68d0821cfb 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -65,6 +65,8 @@ #define CPUACTLR_DIS_OVERREAD (1 << 52) #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CPUACTLR_DIS_STREAMING (3 << 27) +#define CPUACTLR_DIS_L1_STREAMING (3 << 25) /******************************************************************************* * L2 Control register specific definitions. diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index d992f98b72..ec32ce78df 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -193,6 +193,37 @@ apply_826974: ret endfunc errata_a57_826974_wa + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #828024. + * This applies only to revision <= r1p1 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_828024_wa + /* + * Compare x0 against revision r1p1 + */ + cmp x0, #0x11 + b.ls apply_828024 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_828024: + mrs x1, CPUACTLR_EL1 + /* + * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 + * instructions here because the resulting bitmask doesn't fit in a + * 16-bit value so it cannot be encoded in a single instruction. + */ + orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA + orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_828024_wa /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. @@ -232,6 +263,10 @@ func cortex_a57_reset_func bl errata_a57_826974_wa #endif +#if ERRATA_A57_828024 + mov x0, x15 + bl errata_a57_828024_wa +#endif /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 3ea462bb62..7d9f2b72dc 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -78,6 +78,10 @@ ERRATA_A57_813420 ?=0 # only to revision <= r1p1 of the Cortex A57 cpu. ERRATA_A57_826974 ?=0 +# Flag to apply erratum 828024 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A57 cpu. +ERRATA_A57_828024 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -97,3 +101,7 @@ $(eval $(call add_define,ERRATA_A57_813420)) # Process ERRATA_A57_826974 flag $(eval $(call assert_boolean,ERRATA_A57_826974)) $(eval $(call add_define,ERRATA_A57_826974)) + +# Process ERRATA_A57_828024 flag +$(eval $(call assert_boolean,ERRATA_A57_828024)) +$(eval $(call add_define,ERRATA_A57_828024)) From 0b77197baf9a22625f91112cf009c9209f4279e8 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Thu, 14 Apr 2016 14:18:07 +0100 Subject: [PATCH 4/7] Add support for Cortex-A57 erratum 829520 workaround Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439 --- docs/cpu-specific-build-macros.md | 3 +++ include/lib/cpus/aarch64/cortex_a57.h | 1 + lib/cpus/aarch64/cortex_a57.S | 32 +++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++++ 4 files changed, 44 insertions(+) diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index 5d34409fd1..94d05d574d 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -66,6 +66,9 @@ For Cortex-A57, following errata build flags are defined : * `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. +* `ERRATA_A57_829520`: This applies errata 829520 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p2 of the CPU. + 3. CPU Specific optimizations ------------------------------ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 68d0821cfb..95c1f56c17 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -67,6 +67,7 @@ #define CPUACTLR_DCC_AS_DCCI (1 << 44) #define CPUACTLR_DIS_STREAMING (3 << 27) #define CPUACTLR_DIS_L1_STREAMING (3 << 25) +#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) /******************************************************************************* * L2 Control register specific definitions. diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index ec32ce78df..25def1cdda 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -225,6 +225,32 @@ apply_828024: ret endfunc errata_a57_828024_wa + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #829520. + * This applies only to revision <= r1p2 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_829520_wa + /* + * Compare x0 against revision r1p2 + */ + cmp x0, #0x12 + b.ls apply_829520 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_829520: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_829520_wa + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Clobbers: x0-x5, x15, x19, x30 @@ -267,6 +293,12 @@ func cortex_a57_reset_func mov x0, x15 bl errata_a57_828024_wa #endif + +#if ERRATA_A57_829520 + mov x0, x15 + bl errata_a57_829520_wa +#endif + /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 7d9f2b72dc..62de70f514 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -82,6 +82,10 @@ ERRATA_A57_826974 ?=0 # only to revision <= r1p1 of the Cortex A57 cpu. ERRATA_A57_828024 ?=0 +# Flag to apply erratum 829520 workaround during reset. This erratum applies +# only to revision <= r1p2 of the Cortex A57 cpu. +ERRATA_A57_829520 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -105,3 +109,7 @@ $(eval $(call add_define,ERRATA_A57_826974)) # Process ERRATA_A57_828024 flag $(eval $(call assert_boolean,ERRATA_A57_828024)) $(eval $(call add_define,ERRATA_A57_828024)) + +# Process ERRATA_A57_829520 flag +$(eval $(call assert_boolean,ERRATA_A57_829520)) +$(eval $(call add_define,ERRATA_A57_829520)) From 072888656dc331c6b4bded88738e7b34166c0933 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Thu, 14 Apr 2016 14:24:13 +0100 Subject: [PATCH 5/7] Add support for Cortex-A57 erratum 826977 workaround Change-Id: Icaacd19c4cef9c10d02adcc2f84a4d7c97d4bcfa --- docs/cpu-specific-build-macros.md | 3 +++ include/lib/cpus/aarch64/cortex_a57.h | 1 + lib/cpus/aarch64/cortex_a57.S | 31 +++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++++ 4 files changed, 43 insertions(+) diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index 94d05d574d..c41cbff697 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -63,6 +63,9 @@ For Cortex-A57, following errata build flags are defined : * `ERRATA_A57_826974`: This applies errata 826974 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. +* `ERRATA_A57_826977`: This applies errata 826977 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p1 of the CPU. + * `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 95c1f56c17..685b87b2e3 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -62,6 +62,7 @@ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ #define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) +#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54) #define CPUACTLR_DIS_OVERREAD (1 << 52) #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 25def1cdda..63cb757929 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -193,6 +193,32 @@ apply_826974: ret endfunc errata_a57_826974_wa + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #826977. + * This applies only to revision <= r1p1 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_826977_wa + /* + * Compare x0 against revision r1p1 + */ + cmp x0, #0x11 + b.ls apply_826977 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_826977: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_826977_wa + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #828024. * This applies only to revision <= r1p1 of Cortex A57. @@ -289,6 +315,11 @@ func cortex_a57_reset_func bl errata_a57_826974_wa #endif +#if ERRATA_A57_826977 + mov x0, x15 + bl errata_a57_826977_wa +#endif + #if ERRATA_A57_828024 mov x0, x15 bl errata_a57_828024_wa diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 62de70f514..aa808b61b7 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -78,6 +78,10 @@ ERRATA_A57_813420 ?=0 # only to revision <= r1p1 of the Cortex A57 cpu. ERRATA_A57_826974 ?=0 +# Flag to apply erratum 826977 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A57 cpu. +ERRATA_A57_826977 ?=0 + # Flag to apply erratum 828024 workaround during reset. This erratum applies # only to revision <= r1p1 of the Cortex A57 cpu. ERRATA_A57_828024 ?=0 @@ -106,6 +110,10 @@ $(eval $(call add_define,ERRATA_A57_813420)) $(eval $(call assert_boolean,ERRATA_A57_826974)) $(eval $(call add_define,ERRATA_A57_826974)) +# Process ERRATA_A57_826977 flag +$(eval $(call assert_boolean,ERRATA_A57_826977)) +$(eval $(call add_define,ERRATA_A57_826977)) + # Process ERRATA_A57_828024 flag $(eval $(call assert_boolean,ERRATA_A57_828024)) $(eval $(call add_define,ERRATA_A57_828024)) From adeecf9219fd542379e704ce190701f6a78eb42a Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Thu, 21 Apr 2016 11:10:52 +0100 Subject: [PATCH 6/7] Add support for Cortex-A57 erratum 833471 workaround Change-Id: I86ac81ffd7cd094ce68c4cceb01c16563671a063 --- docs/cpu-specific-build-macros.md | 3 +++ include/lib/cpus/aarch64/cortex_a57.h | 1 + lib/cpus/aarch64/cortex_a57.S | 31 +++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++++ 4 files changed, 43 insertions(+) diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index c41cbff697..202cea7045 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -72,6 +72,9 @@ For Cortex-A57, following errata build flags are defined : * `ERRATA_A57_829520`: This applies errata 829520 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. +* `ERRATA_A57_833471`: This applies errata 833471 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p2 of the CPU. + 3. CPU Specific optimizations ------------------------------ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 685b87b2e3..ac4ae57017 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -66,6 +66,7 @@ #define CPUACTLR_DIS_OVERREAD (1 << 52) #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38) #define CPUACTLR_DIS_STREAMING (3 << 27) #define CPUACTLR_DIS_L1_STREAMING (3 << 25) #define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 63cb757929..60929a0506 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -277,6 +277,32 @@ apply_829520: ret endfunc errata_a57_829520_wa + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #833471. + * This applies only to revision <= r1p2 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_833471_wa + /* + * Compare x0 against revision r1p2 + */ + cmp x0, #0x12 + b.ls apply_833471 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_833471: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_833471_wa + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Clobbers: x0-x5, x15, x19, x30 @@ -330,6 +356,11 @@ func cortex_a57_reset_func bl errata_a57_829520_wa #endif +#if ERRATA_A57_833471 + mov x0, x15 + bl errata_a57_833471_wa +#endif + /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index aa808b61b7..0659bff9c6 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -90,6 +90,10 @@ ERRATA_A57_828024 ?=0 # only to revision <= r1p2 of the Cortex A57 cpu. ERRATA_A57_829520 ?=0 +# Flag to apply erratum 833471 workaround during reset. This erratum applies +# only to revision <= r1p2 of the Cortex A57 cpu. +ERRATA_A57_833471 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -121,3 +125,7 @@ $(eval $(call add_define,ERRATA_A57_828024)) # Process ERRATA_A57_829520 flag $(eval $(call assert_boolean,ERRATA_A57_829520)) $(eval $(call add_define,ERRATA_A57_829520)) + +# Process ERRATA_A57_833471 flag +$(eval $(call assert_boolean,ERRATA_A57_833471)) +$(eval $(call add_define,ERRATA_A57_833471)) From 86d8948c781404ec7091538588c1403664603649 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Thu, 21 Apr 2016 11:30:41 +0100 Subject: [PATCH 7/7] Doc: Add links to the A53/A57 Errata Notice documents This patch adds links to the Cortex-A53 and Cortex-A57 MPCores Software Developers Errata Notice documents in the ARM CPU Specific Build Macros document. Change-Id: I0aa26d7f373026097ed012a02bc61ee2c5b9d6fc --- docs/cpu-specific-build-macros.md | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index 202cea7045..df2fbd86d0 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -22,14 +22,19 @@ for a specific CPU on a platform. ARM Trusted Firmware exports a series of build flags which control the errata workarounds that are applied to each CPU by the reset handler. The errata details can be found in the CPU specific errata documents published -by ARM. The errata workarounds are implemented for a particular revision -or a set of processor revisions. This is checked by reset handler at runtime. -Each errata workaround is identified by its `ID` as specified in the processor's +by ARM: + +* [Cortex-A53 MPCore Software Developers Errata Notice][A53 Errata Notice] +* [Cortex-A57 MPCore Software Developers Errata Notice][A57 Errata Notice] + +The errata workarounds are implemented for a particular revision or a set of +processor revisions. This is checked by the reset handler at runtime. Each +errata workaround is identified by its `ID` as specified in the processor's errata notice document. The format of the define used to enable/disable the errata workaround is `ERRATA__`, where the `Processor name` is for example `A57` for the `Cortex_A57` CPU. -All workarounds are disabled by default. The platform is reponsible for +All workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the errata workaround build flags in the platform specific makefile. In case these workarounds are enabled for the wrong CPU revision then the errata @@ -109,3 +114,5 @@ architecture that can be enabled by the platform as desired. _Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved._ [A57 SW Optimization Guide]: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf +[A53 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html +[A57 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf