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Braswell: Added SOC G3 / Pseudo G3 support

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BUG=none
TEST=Tested on DVT 1.1, verified V3p3A is off in Pseudo G3
BRANCH=none

Change-Id: Id73b42d9f2e49239e82fad7931bbcc63e36a2c0b
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283602
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Commit-Queue: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
This commit is contained in:
Kevin K Wong
2015-06-11 14:12:50 -07:00
committed by ChromeOS Commit Bot
parent 2d01549b2b
commit 776ea6b118
4 changed files with 49 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/config.h
View File

@@ -1101,6 +1101,12 @@
#undef CONFIG_LOW_POWER_IDLE
#undef CONFIG_LOW_POWER_USE_LFIOSC
/*
* Enable Pseudo G3 (power removed from EC)
* This requires board specific implementation.
*/
#undef CONFIG_LOW_POWER_PSEUDO_G3
/*
* Enable deep sleep during S0 (ignores SLEEP_MASK_AP_RUN).
*/

4
include/power.h
View File

@@ -117,4 +117,8 @@ inline int power_get_pause_in_s5(void);
*/
inline void power_set_pause_in_s5(int pause);
#ifdef CONFIG_LOW_POWER_PSEUDO_G3
void enter_pseudo_g3(void);
#endif
#endif /* __CROS_EC_POWER_H */