diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c index bce2138ca2..50fa9dbce0 100644 --- a/chip/lm4/gpio.c +++ b/chip/lm4/gpio.c @@ -58,7 +58,7 @@ void gpio_set_alternate_function(int port, int mask, int func) clock_wait_cycles(3); } - if (func) { + if (func >= 0) { int pctlmask = 0; int i; /* Expand mask from bits to nibbles */ @@ -196,7 +196,7 @@ void gpio_pre_init(void) /* Set all GPIOs to defaults */ for (i = 0; i < GPIO_COUNT; i++, g++) { /* Use as GPIO, not alternate function */ - gpio_set_alternate_function(g->port, g->mask, 0); + gpio_set_alternate_function(g->port, g->mask, -1); /* Set up GPIO based on flags */ gpio_set_flags(i, g->flags); diff --git a/chip/lm4/onewire.c b/chip/lm4/onewire.c index 0c795eeedc..d6677bfa55 100644 --- a/chip/lm4/onewire.c +++ b/chip/lm4/onewire.c @@ -158,7 +158,7 @@ void onewire_write(int data) static void onewire_init(void) { /* Configure 1-wire pin as open-drain GPIO */ - gpio_set_alternate_function(LM4_GPIO_H, ONEWIRE_PIN, 0); + gpio_set_alternate_function(LM4_GPIO_H, ONEWIRE_PIN, -1); LM4_GPIO_ODR(LM4_GPIO_H) |= ONEWIRE_PIN; } DECLARE_HOOK(HOOK_INIT, onewire_init, HOOK_PRIO_DEFAULT); diff --git a/chip/lm4/spi.c b/chip/lm4/spi.c index 09a5ec03a8..4607f7460c 100644 --- a/chip/lm4/spi.c +++ b/chip/lm4/spi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -41,7 +41,7 @@ int spi_enable(int enable) gpio_set_flags(GPIO_SPI_CSn, GPIO_HI_Z); /* PA2,4,5 normal function (high-Z GPIOs) */ - gpio_set_alternate_function(LM4_GPIO_A, 0x34, 0); + gpio_set_alternate_function(LM4_GPIO_A, 0x34, -1); } return EC_SUCCESS; diff --git a/chip/stm32/gpio-stm32l15x.c b/chip/stm32/gpio-stm32l15x.c index 72c118cbf5..dbd7af174c 100644 --- a/chip/stm32/gpio-stm32l15x.c +++ b/chip/stm32/gpio-stm32l15x.c @@ -118,6 +118,17 @@ void gpio_set_alternate_function(int port, int mask, int func) uint32_t afr; uint32_t moder = STM32_GPIO_MODER_OFF(port); + if (func < 0) { + /* Return to normal GPIO function, defaulting to input. */ + while (mask) { + bit = 31 - __builtin_clz(mask); + moder &= ~(0x3 << (bit * 2 + 16)); + mask &= ~(1 << bit); + } + STM32_GPIO_MODER_OFF(port) = moder; + return; + } + /* Low half of the GPIO bank */ half = mask & 0xff; afr = STM32_GPIO_AFRL_OFF(port); diff --git a/include/gpio.h b/include/gpio.h index 9dd97cb3aa..fca33231e0 100644 --- a/include/gpio.h +++ b/include/gpio.h @@ -133,7 +133,7 @@ int gpio_enable_interrupt(enum gpio_signal signal); * * @param port GPIO port to set (LM4_GPIO_*) * @param mask Bitmask of pins on that port to affect - * @param func Alternate function; if 0, configures the specified + * @param func Alternate function; if <0, configures the specified * GPIOs for normal GPIO operation. */ void gpio_set_alternate_function(int port, int mask, int func);