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Merge pull request #584 from soby-mathew/sm/enable_scr_sif

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Enable SCR_EL3.SIF bit
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danh-arm
2016-04-07 17:17:25 +01:00
parent 0892f6b605 99e58f9e69
commit 7a0ae2f457
2 changed files with 7 additions and 4 deletions
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docs/firmware-design.md
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@@ -176,7 +176,9 @@ BL1 performs minimal architectural initialization as follows.
- `SCR_EL3`. The register width of the next lower exception level is set
to AArch64 by setting the `SCR.RW` bit. The `SCR.EA` bit is set to trap
both External Aborts and SError Interrupts in EL3.
both External Aborts and SError Interrupts in EL3. The `SCR.SIF` bit is
also set to disable instruction fetches from Non-secure memory when in
secure state.
- `CPTR_EL3`. Accesses to the `CPACR_EL1` register from EL1 or EL2, or the
`CPTR_EL2` register from EL2 are configured to not trap to EL3 by