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pd: refactor tcpm and move alert function to tcpm driver
Refactor the tcpm/tcpc split such that the tcpm driver implements the alert functionality since it may be unique for different tcpc chips. BUG=chrome-os-partner:41842 BRANCH=none TEST=make -j buildall. run on samus and glados. Change-Id: I23f2d7f8627d5337b8d001a09bf27622be24fe33 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/281631 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Alec Berg
committed by
ChromeOS Commit Bot
ChromeOS Commit Bot
parent
59576398db
commit
82ec2510a3
@@ -5,14 +5,14 @@
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/* TCPM for MCU also running TCPC */
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#include "task.h"
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#include "tcpci.h"
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#include "usb_pd.h"
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#include "usb_pd_tcpm.h"
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#include "console.h"
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extern int tcpc_alert_status(int port, uint16_t *alert);
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extern int tcpc_alert_status(int port, int *alert);
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extern int tcpc_alert_status_clear(int port, uint16_t mask);
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extern int tcpc_alert_mask_update(int port, uint16_t mask);
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extern int tcpc_alert_mask_set(int port, uint16_t mask);
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extern int tcpc_get_cc(int port, int *cc1, int *cc2);
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extern int tcpc_set_cc(int port, int pull);
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extern int tcpc_set_polarity(int port, int polarity);
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@@ -24,10 +24,28 @@ extern int tcpc_get_message(int port, uint32_t *payload, int *head);
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extern int tcpc_transmit(int port, enum tcpm_transmit_type type,
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uint16_t header, const uint32_t *data);
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static int init_alert_mask(int port)
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{
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uint16_t mask;
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int rv;
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/*
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* Create mask of alert events that will cause the TCPC to
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* signal the TCPM via the Alert# gpio line.
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*/
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mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
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TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
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TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS;
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/* Set the alert mask in TCPC */
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rv = tcpm_alert_mask_set(port, mask);
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return rv;
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}
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int tcpm_init(int port)
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{
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tcpc_init(port);
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return EC_SUCCESS;
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return init_alert_mask(port);
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}
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int tcpm_get_cc(int port, int *cc1, int *cc2)
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@@ -55,7 +73,7 @@ int tcpm_set_msg_header(int port, int power_role, int data_role)
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return tcpc_set_msg_header(port, power_role, data_role);
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}
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int tcpm_alert_status(int port, int alert_reg, uint16_t *alert)
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int tcpm_alert_status(int port, int *alert)
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{
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int rv;
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@@ -71,9 +89,9 @@ int tcpm_set_rx_enable(int port, int enable)
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return tcpc_set_rx_enable(port, enable);
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}
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int tcpm_alert_mask_set(int port, int reg, uint16_t mask)
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int tcpm_alert_mask_set(int port, uint16_t mask)
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{
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return tcpc_alert_mask_update(port, mask);
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return tcpc_alert_mask_set(port, mask);
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}
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int tcpm_get_message(int port, uint32_t *payload, int *head)
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@@ -86,3 +104,33 @@ int tcpm_transmit(int port, enum tcpm_transmit_type type, uint16_t header,
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{
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return tcpc_transmit(port, type, header, data);
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}
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void tcpc_alert(int port)
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{
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int status;
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/* Read the Alert register from the TCPC */
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tcpm_alert_status(port, &status);
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if (status & TCPC_REG_ALERT_CC_STATUS) {
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/* CC status changed, wake task */
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task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
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}
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if (status & TCPC_REG_ALERT_RX_STATUS) {
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/*
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* message received. since TCPC is compiled in, we
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* already received PD_EVENT_RX from phy layer in
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* pd_rx_event(), so we don't need to set another
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* event.
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*/
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}
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if (status & TCPC_REG_ALERT_RX_HARD_RST) {
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/* hard reset received */
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pd_execute_hard_reset(port);
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task_wake(PD_PORT_TO_TASK_ID(port));
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}
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if (status & TCPC_REG_ALERT_TX_COMPLETE) {
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/* transmit complete */
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pd_transmit_complete(port, status & TCPC_REG_ALERT_TX_COMPLETE);
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}
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}
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@@ -6,20 +6,37 @@
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/* Type-C port manager */
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#include "i2c.h"
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#include "task.h"
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#include "tcpci.h"
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#include "timer.h"
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#include "usb_pd.h"
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#include "usb_pd_tcpc.h"
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#include "usb_pd_tcpm.h"
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#include "util.h"
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#include "console.h"
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/* Convert port number to tcpc i2c address */
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#define I2C_ADDR_TCPC(p) (CONFIG_TCPC_I2C_BASE_ADDR + 2*(p))
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static int tcpc_polarity, tcpc_vconn;
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static int init_alert_mask(int port)
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{
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uint16_t mask;
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int rv;
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/*
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* Create mask of alert events that will cause the TCPC to
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* signal the TCPM via the Alert# gpio line.
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*/
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mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
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TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
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TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS;
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/* Set the alert mask in TCPC */
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rv = tcpm_alert_mask_set(port, mask);
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return rv;
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}
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int tcpm_init(int port)
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{
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int rv, vid = 0;
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@@ -32,7 +49,7 @@ int tcpm_init(int port)
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* is complete
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*/
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if (rv == EC_SUCCESS && vid)
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return rv;
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return init_alert_mask(port);
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msleep(10);
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}
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}
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@@ -92,19 +109,19 @@ int tcpm_set_msg_header(int port, int power_role, int data_role)
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TCPC_REG_MSG_HDR_INFO_SET(data_role, power_role));
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}
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int tcpm_alert_status(int port, int alert_reg, uint16_t *alert)
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int tcpm_alert_status(int port, int *alert)
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{
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int rv;
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/* Read TCPC Alert register */
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rv = i2c_read16(I2C_PORT_TCPC, I2C_ADDR_TCPC(port),
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alert_reg, (int *)alert);
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TCPC_REG_ALERT, alert);
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/*
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* The PD protocol layer will process all alert bits
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* returned by this function. Therefore, these bits
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* can now be cleared from the TCPC register.
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*/
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i2c_write16(I2C_PORT_TCPC, I2C_ADDR_TCPC(port),
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alert_reg, *alert);
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TCPC_REG_ALERT, *alert);
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return rv;
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}
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@@ -116,12 +133,12 @@ int tcpm_set_rx_enable(int port, int enable)
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enable ? TCPC_REG_RX_DETECT_SOP_HRST_MASK : 0);
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}
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int tcpm_alert_mask_set(int port, int reg, uint16_t mask)
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int tcpm_alert_mask_set(int port, uint16_t mask)
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{
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int rv;
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/* write to the Alert Mask register */
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rv = i2c_write16(I2C_PORT_TCPC, I2C_ADDR_TCPC(port),
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reg, mask);
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TCPC_REG_ALERT_MASK, mask);
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if (rv)
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return rv;
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@@ -192,3 +209,29 @@ int tcpm_transmit(int port, enum tcpm_transmit_type type, uint16_t header,
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return rv;
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}
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void tcpc_alert(int port)
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{
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int status;
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/* Read the Alert register from the TCPC */
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tcpm_alert_status(port, &status);
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if (status & TCPC_REG_ALERT_CC_STATUS) {
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/* CC status changed, wake task */
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task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC, 0);
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}
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if (status & TCPC_REG_ALERT_RX_STATUS) {
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/* message received */
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task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_RX, 0);
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}
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if (status & TCPC_REG_ALERT_RX_HARD_RST) {
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/* hard reset received */
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pd_execute_hard_reset(port);
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task_wake(PD_PORT_TO_TASK_ID(port));
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}
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if (status & TCPC_REG_ALERT_TX_COMPLETE) {
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/* transmit complete */
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pd_transmit_complete(port, status & TCPC_REG_ALERT_TX_COMPLETE);
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}
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}
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85
driver/tcpm/tcpci.h
Normal file
85
driver/tcpm/tcpci.h
Normal file
@@ -0,0 +1,85 @@
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* USB Power delivery port management */
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#ifndef __CROS_EC_USB_PD_TCPM_TCPCI_H
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#define __CROS_EC_USB_PD_TCPM_TCPCI_H
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#define TCPC_REG_VENDOR_ID 0x0
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#define TCPC_REG_PRODUCT_ID 0x2
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#define TCPC_REG_BCD_DEV 0x4
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#define TCPC_REG_TC_REV 0x6
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#define TCPC_REG_PD_REV 0x8
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#define TCPC_REG_PD_INT_REV 0xa
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#define TCPC_REG_DEV_CAP_1 0xc
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#define TCPC_REG_DEV_CAP_2 0xd
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#define TCPC_REG_DEV_CAP_3 0xe
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#define TCPC_REG_DEV_CAP_4 0xf
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#define TCPC_REG_ALERT 0x10
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#define TCPC_REG_ALERT_GPIO_CHANGE (1<<10)
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#define TCPC_REG_ALERT_V_ALARM_LO (1<<9)
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#define TCPC_REG_ALERT_V_ALARM_HI (1<<8)
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#define TCPC_REG_ALERT_SLEEP_EXITED (1<<7)
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#define TCPC_REG_ALERT_POWER_STATUS (1<<6)
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#define TCPC_REG_ALERT_CC_STATUS (1<<5)
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#define TCPC_REG_ALERT_RX_STATUS (1<<4)
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#define TCPC_REG_ALERT_RX_HARD_RST (1<<3)
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#define TCPC_REG_ALERT_TX_SUCCESS (1<<2)
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#define TCPC_REG_ALERT_TX_DISCARDED (1<<1)
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#define TCPC_REG_ALERT_TX_FAILED (1<<0)
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#define TCPC_REG_ALERT_TX_COMPLETE (TCPC_REG_ALERT_TX_SUCCESS | \
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TCPC_REG_ALERT_TX_DISCARDED | \
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TCPC_REG_ALERT_TX_FAILED)
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#define TCPC_REG_ALERT_MASK 0x12
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#define TCPC_REG_POWER_STATUS_MASK 0x14
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#define TCPC_REG_CC1_STATUS 0x16
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#define TCPC_REG_CC2_STATUS 0x17
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#define TCPC_REG_CC_STATUS_SET(term, volt) \
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((term) << 3 | volt)
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#define TCPC_REG_CC_STATUS_TERM(reg) (((reg) & 0x38) >> 3)
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#define TCPC_REG_CC_STATUS_VOLT(reg) ((reg) & 0x7)
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#define TCPC_REG_POWER_STATUS 0x1a
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#define TCPC_REG_ROLE_CTRL 0x1b
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#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc2, cc1) \
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((drp) << 6 | (rp) << 4 | (cc2) << 2 | (cc1))
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#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg) & 0xc) >> 2)
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#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg) & 0x3)
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#define TCPC_REG_POWER_PATH_CTRL 0x1c
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#define TCPC_REG_POWER_CTRL 0x1d
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#define TCPC_REG_POWER_CTRL_SET(polarity, vconn) \
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((polarity) << 4 | (vconn))
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#define TCPC_REG_POWER_CTRL_POLARITY(reg) (((reg) & 0x10) >> 4)
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#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg) & 0x1)
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#define TCPC_REG_COMMAND 0x23
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#define TCPC_REG_MSG_HDR_INFO 0x2e
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#define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \
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((drole) << 3 | (PD_REV20 << 1) | (prole))
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#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3)
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#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1)
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#define TCPC_REG_RX_BYTE_CNT 0x2f
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#define TCPC_REG_RX_STATUS 0x30
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#define TCPC_REG_RX_DETECT 0x31
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#define TCPC_REG_RX_DETECT_SOP_HRST_MASK 0x21
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#define TCPC_REG_RX_HDR 0x32
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#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */
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#define TCPC_REG_TRANSMIT 0x50
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#define TCPC_REG_TRANSMIT_SET(type) \
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(PD_RETRY_COUNT << 4 | (type))
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#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4)
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#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg) & 0x7)
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#define TCPC_REG_TX_BYTE_CNT 0x51
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#define TCPC_REG_TX_HDR 0x52
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#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */
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#endif /* __CROS_EC_USB_PD_TCPM_TCPCI_H */
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