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https://github.com/Telecominfraproject/OpenCellular.git
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pd: refactor tcpm and move alert function to tcpm driver
Refactor the tcpm/tcpc split such that the tcpm driver implements the alert functionality since it may be unique for different tcpc chips. BUG=chrome-os-partner:41842 BRANCH=none TEST=make -j buildall. run on samus and glados. Change-Id: I23f2d7f8627d5337b8d001a09bf27622be24fe33 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/281631 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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ChromeOS Commit Bot
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82ec2510a3
@@ -1478,6 +1478,21 @@ int pd_analyze_rx(int port, uint32_t *payload);
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*/
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int pd_is_connected(int port);
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/**
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* Execute a hard reset
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*
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* @param port USB-C port number
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*/
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void pd_execute_hard_reset(int port);
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/**
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* Signal to protocol layer that PD transmit is complete
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*
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* @param port USB-C port number
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* @param status status of the transmission
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*/
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void pd_transmit_complete(int port, int status);
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/**
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* Get port polarity.
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*
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@@ -14,40 +14,6 @@
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/* Time to wait for TCPC to complete transmit */
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#define PD_T_TCPC_TX_TIMEOUT (100*MSEC)
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#define TCPC_REG_VENDOR_ID 0x0
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#define TCPC_REG_PRODUCT_ID 0x2
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#define TCPC_REG_BCD_DEV 0x4
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#define TCPC_REG_TC_REV 0x6
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#define TCPC_REG_PD_REV 0x8
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#define TCPC_REG_PD_INT_REV 0xa
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#define TCPC_REG_DEV_CAP_1 0xc
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#define TCPC_REG_DEV_CAP_2 0xd
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#define TCPC_REG_DEV_CAP_3 0xe
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#define TCPC_REG_DEV_CAP_4 0xf
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#define TCPC_REG_ALERT 0x10
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#define TCPC_REG_ALERT_GPIO_CHANGE (1<<10)
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#define TCPC_REG_ALERT_V_ALARM_LO (1<<9)
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#define TCPC_REG_ALERT_V_ALARM_HI (1<<8)
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#define TCPC_REG_ALERT_SLEEP_EXITED (1<<7)
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#define TCPC_REG_ALERT_POWER_STATUS (1<<6)
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#define TCPC_REG_ALERT_CC_STATUS (1<<5)
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#define TCPC_REG_ALERT_RX_STATUS (1<<4)
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#define TCPC_REG_ALERT_RX_HARD_RST (1<<3)
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#define TCPC_REG_ALERT_TX_SUCCESS (1<<2)
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#define TCPC_REG_ALERT_TX_DISCARDED (1<<1)
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#define TCPC_REG_ALERT_TX_FAILED (1<<0)
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#define TCPC_REG_ALERT_TX_COMPLETE (TCPC_REG_ALERT_TX_SUCCESS | \
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TCPC_REG_ALERT_TX_DISCARDED | \
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TCPC_REG_ALERT_TX_FAILED)
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#define TCPC_REG_ALERT_MASK 0x12
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#define TCPC_REG_POWER_STATUS_MASK 0x14
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#define TCPC_REG_CC1_STATUS 0x16
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#define TCPC_REG_CC2_STATUS 0x17
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#define TCPC_REG_CC_STATUS_SET(term, volt) \
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((term) << 3 | volt)
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#define TCPC_REG_CC_STATUS_TERM(reg) (((reg) & 0x38) >> 3)
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#define TCPC_REG_CC_STATUS_VOLT(reg) ((reg) & 0x7)
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enum tcpc_cc_termination_status {
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TYPEC_CC_TERM_RA = 0,
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TYPEC_CC_TERM_RP_DEF = 1,
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@@ -67,16 +33,11 @@ enum tcpc_cc_voltage_status {
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TYPEC_CC_VOLT_SRC_3_0 = 6,
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TYPEC_CC_VOLT_OPEN = 7
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};
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/* Check if CC voltage is within Rd */
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#define TYPEC_CC_IS_RD(cc) ((cc) >= TYPEC_CC_VOLT_SNK_DEF && \
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(cc) <= TYPEC_CC_VOLT_SNK_3_0)
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#define TCPC_REG_POWER_STATUS 0x1a
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#define TCPC_REG_ROLE_CTRL 0x1b
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#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc2, cc1) \
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((drp) << 6 | (rp) << 4 | (cc2) << 2 | (cc1))
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#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg) & 0xc) >> 2)
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#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg) & 0x3)
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enum tcpc_cc_pull {
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TYPEC_CC_RA = 0,
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TYPEC_CC_RP = 1,
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@@ -84,53 +45,32 @@ enum tcpc_cc_pull {
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TYPEC_CC_OPEN = 3,
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};
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#define TCPC_REG_POWER_PATH_CTRL 0x1c
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#define TCPC_REG_POWER_CTRL 0x1d
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#define TCPC_REG_POWER_CTRL_SET(polarity, vconn) \
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((polarity) << 4 | (vconn))
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#define TCPC_REG_POWER_CTRL_POLARITY(reg) (((reg) & 0x10) >> 4)
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#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg) & 0x1)
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#define TCPC_REG_COMMAND 0x23
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#define TCPC_REG_MSG_HDR_INFO 0x2e
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#define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \
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((drole) << 3 | (PD_REV20 << 1) | (prole))
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#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3)
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#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1)
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#define TCPC_REG_RX_BYTE_CNT 0x2f
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#define TCPC_REG_RX_STATUS 0x30
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#define TCPC_REG_RX_DETECT 0x31
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#define TCPC_REG_RX_DETECT_SOP_HRST_MASK 0x21
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#define TCPC_REG_RX_HDR 0x32
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#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */
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#define TCPC_REG_TRANSMIT 0x50
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#define TCPC_REG_TRANSMIT_SET(type) \
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(PD_RETRY_COUNT << 4 | (type))
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#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4)
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#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg) & 0x7)
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enum tcpm_transmit_type {
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TRANSMIT_SOP = 0,
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TRANSMIT_SOP_PRIME = 1,
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TRANSMIT_SOP_PRIME_PRIME = 2,
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TRANSMIT_SOP_DEBUG_PRIME = 3,
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TRANSMIT_SOP_DEBUG_PRIME_PRIME = 4,
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TRANSMIT_HARD_RESET = 5,
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TRANSMIT_CABLE_RESET = 6,
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TRANSMIT_BIST_MODE_2 = 7
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TCPC_TX_SOP = 0,
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TCPC_TX_SOP_PRIME = 1,
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TCPC_TX_SOP_PRIME_PRIME = 2,
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TCPC_TX_SOP_DEBUG_PRIME = 3,
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TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4,
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TCPC_TX_HARD_RESET = 5,
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TCPC_TX_CABLE_RESET = 6,
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TCPC_TX_BIST_MODE_2 = 7
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};
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#define TCPC_REG_TX_BYTE_CNT 0x51
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#define TCPC_REG_TX_HDR 0x52
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#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */
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enum tcpc_transmit_complete {
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TCPC_TX_COMPLETE_SUCCESS = (1 << 2),
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TCPC_TX_COMPLETE_DISCARDED = (1 << 1),
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TCPC_TX_COMPLETE_FAILED = (1 << 0),
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};
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/**
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* TCPC is asserting alert
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* Initialize TCPM driver and wait for TCPC readiness.
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*
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* @param port Type-C port number
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*
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* @return EC_SUCCESS or error
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*/
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void tcpc_alert(int port);
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void tcpc_alert_clear(int port);
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int tcpm_init(int port);
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/**
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* Initialize TCPC.
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*
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@@ -138,6 +78,14 @@ void tcpc_alert_clear(int port);
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*/
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void tcpc_init(int port);
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/**
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* TCPC is asserting alert
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*
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* @param port Type-C port number
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*/
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void tcpc_alert(int port);
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void tcpc_alert_clear(int port);
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/**
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* Run TCPC task once. This checks for incoming messages, processes
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* any outgoing messages, and reads CC lines.
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@@ -147,36 +95,26 @@ void tcpc_init(int port);
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*/
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int tcpc_run(int port, int evt);
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/**
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* Read TCPC alert status
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*
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* @param port Type-C port number
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* @param reg TCPC register address
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* @param alert Pointer to location to store alert status
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* @return EC_SUCCESS or error
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*/
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int tcpm_alert_status(int port, int reg, uint16_t *alert);
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int tcpm_alert_status(int port, int *alert);
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/**
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* Write TCPC Alert Mask register
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*
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* @param port Type-C port number
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* @param reg TCPC register address
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* @param mask bits to be set in Alert Mask register
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* @return EC_SUCCESS or error
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*/
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int tcpm_alert_mask_set(int port, int reg, uint16_t mask);
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/**
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* Initialize TCPM driver and wait for TCPC readiness.
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*
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* @param port Type-C port number
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*
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* @return EC_SUCCESS or error
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*/
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int tcpm_init(int port);
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int tcpm_alert_mask_set(int port, uint16_t mask);
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/**
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* Read the CC line status.
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