diff --git a/firmware/coreboot/util/nvidia/cbootimage b/firmware/coreboot/util/nvidia/cbootimage deleted file mode 160000 index 64045f993c..0000000000 --- a/firmware/coreboot/util/nvidia/cbootimage +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 64045f993c2cd8989838aeaad3d22107d96d5596 diff --git a/firmware/coreboot/util/nvidia/cbootimage/.dir-locals.el b/firmware/coreboot/util/nvidia/cbootimage/.dir-locals.el new file mode 100644 index 0000000000..31a7ea718a --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/.dir-locals.el @@ -0,0 +1,10 @@ +;;; This file is used by Emacs to configure it's code editing modes to correctly +;;; indent cbootimage style source code. + +((nil . ((indent-tabs-mode . t) + (tab-width . 8) + (fill-column . 80))) + + (c-mode . ((c-basic-offset . 8))) + + (c++-mode . ((c-basic-offset . 8)))) diff --git a/firmware/coreboot/util/nvidia/cbootimage/.gitignore b/firmware/coreboot/util/nvidia/cbootimage/.gitignore new file mode 100644 index 0000000000..91c964c696 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/.gitignore @@ -0,0 +1,27 @@ +bct_dump +cbootimage +.*.swp +*.o +*~ + +.deps +.dirstamp +Makefile +Makefile.in +/aclocal.m4 +/autom4te.cache/ +/compile +/config.h +/config.h.in +/config.log +/config.status +/configure +/depcomp +/install-sh +/missing +/stamp-h1 + +src/bct_dump.1 +src/bct_dump.man +src/cbootimage.1 +src/cbootimage.man diff --git a/firmware/coreboot/util/nvidia/cbootimage/COPYING b/firmware/coreboot/util/nvidia/cbootimage/COPYING new file mode 100644 index 0000000000..d159169d10 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/firmware/coreboot/util/nvidia/cbootimage/CREDITS b/firmware/coreboot/util/nvidia/cbootimage/CREDITS new file mode 100644 index 0000000000..0e5c0d0b4c --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/CREDITS @@ -0,0 +1,5 @@ +# Names should be added to this file like so: +# Name or Organization + +Google Inc. +NVIDIA CORPORATION diff --git a/firmware/coreboot/util/nvidia/cbootimage/Makefile.am b/firmware/coreboot/util/nvidia/cbootimage/Makefile.am new file mode 100644 index 0000000000..d35ae37827 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/Makefile.am @@ -0,0 +1,5 @@ +AUTOMAKE_OPTIONS = foreign +SUBDIRS = src + +distclean-local: + rm -rf autom4te.cache diff --git a/firmware/coreboot/util/nvidia/cbootimage/README.txt b/firmware/coreboot/util/nvidia/cbootimage/README.txt new file mode 100644 index 0000000000..ce95b5a35e --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/README.txt @@ -0,0 +1,34 @@ +Introduction +============ + +This project provides a tool which compiles BCT (Boot Configuration Table) +images to place into the boot flash of a Tegra-based device. + +The tool will either: + +a) Compile a textual representation of a BCT into a binary image. + +b) Generate an entire boot image from a previously compiled BCT and a + bootloader binary. + +Submitting Changes +================== + +To submit patches to this project, please use the following commands: + +* git format-patch --subject-prefix="cbootimage PATCH" + + Creates a patch file from your git commit. + +* git send-email --to linux-tegra@vger.kernel.org *.patch + + Sends the patch by email to the Tegra mailing list. + +Even though the primary upstream repository for this project is hosted on +github, contributions aren't accepted via github pull requests. Github pull +requests would bypass public code review on the project mailing list. + +Patches should be signed off (include a signed-off-by line) to indicate your +acceptance of the code's license (see COPYING and the license header in each +file). See http://developercertificate.org/ for details of what signed-off-by +implies. diff --git a/firmware/coreboot/util/nvidia/cbootimage/autogen.sh b/firmware/coreboot/util/nvidia/cbootimage/autogen.sh new file mode 100755 index 0000000000..530783bcae --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/autogen.sh @@ -0,0 +1,4 @@ +#!/bin/sh -e + +autoreconf --install --symlink +./configure "$@" diff --git a/firmware/coreboot/util/nvidia/cbootimage/configure.ac b/firmware/coreboot/util/nvidia/cbootimage/configure.ac new file mode 100644 index 0000000000..c8218ba5b5 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/configure.ac @@ -0,0 +1,38 @@ +# -*- Autoconf -*- +# Process this file with autoconf to produce a configure script. + +AC_PREREQ([2.67]) +AC_INIT([cbootimage], [1.7], [jimmzhang@nvidia.com]) +AM_INIT_AUTOMAKE +AC_CONFIG_SRCDIR([src/cbootimage.c]) +AC_CONFIG_HEADERS([config.h]) + +# Checks for programs. +AC_PROG_CC +AM_PROG_CC_C_O +PKG_PROG_PKG_CONFIG + +# Checks for libraries. +AC_CHECK_LIB(m, log2) + +# Checks for header files. +AC_CHECK_HEADERS([stdio.h string.h ctype.h sys/stat.h getopt.h stdlib.h assert.h errno.h sys/types.h math.h]) + +# Checks for typedefs, structures, and compiler characteristics. +AC_TYPE_SSIZE_T +AC_HEADER_STDBOOL +AC_TYPE_UINT16_T +AC_TYPE_UINT32_T +AC_TYPE_UINT64_T +AC_TYPE_UINT8_T + +# Checks for library functions. +AC_FUNC_ERROR_AT_LINE +AC_FUNC_MALLOC +AC_CHECK_FUNCS([memset]) + +AC_CONFIG_FILES([ + Makefile + src/Makefile +]) +AC_OUTPUT diff --git a/firmware/coreboot/util/nvidia/cbootimage/samples/rsa_priv.pem b/firmware/coreboot/util/nvidia/cbootimage/samples/rsa_priv.pem new file mode 100644 index 0000000000..a02d77fc43 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/samples/rsa_priv.pem @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEpQIBAAKCAQEA2L0jolLgp2pKAzn/JeZuxgGPY1Yz4ZNkttzvBlVhozEynj2x +Lttz1gZ6fYUb/ObM8v2PoeOlrwkGoWMscuMS4MnLG2NcJlWmlsLTyfw3EwxblM3D +DniscakhMexNK3J7uxmmRkQTfldec4JHjsAN6d9cZQ0POdsA7j5lKNG0KgCohKk6 +p+lMYXFqgxx3IQWcynhuKVtVFm/UJJBC+a4ibbXcpnio96ySVrPO/ZpEOhEpPTWX +VLeiqBB3dsu//9X0vDfShyBlctaonx2Z7xWQWotubze0iIvyU6U+T69aDOXfHQfu +kNMX3Dj4VCndW/FUrrg5k/y9dMA1We3Ng1A0NQIDAQABAoIBABcWRqZy15VdwBaJ +5gDeg+w5nFGDjDE6Jx9Hd3qgO69LfU3X2njYTYV92SxnsmyFFU3I7rTa7/ouJvOo +AcMXJxqkxCrdsaIvu3gRtsesQx2XUmYOaPmwpwXQc0XDGxFGt6FdgRW5CK6LlfcN +6JtvH8xKy6fD9Vw/VOEL6nCnrd5PU3UNU/Ng7h/SZ+5NEALJE7+gaMvmK9o9lX3a +/tze6bwKKF+a2luTs2aVGxjUYBud6YOE2KPG7zltuHUHUeEgJ/X/sgWYiHsqpK3l +rIrjCVIQnrRCCtCHg5BbqtwStl5Gz+Y431DXU9Sv6fVqIFgveweePhhDux/YV+KY +rvq5RiECgYEA7OHr8BYWkeZKuU/IkGdsdiPEEB7mNOJHwE4OXdwLIIygQGtQCuJG +EHMQv9kE/1ibVRIxqnliFb/CupZ5wwyvjFgUq5XZl7s6XpNOBhJHV0U5AJSvS0rb +YNU2PBfRmMMI/gRdF/onUpopY7ZWLv7u+VF7ZgtM5hQr2jwcjwBzbRkCgYEA6jsK +tB6SGIO2c5E+CLAY5J4eJca6ORaVcKw1OfDL346UJYkvqOLBc8KwFs87gDbwhmjn +GJUWlhk5iUoWZrFJpTj8+hVNxKumtZ5x8MQkNXL7WBNYcVxobuGVW8c6jZU3C/al +Im9DRTPXhgvMy7mu4slVaAhhrmUJRdl6fwmCR30CgYEA5FoxwML6RPGUrSl9Nb+N +riFyWvv+fZJ5Cqf0b4S08U6/GPqaMbPJSQgzaE3D5Ie9Tff5CtZyuHagOJDglie/ +fvJWEsak+QETFqK3/2BVh4qClc2/YjyqWKGQ48MuWS4CmCUKvRd4GsfkCGx4jltR +ceSbqVZRbiaZ04pJGY2ct9kCgYEArWaaLO/4zgcsGfArUXk0ZIMd5G9zS3IJnckO ++l7mPxEpYYRm8Qs1lcJKZAh0jx2dAJRGiO9OMj5oVtevL8UNtTA0L9t3oCJHH2s2 +BLzf5WXC5tgjgICdm4CK9s/N7CTMBKJKa+yci22un0C7ExLagm/0NzkFP3ry22/9 +/HAIr20CgYEAnUGwciM7Z9aMpPkX3iaRG/zm1FWbsuJldNa5IZQ6CamDIZhb+u2u +1yuCUJZ7zY51RO4n2Hi/1OU1XS7XlevoT22i7xJmIjPVoWzumUwMjmhYVqxK/X50 +Hcd+qL1Xs6KmsWrlg2sgFliX79RawE3jl/yZrFMuHvWiItXO92YFuOI= +-----END RSA PRIVATE KEY----- diff --git a/firmware/coreboot/util/nvidia/cbootimage/samples/sign.sh b/firmware/coreboot/util/nvidia/cbootimage/samples/sign.sh new file mode 100755 index 0000000000..c9d237d1a1 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/samples/sign.sh @@ -0,0 +1,123 @@ +#!/bin/bash +# +# Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# See file CREDITS for list of people who contributed to this +# project. +# + +Usage () +{ + cat << EOF +Usage: ./sign.sh + Where, + soc: tegra124, tegra210 + boot_image: image generated by cbootimage, + priv_key: rsa key file in .pem format. +EOF + exit 1; +} + +set -e + +soc=$1 # tegra124, tegra210 +if [[ "${soc}" = tegra124 ]]; then + bl_block_offset=16384; # emmc: 16384, spi_flash: 32768: default: emmc + bct_signed_offset=1712; + bct_signed_length=6480; +elif [[ "${soc}" = tegra210 ]]; then + bl_block_offset=32768; # emmc: 16384, spi_flash: 32768: default: spi + bct_signed_offset=1296; + bct_signed_length=8944; +else + echo "Error: Invalid target device: soc = $soc"; + Usage; +fi; +bct_length=$(($bct_signed_offset + $bct_signed_length)); + +# more error check +if [ $# -lt 3 ]; then + echo "Error: Missing parameter(s)"; + Usage; +fi; + +# +# In case to add more parameters in the future, we keep the last two as +# IMAGE_FILE and KEY_FILE +# +argv=($@); +IMAGE_FILE=${argv[$#-2]}; +KEY_FILE=${argv[$#-1]}; +TARGET_IMAGE=$IMAGE_FILE +CONFIG_FILE=config.tmp + +CBOOTIMAGE=../src/cbootimage +BCT_DUMP=../src/bct_dump +OBJCOPY=objcopy +OPENSSL=openssl +DD=dd +RM=rm +MV=mv +XXD=xxd +CUT=cut + +echo "Sign ${soc} ${IMAGE_FILE} with key ${KEY_FILE}" + +echo "Get bl length " +BL_LENGTH=`$BCT_DUMP $IMAGE_FILE | grep "Bootloader\[0\].Length"\ + | awk -F ' ' '{print $4}' | awk -F ';' '{print $1}'` + +echo "Extract bootloader to $IMAGE_FILE.bl.tosig, length $BL_LENGTH" +$DD bs=1 skip=${bl_block_offset} if=$IMAGE_FILE of=$IMAGE_FILE.bl.tosig \ + count=$BL_LENGTH + +echo "Calculate rsa signature for bootloader and save to $IMAGE_FILE.bl.sig" +$OPENSSL dgst -sha256 -sigopt rsa_padding_mode:pss -sigopt rsa_pss_saltlen:-1 \ + -sign $KEY_FILE -out $IMAGE_FILE.bl.sig $IMAGE_FILE.bl.tosig + +echo "Update bootloader's rsa signature, aes hash and bct's aes hash" +echo "RsaPssSigBlFile = $IMAGE_FILE.bl.sig;" > $CONFIG_FILE +echo "RehashBl;" >> $CONFIG_FILE +$CBOOTIMAGE -s ${soc} -u $CONFIG_FILE $IMAGE_FILE $IMAGE_FILE.tmp + +echo "Extract the part of bct which needs to be rsa signed" +$DD bs=1 if=$IMAGE_FILE.tmp of=$IMAGE_FILE.bct.tosig skip=${bct_signed_offset} \ + count=${bct_signed_length} + +echo "Calculate rsa signature for bct and save to $IMAGE_FILE.bct.sig" +$OPENSSL dgst -sha256 -sigopt rsa_padding_mode:pss -sigopt rsa_pss_saltlen:-1 \ + -sign $KEY_FILE -out $IMAGE_FILE.bct.sig $IMAGE_FILE.bct.tosig + +echo "Create public key modulus from key file $KEY_FILE and save to $KEY_FILE.mod" +$OPENSSL rsa -in $KEY_FILE -noout -modulus -out $KEY_FILE.mod +# remove prefix +$CUT -d= -f2 < $KEY_FILE.mod > $KEY_FILE.mod.tmp + +# convert from hexdecimal to binary +$XXD -r -p -l 256 $KEY_FILE.mod.tmp $KEY_FILE.mod.bin + +echo "Update bct's rsa signature and modulus" +echo "RsaPssSigBctFile = $IMAGE_FILE.bct.sig;" > $CONFIG_FILE +echo "RsaKeyModulusFile = $KEY_FILE.mod.bin;" >> $CONFIG_FILE +echo "" +$CBOOTIMAGE -s ${soc} -u $CONFIG_FILE $IMAGE_FILE.tmp $TARGET_IMAGE + +echo "" +$DD bs=1 if=$TARGET_IMAGE of=${soc}.bct count=${bct_length} +echo "" +echo "Signed bct ${soc}.bct has been successfully generated!"; + +#echo "Get rid of all temporary files: *.sig, *.tosig, *.tmp, *.mod, *.mod.bin" +$RM -f *.sig *.tosig *.tmp *.mod *.mod.bin diff --git a/firmware/coreboot/util/nvidia/cbootimage/samples/update.cfg b/firmware/coreboot/util/nvidia/cbootimage/samples/update.cfg new file mode 100644 index 0000000000..c5c741bad5 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/samples/update.cfg @@ -0,0 +1 @@ +RehashBl; diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/Makefile.am b/firmware/coreboot/util/nvidia/cbootimage/src/Makefile.am new file mode 100644 index 0000000000..285f9dbd62 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/Makefile.am @@ -0,0 +1,103 @@ +AUTOMAKE_OPTIONS = subdir-objects + +AM_CFLAGS = -Wall -std=c99 + +bin_PROGRAMS = cbootimage bct_dump +cbootimage_SOURCES = \ + cbootimage.c \ + data_layout.c \ + set.c \ + crypto.c \ + aes_ref.c \ + context.c \ + parse.c \ + t210/parse_t210.c \ + t132/parse_t132.c \ + t124/parse_t124.c \ + t114/parse_t114.c \ + t30/parse_t30.c \ + t20/parse_t20.c \ + t210/nvbctlib_t210.c \ + t132/nvbctlib_t132.c \ + t124/nvbctlib_t124.c \ + t114/nvbctlib_t114.c \ + t30/nvbctlib_t30.c \ + t20/nvbctlib_t20.c \ + cbootimage.h \ + context.h \ + crypto.h \ + data_layout.h \ + nvaes_ref.h \ + parse.h \ + set.h \ + t20/nvboot_bct_t20.h \ + t20/nvboot_sdram_param_t20.h \ + t30/nvboot_bct_t30.h \ + t30/nvboot_sdram_param_t30.h \ + t114/nvboot_bct_t114.h \ + t114/nvboot_sdram_param_t114.h \ + t124/nvboot_bct_t124.h \ + t124/nvboot_sdram_param_t124.h \ + t132/nvboot_bct_t132.h \ + t132/nvboot_sdram_param_t132.h \ + t210/nvboot_bct_t210.h \ + t210/nvboot_sdram_param_t210.h + +cbootimage_LDADD = -lm + +bct_dump_SOURCES = \ + bct_dump.c \ + data_layout.c \ + set.c \ + crypto.c \ + aes_ref.c \ + context.c \ + parse.c \ + t210/parse_t210.c \ + t132/parse_t132.c \ + t124/parse_t124.c \ + t114/parse_t114.c \ + t30/parse_t30.c \ + t20/parse_t20.c \ + t210/nvbctlib_t210.c \ + t132/nvbctlib_t132.c \ + t124/nvbctlib_t124.c \ + t114/nvbctlib_t114.c \ + t30/nvbctlib_t30.c \ + t20/nvbctlib_t20.c \ + cbootimage.h \ + context.h \ + crypto.h \ + data_layout.h \ + nvaes_ref.h \ + parse.h \ + set.h \ + t20/nvboot_bct_t20.h \ + t20/nvboot_sdram_param_t20.h \ + t30/nvboot_bct_t30.h \ + t30/nvboot_sdram_param_t30.h \ + t114/nvboot_bct_t114.h \ + t114/nvboot_sdram_param_t114.h \ + t124/nvboot_bct_t124.h \ + t124/nvboot_sdram_param_t124.h \ + t132/nvboot_bct_t132.h \ + t132/nvboot_sdram_param_t132.h \ + t210/nvboot_bct_t210.h \ + t210/nvboot_sdram_param_t210.h + +man_MANS = cbootimage.1 bct_dump.1 + +EXTRA_DIST = cbootimage.1.in bct_dump.1.in +DISTCLEANFILES = cbootimage.1 cbootimage.man bct_dump.1 bct_dump.man + +cbootimage.1: $(srcdir)/cbootimage.1.in + sed 's|VERSION|$(VERSION)|g' $< >$@ + +cbootimage.man: $(srcdir)/cbootimage.1 + nroff -man $< >$@ + +bct_dump.1: $(srcdir)/bct_dump.1.in + sed 's|VERSION|$(VERSION)|g' $< >$@ + +bct_dump.man: $(srcdir)/bct_dump.1 + nroff -man $< >$@ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/aes_ref.c b/firmware/coreboot/util/nvidia/cbootimage/src/aes_ref.c new file mode 100644 index 0000000000..85b7d69756 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/aes_ref.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* advanced encryption standard + * author: karl malbrain, malbrain@yahoo.com + */ + +/* +This work, including the source code, documentation +and related data, is placed into the public domain. + +The orginal author is Karl Malbrain. + +THIS SOFTWARE IS PROVIDED AS-IS WITHOUT WARRANTY +OF ANY KIND, NOT EVEN THE IMPLIED WARRANTY OF +MERCHANTABILITY. THE AUTHOR OF THIS SOFTWARE, +ASSUMES _NO_ RESPONSIBILITY FOR ANY CONSEQUENCE +RESULTING FROM THE USE, MODIFICATION, OR +REDISTRIBUTION OF THIS SOFTWARE. +*/ + +/* + * Modifications by NVIDIA: + * - Created nvaes_ref.h header. + * - Replaced type definitions with NVIDIA standard types. + * - Removed unneeded code that turns this source file into an executable. + * - Created function prototypes for some of the functions. + * - Reformatted the code to conform to coding conventions. + */ + +#include "nvaes_ref.h" + +static void shift_rows(uint8_t *state); +static void mix_sub_columns(uint8_t *state); +static void add_round_key(uint32_t *state, uint32_t *key); + +static uint8_t s_Sbox[256] = +{ /* forward s-box */ + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, + 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, + 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, + 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, + 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, + 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, + 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, + 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, + 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, + 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, + 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, + 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, + 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, + 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, + 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, + 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, + 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, + 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, + 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, + 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, + 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, + 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, + 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, + 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, + 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, + 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, + 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, + 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, + 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, + 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, + 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 +}; + +/* combined Xtimes2[Sbox[]] */ +static uint8_t s_Xtime2Sbox[256] = +{ + 0xc6, 0xf8, 0xee, 0xf6, 0xff, 0xd6, 0xde, 0x91, + 0x60, 0x02, 0xce, 0x56, 0xe7, 0xb5, 0x4d, 0xec, + 0x8f, 0x1f, 0x89, 0xfa, 0xef, 0xb2, 0x8e, 0xfb, + 0x41, 0xb3, 0x5f, 0x45, 0x23, 0x53, 0xe4, 0x9b, + 0x75, 0xe1, 0x3d, 0x4c, 0x6c, 0x7e, 0xf5, 0x83, + 0x68, 0x51, 0xd1, 0xf9, 0xe2, 0xab, 0x62, 0x2a, + 0x08, 0x95, 0x46, 0x9d, 0x30, 0x37, 0x0a, 0x2f, + 0x0e, 0x24, 0x1b, 0xdf, 0xcd, 0x4e, 0x7f, 0xea, + 0x12, 0x1d, 0x58, 0x34, 0x36, 0xdc, 0xb4, 0x5b, + 0xa4, 0x76, 0xb7, 0x7d, 0x52, 0xdd, 0x5e, 0x13, + 0xa6, 0xb9, 0x00, 0xc1, 0x40, 0xe3, 0x79, 0xb6, + 0xd4, 0x8d, 0x67, 0x72, 0x94, 0x98, 0xb0, 0x85, + 0xbb, 0xc5, 0x4f, 0xed, 0x86, 0x9a, 0x66, 0x11, + 0x8a, 0xe9, 0x04, 0xfe, 0xa0, 0x78, 0x25, 0x4b, + 0xa2, 0x5d, 0x80, 0x05, 0x3f, 0x21, 0x70, 0xf1, + 0x63, 0x77, 0xaf, 0x42, 0x20, 0xe5, 0xfd, 0xbf, + 0x81, 0x18, 0x26, 0xc3, 0xbe, 0x35, 0x88, 0x2e, + 0x93, 0x55, 0xfc, 0x7a, 0xc8, 0xba, 0x32, 0xe6, + 0xc0, 0x19, 0x9e, 0xa3, 0x44, 0x54, 0x3b, 0x0b, + 0x8c, 0xc7, 0x6b, 0x28, 0xa7, 0xbc, 0x16, 0xad, + 0xdb, 0x64, 0x74, 0x14, 0x92, 0x0c, 0x48, 0xb8, + 0x9f, 0xbd, 0x43, 0xc4, 0x39, 0x31, 0xd3, 0xf2, + 0xd5, 0x8b, 0x6e, 0xda, 0x01, 0xb1, 0x9c, 0x49, + 0xd8, 0xac, 0xf3, 0xcf, 0xca, 0xf4, 0x47, 0x10, + 0x6f, 0xf0, 0x4a, 0x5c, 0x38, 0x57, 0x73, 0x97, + 0xcb, 0xa1, 0xe8, 0x3e, 0x96, 0x61, 0x0d, 0x0f, + 0xe0, 0x7c, 0x71, 0xcc, 0x90, 0x06, 0xf7, 0x1c, + 0xc2, 0x6a, 0xae, 0x69, 0x17, 0x99, 0x3a, 0x27, + 0xd9, 0xeb, 0x2b, 0x22, 0xd2, 0xa9, 0x07, 0x33, + 0x2d, 0x3c, 0x15, 0xc9, 0x87, 0xaa, 0x50, 0xa5, + 0x03, 0x59, 0x09, 0x1a, 0x65, 0xd7, 0x84, 0xd0, + 0x82, 0x29, 0x5a, 0x1e, 0x7b, 0xa8, 0x6d, 0x2c +}; + +/* combined Xtimes3[Sbox[]] */ +static uint8_t s_Xtime3Sbox[256] = +{ + 0xa5, 0x84, 0x99, 0x8d, 0x0d, 0xbd, 0xb1, 0x54, + 0x50, 0x03, 0xa9, 0x7d, 0x19, 0x62, 0xe6, 0x9a, + 0x45, 0x9d, 0x40, 0x87, 0x15, 0xeb, 0xc9, 0x0b, + 0xec, 0x67, 0xfd, 0xea, 0xbf, 0xf7, 0x96, 0x5b, + 0xc2, 0x1c, 0xae, 0x6a, 0x5a, 0x41, 0x02, 0x4f, + 0x5c, 0xf4, 0x34, 0x08, 0x93, 0x73, 0x53, 0x3f, + 0x0c, 0x52, 0x65, 0x5e, 0x28, 0xa1, 0x0f, 0xb5, + 0x09, 0x36, 0x9b, 0x3d, 0x26, 0x69, 0xcd, 0x9f, + 0x1b, 0x9e, 0x74, 0x2e, 0x2d, 0xb2, 0xee, 0xfb, + 0xf6, 0x4d, 0x61, 0xce, 0x7b, 0x3e, 0x71, 0x97, + 0xf5, 0x68, 0x00, 0x2c, 0x60, 0x1f, 0xc8, 0xed, + 0xbe, 0x46, 0xd9, 0x4b, 0xde, 0xd4, 0xe8, 0x4a, + 0x6b, 0x2a, 0xe5, 0x16, 0xc5, 0xd7, 0x55, 0x94, + 0xcf, 0x10, 0x06, 0x81, 0xf0, 0x44, 0xba, 0xe3, + 0xf3, 0xfe, 0xc0, 0x8a, 0xad, 0xbc, 0x48, 0x04, + 0xdf, 0xc1, 0x75, 0x63, 0x30, 0x1a, 0x0e, 0x6d, + 0x4c, 0x14, 0x35, 0x2f, 0xe1, 0xa2, 0xcc, 0x39, + 0x57, 0xf2, 0x82, 0x47, 0xac, 0xe7, 0x2b, 0x95, + 0xa0, 0x98, 0xd1, 0x7f, 0x66, 0x7e, 0xab, 0x83, + 0xca, 0x29, 0xd3, 0x3c, 0x79, 0xe2, 0x1d, 0x76, + 0x3b, 0x56, 0x4e, 0x1e, 0xdb, 0x0a, 0x6c, 0xe4, + 0x5d, 0x6e, 0xef, 0xa6, 0xa8, 0xa4, 0x37, 0x8b, + 0x32, 0x43, 0x59, 0xb7, 0x8c, 0x64, 0xd2, 0xe0, + 0xb4, 0xfa, 0x07, 0x25, 0xaf, 0x8e, 0xe9, 0x18, + 0xd5, 0x88, 0x6f, 0x72, 0x24, 0xf1, 0xc7, 0x51, + 0x23, 0x7c, 0x9c, 0x21, 0xdd, 0xdc, 0x86, 0x85, + 0x90, 0x42, 0xc4, 0xaa, 0xd8, 0x05, 0x01, 0x12, + 0xa3, 0x5f, 0xf9, 0xd0, 0x91, 0x58, 0x27, 0xb9, + 0x38, 0x13, 0xb3, 0x33, 0xbb, 0x70, 0x89, 0xa7, + 0xb6, 0x22, 0x92, 0x20, 0x49, 0xff, 0x78, 0x7a, + 0x8f, 0xf8, 0x80, 0x17, 0xda, 0x31, 0xc6, 0xb8, + 0xc3, 0xb0, 0x77, 0x11, 0xcb, 0xfc, 0xd6, 0x3a +}; + +/* exchanges columns in each of 4 rows + * row0 - unchanged, row1- shifted left 1, + * row2 - shifted left 2 and row3 - shifted left 3 + */ +static void +shift_rows(uint8_t *state) +{ + uint8_t tmp; + + /* just substitute row 0 */ + state[ 0] = s_Sbox[state[ 0]]; + state[ 4] = s_Sbox[state[ 4]]; + state[ 8] = s_Sbox[state[ 8]]; + state[12] = s_Sbox[state[12]]; + + /* rotate row 1 */ + tmp = s_Sbox[state[ 1]]; + state[ 1] = s_Sbox[state[ 5]]; + state[ 5] = s_Sbox[state[ 9]]; + state[ 9] = s_Sbox[state[13]]; + state[13] = tmp; + + /* rotate row 2 */ + tmp = s_Sbox[state[ 2]]; + state[ 2] = s_Sbox[state[10]]; + state[10] = tmp; + tmp = s_Sbox[state[ 6]]; + state[ 6] = s_Sbox[state[14]]; + state[14] = tmp; + + /* rotate row 3 */ + tmp = s_Sbox[state[15]]; + state[15] = s_Sbox[state[11]]; + state[11] = s_Sbox[state[ 7]]; + state[ 7] = s_Sbox[state[ 3]]; + state[ 3] = tmp; +} + +/* recombine and mix each row in a column */ +static void +mix_sub_columns(uint8_t *state) +{ + uint8_t tmp[4 * NVAES_STATECOLS]; + + /* mixing column 0 */ + tmp[ 0] = s_Xtime2Sbox[state[ 0]] ^ s_Xtime3Sbox[state[ 5]] ^ + s_Sbox[state[10]] ^ s_Sbox[state[15]]; + tmp[ 1] = s_Sbox[state[ 0]] ^ s_Xtime2Sbox[state[ 5]] ^ + s_Xtime3Sbox[state[10]] ^ s_Sbox[state[15]]; + tmp[ 2] = s_Sbox[state[ 0]] ^ s_Sbox[state[ 5]] ^ + s_Xtime2Sbox[state[10]] ^ s_Xtime3Sbox[state[15]]; + tmp[ 3] = s_Xtime3Sbox[state[ 0]] ^ s_Sbox[state[ 5]] ^ + s_Sbox[state[10]] ^ s_Xtime2Sbox[state[15]]; + + /* mixing column 1 */ + tmp[ 4] = s_Xtime2Sbox[state[ 4]] ^ s_Xtime3Sbox[state[ 9]] ^ + s_Sbox[state[14]] ^ s_Sbox[state[ 3]]; + tmp[ 5] = s_Sbox[state[ 4]] ^ s_Xtime2Sbox[state[ 9]] ^ + s_Xtime3Sbox[state[14]] ^ s_Sbox[state[ 3]]; + tmp[ 6] = s_Sbox[state[ 4]] ^ s_Sbox[state[ 9]] ^ + s_Xtime2Sbox[state[14]] ^ s_Xtime3Sbox[state[ 3]]; + tmp[ 7] = s_Xtime3Sbox[state[ 4]] ^ s_Sbox[state[ 9]] ^ + s_Sbox[state[14]] ^ s_Xtime2Sbox[state[ 3]]; + + /* mixing column 2 */ + tmp[ 8] = s_Xtime2Sbox[state[ 8]] ^ s_Xtime3Sbox[state[13]] ^ + s_Sbox[state[ 2]] ^ s_Sbox[state[ 7]]; + tmp[ 9] = s_Sbox[state[ 8]] ^ s_Xtime2Sbox[state[13]] ^ + s_Xtime3Sbox[state[ 2]] ^ s_Sbox[state[ 7]]; + tmp[10] = s_Sbox[state[ 8]] ^ s_Sbox[state[13]] ^ + s_Xtime2Sbox[state[ 2]] ^ s_Xtime3Sbox[state[ 7]]; + tmp[11] = s_Xtime3Sbox[state[ 8]] ^ s_Sbox[state[13]] ^ + s_Sbox[state[ 2]] ^ s_Xtime2Sbox[state[ 7]]; + + /* mixing column 3 */ + tmp[12] = s_Xtime2Sbox[state[12]] ^ s_Xtime3Sbox[state[ 1]] ^ + s_Sbox[state[ 6]] ^ s_Sbox[state[11]]; + tmp[13] = s_Sbox[state[12]] ^ s_Xtime2Sbox[state[ 1]] ^ + s_Xtime3Sbox[state[ 6]] ^ s_Sbox[state[11]]; + tmp[14] = s_Sbox[state[12]] ^ s_Sbox[state[ 1]] ^ + s_Xtime2Sbox[state[ 6]] ^ s_Xtime3Sbox[state[11]]; + tmp[15] = s_Xtime3Sbox[state[12]] ^ s_Sbox[state[ 1]] ^ + s_Sbox[state[ 6]] ^ s_Xtime2Sbox[state[11]]; + + memcpy (state, tmp, sizeof(tmp)); +} + +/* encrypt/decrypt columns of the key + * n.b. you can replace this with + * byte-wise xor if you wish. + */ + +static void +add_round_key(uint32_t *state, uint32_t *key) +{ + int idx; + + for (idx = 0; idx < 4; idx++) + state[idx] ^= key[idx]; +} + +static uint8_t s_Rcon[11] = +{ + 0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36 +}; + +/* produce NVAES_STATECOLS bytes for each round */ +void +nv_aes_expand_key(uint8_t *key, uint8_t *expkey) +{ + uint8_t tmp0, tmp1, tmp2, tmp3, tmp4; + uint32_t idx; + + memcpy(expkey, key, NVAES_KEYCOLS * 4); + + for (idx = NVAES_KEYCOLS; + idx < NVAES_STATECOLS * (NVAES_ROUNDS + 1); + idx++) { + tmp0 = expkey[4*idx - 4]; + tmp1 = expkey[4*idx - 3]; + tmp2 = expkey[4*idx - 2]; + tmp3 = expkey[4*idx - 1]; + if (!(idx % NVAES_KEYCOLS)) { + tmp4 = tmp3; + tmp3 = s_Sbox[tmp0]; + tmp0 = s_Sbox[tmp1] ^ s_Rcon[idx/NVAES_KEYCOLS]; + tmp1 = s_Sbox[tmp2]; + tmp2 = s_Sbox[tmp4]; + } else if (NVAES_KEYCOLS > 6 && idx % NVAES_KEYCOLS == 4 ) { + tmp0 = s_Sbox[tmp0]; + tmp1 = s_Sbox[tmp1]; + tmp2 = s_Sbox[tmp2]; + tmp3 = s_Sbox[tmp3]; + } + + expkey[4*idx+0] = expkey[4*idx - 4*NVAES_KEYCOLS + 0] ^ tmp0; + expkey[4*idx+1] = expkey[4*idx - 4*NVAES_KEYCOLS + 1] ^ tmp1; + expkey[4*idx+2] = expkey[4*idx - 4*NVAES_KEYCOLS + 2] ^ tmp2; + expkey[4*idx+3] = expkey[4*idx - 4*NVAES_KEYCOLS + 3] ^ tmp3; + } +} + +/* encrypt one 128 bit block */ +void +nv_aes_encrypt(uint8_t *in, uint8_t *expkey, uint8_t *out) +{ + uint8_t state[NVAES_STATECOLS * 4]; + uint32_t round; + + memcpy(state, in, NVAES_STATECOLS * 4); + add_round_key((uint32_t *)state, (uint32_t *)expkey); + + for (round = 1; round < NVAES_ROUNDS + 1; round++) { + if (round < NVAES_ROUNDS) + mix_sub_columns (state); + else + shift_rows (state); + + add_round_key((uint32_t *)state, (uint32_t *)expkey + + round * NVAES_STATECOLS); + } + + memcpy(out, state, sizeof(state)); +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/bct_dump.1.in b/firmware/coreboot/util/nvidia/cbootimage/src/bct_dump.1.in new file mode 100644 index 0000000000..0a6ca27aa6 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/bct_dump.1.in @@ -0,0 +1,53 @@ +.TH bct_dump 1 "6 October 2015" "bct_dump-VERSION" "NVIDIA Tegra BCT Disassembly Tool" +.IX bct_dump +.SH NAME +bct_dump \- tegra BCT disassembly tool +.SH SYNOPSIS +.B bct_dump +.I bctfile +.SH DESCRIPTION +This program is used to take a binary Tegra Boot Configuration Table (BCT) and +disassemble it into a text format suitable to be compiled with cbootimage(1). + +.SS Platforms supported +.IP \(bu +.B Tegra20 +.IP \(bu +.B Tegra30 +.IP \(bu +.B Tegra114 +.IP \(bu +.B Tegra124 +.IP \(bu +.B Tegra132 +.IP \(bu +.B Tegra210 + +.SH OPTIONS +.TP +.B \fIbctfile\fP +Specify the BCT file to disassemble + +.SH EXAMPLES +To disassemble the BCT file for a Tegra124 Jetson-TK1: + +.nf +$ bct_dump PM375_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.bct +Version = 0x00400001; +BlockSize = 0x00004000; +PageSize = 0x00000200; +PartitionSize = 0x01000000; +OdmData = 0x800d8000; +JtagCtrl = 0x00000000; +ChipUid = 0x00000000000000000000000000000000; +# Bootloader used = 0; +# Bootloaders max = 4; +# BCT size = 8192; + ... +.fi + +.SH RETURN VALUE +If any error occurs a non zero exit status is returned. + +.SH SEE ALSO +.BR tegrarcm(1), cbootimage(1) diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/bct_dump.c b/firmware/coreboot/util/nvidia/cbootimage/src/bct_dump.c new file mode 100644 index 0000000000..5e1405be7b --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/bct_dump.c @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include "cbootimage.h" +#include "data_layout.h" +#include "context.h" +#include "parse.h" +#include "t20/nvboot_bct_t20.h" +#include + +int enable_debug; +cbootimage_soc_config * g_soc_config; + +static void format_u32_hex8(parse_token id, char const * message, void * data); +static void format_u32(parse_token id, char const * message, void * data); +static void format_chipuid(parse_token id, char const * message, void * data); +static void format_hex_16_bytes(parse_token id, char const * message, void * data); +static void format_rsa_param(parse_token id, char const * message, void * data); + +typedef void (*format_function)(parse_token id, char const * message, void * data); + +typedef struct { + parse_token id; + char const * message; + format_function format; +} value_data; + +#define PARAM_TYPE_BINARY_DATA_MAX_SIZE 256 +typedef union { + uint32_t val; + uint8_t uid[16]; + uint8_t binary[PARAM_TYPE_BINARY_DATA_MAX_SIZE]; +} param_types; + +#define MAX_PARAM_SIZE sizeof(param_types) + +static value_data const values[] = { + { token_boot_data_version, "Version = ", format_u32_hex8 }, + { token_block_size, "BlockSize = ", format_u32_hex8 }, + { token_page_size, "PageSize = ", format_u32_hex8 }, + { token_partition_size, "PartitionSize = ", format_u32_hex8 }, + { token_odm_data, "OdmData = ", format_u32_hex8 }, + { token_secure_jtag_control, "JtagCtrl = ", format_u32_hex8 }, + { token_secure_debug_control, "DebugCtrl = ", format_u32_hex8 }, + { token_crypto_hash, "BCT AES Hash = ", format_hex_16_bytes }, + { token_rsa_key_modulus, "RsaKeyModulus:\n", format_rsa_param }, + { token_rsa_pss_sig_bct, "RsaPssSigBct:\n", format_rsa_param }, + { token_unique_chip_id, "ChipUid = ", format_chipuid }, + { token_bootloader_used, "# Bootloader used = ", format_u32 }, + { token_bootloaders_max, "# Bootloaders max = ", format_u32 }, + { token_bct_size, "# BCT size = ", format_u32 }, + { token_hash_size, "# Hash size = ", format_u32 }, + { token_crypto_offset, "# Crypto offset = ", format_u32 }, + { token_crypto_length, "# Crypto length = ", format_u32 }, + { token_max_bct_search_blks, "# Max BCT search blocks = ", format_u32 }, +}; + +static value_data const bl_values[] = { + { token_bl_version, "Version = ", format_u32_hex8 }, + { token_bl_start_blk, "Start block = ", format_u32 }, + { token_bl_start_page, "Start page = ", format_u32 }, + { token_bl_length, "Length = ", format_u32 }, + { token_bl_load_addr, "Load address = ", format_u32_hex8 }, + { token_bl_entry_point, "Entry point = ", format_u32_hex8 }, + { token_bl_attribute, "Attributes = ", format_u32_hex8 }, + { token_bl_crypto_hash, "Bl AES Hash = ", format_hex_16_bytes }, + { token_rsa_pss_sig_bl, "RsaPssSigBl:\n", format_rsa_param }, +}; + +static value_data const mts_values[] = { + { token_mts_info_version, "Version = ", format_u32_hex8 }, + { token_mts_info_start_blk, "Start block = ", format_u32 }, + { token_mts_info_start_page, "Start page = ", format_u32 }, + { token_mts_info_length, "Length = ", format_u32 }, + { token_mts_info_load_addr, "Load address = ", format_u32_hex8 }, + { token_mts_info_entry_point, "Entry point = ", format_u32_hex8 }, + { token_mts_info_attribute, "Attributes = ", format_u32_hex8 }, +}; + +/*****************************************************************************/ +static void format_u32_hex8(parse_token id, char const * message, void * data) +{ + printf("%s0x%08x;\n", message, *((uint32_t *) data)); +} + +static void format_u32(parse_token id, char const * message, void * data) +{ + printf("%s%d;\n", message, *((uint32_t *) data)); +} + +static void format_chipuid(parse_token id, char const * message, void * data) +{ + uint8_t *uid = (uint8_t *)data; + int byte_index; + char uid_str[35] = "0x"; + char *s = &uid_str[2]; + + for (byte_index = 15; byte_index >= 0; byte_index--, s += 2) + sprintf(s, "%02x", uid[byte_index]); + + printf("%s%s;\n", message, uid_str); +} + +static void format_hex_16_bytes(parse_token id, char const * message, void * data) +{ + uint8_t *p_byte = (uint8_t *)data; + int byte_index; + + printf("%s", message); + for (byte_index = 0; byte_index < 16; ++byte_index) + printf("%02x", *p_byte++); + + printf(";\n"); +} + +static void format_rsa_param(parse_token id, char const * message, void * data) +{ +#define MAX_BYTE_NUMBER_PER_LINE 16 + uint8_t *rsa = (uint8_t *)data; + int size, byte_index; + + printf("%s", message); + + if (!g_soc_config->get_value_size) + return; + + size = g_soc_config->get_value_size(id); + for (byte_index = 0; byte_index < size; ++byte_index) { + printf(" %02x", *rsa++); + + if ((byte_index + 1) % MAX_BYTE_NUMBER_PER_LINE == 0) + printf("\n"); + } + + if (byte_index % MAX_BYTE_NUMBER_PER_LINE != 0) + printf("\n"); +#undef MAX_BYTE_NUMBER_PER_LINE +} + +/*****************************************************************************/ +static void usage(void) +{ + printf("Usage: bct_dump bctfile\n"); + printf(" bctfile BCT filename to read and display\n"); +} +/*****************************************************************************/ +static int max_width(field_item const * table) +{ + int width = 0; + int i; + + for (i = 0; table[i].name != NULL; ++i) { + int length = strlen(table[i].name); + + if (width < length) + width = length; + } + + return width; +} +/*****************************************************************************/ +static enum_item const * find_enum_item(build_image_context *context, + enum_item const * table, + uint32_t value) +{ + int i; + + for (i = 0; table[i].name != NULL; ++i) { + if (table[i].value == value) + return table + i; + } + + return NULL; +} +/*****************************************************************************/ +static void display_enum_value(build_image_context *context, + enum_item const * table, + uint32_t value) +{ + enum_item const * e_item = find_enum_item(context, table, value); + + if (e_item) + printf("%s", e_item->name); + else + printf("", value); +} +/*****************************************************************************/ +static int display_field_value(build_image_context *context, + field_item const * item, + uint32_t value) +{ + switch (item->type) { + case field_type_enum: + display_enum_value(context, item->enum_table, value); + break; + + case field_type_u32: + printf("0x%08x", value); + break; + + case field_type_u8: + printf("%d", value); + break; + + default: + printf("", item->type); + return 1; + } + + return 0; +} +/*****************************************************************************/ +int main(int argc, char *argv[]) +{ + int e; + build_image_context context; + uint32_t bootloaders_used; + uint32_t parameters_used; + uint32_t sdram_used; + uint32_t mts_used; + nvboot_dev_type type; + param_types data; + int i; + int j; + + if (argc != 2) + usage(); + + memset(&context, 0, sizeof(build_image_context)); + context.bct_filename = argv[1]; + + e = read_bct_file(&context); + if (e != 0) + return e; + + /* Display root values */ + for (i = 0; i < sizeof(values) / sizeof(values[0]); ++i) { + if (!g_soc_config->token_supported(values[i].id)) + continue; + + e = g_soc_config->get_value(values[i].id, &data, context.bct); + if (e) + memset(&data, 0, MAX_PARAM_SIZE); + + values[i].format(values[i].id, values[i].message, &data); + } + + /* Display bootloader values */ + e = g_soc_config->get_value(token_bootloader_used, + &bootloaders_used, + context.bct); + + if ((e == 0) && (bootloaders_used > 0)) { + int bl_count = sizeof(bl_values) / sizeof(bl_values[0]); + + printf("#\n" + "# These values are set by cbootimage using the\n" + "# bootloader provided by the Bootloader=...\n" + "# configuration option.\n" + "#\n"); + + for (i = 0; i < bootloaders_used; ++i) { + for (j = 0; j < bl_count; ++j) { + e = g_soc_config->getbl_param(i, + bl_values[j].id, + &data.val, + context.bct); + printf("# Bootloader[%d].", i); + + if (e) + data.val = -1; + + bl_values[j].format(bl_values[j].id, + bl_values[j].message, + &data); + } + } + } + + /* Display mts values */ + e = g_soc_config->get_value(token_mts_used, + &mts_used, + context.bct); + + if ((e == 0) && (mts_used> 0)) { + int mts_count = sizeof(mts_values) / sizeof(mts_values[0]); + + printf("#\n" + "# These values are set by cbootimage using the\n" + "# mts provided by the Mts=... or MtsPreboot=...\n" + "# configuration option.\n" + "#\n"); + + for (i = 0; i < mts_used; ++i) { + for (j = 0; j < mts_count; ++j) { + e = g_soc_config->get_mts_info(&context, + i, + mts_values[j].id, + &(data.val)); + printf("# Mts[%d].", i); + + if (e) + data.val = -1; + + mts_values[j].format(mts_values[j].id, + mts_values[j].message, + &data); + } + } + } + /* Display flash device parameters */ + e = g_soc_config->get_value(token_num_param_sets, + ¶meters_used, + context.bct); + + for (i = 0; (e == 0) && (i < parameters_used); ++i) { + field_item const * device_field_table = NULL; + char const * prefix = NULL; + field_item const * item; + + e = g_soc_config->get_dev_param(&context, + i, + token_dev_type, + &type); + printf("\n" + "DevType[%d] = ", i); + display_enum_value(&context, g_soc_config->devtype_table, type); + printf(";\n"); + + switch (type) { + case nvboot_dev_type_spi: + device_field_table = g_soc_config->spiflash_table; + prefix = "SpiFlashParams"; + break; + + case nvboot_dev_type_sdmmc: + device_field_table = g_soc_config->sdmmc_table; + prefix = "SdmmcParams"; + break; + + case nvboot_dev_type_nand: + device_field_table = g_soc_config->nand_table; + prefix = "NandParams"; + break; + + default: + device_field_table = NULL; + prefix = ""; + break; + } + + if (!device_field_table) + continue; + + int width = max_width(device_field_table); + + for (item = device_field_table; item->name != NULL; ++item) { + g_soc_config->get_dev_param(&context, + i, + item->token, + &data.val); + printf("DeviceParam[%d].%s.%-*s = ", + i, prefix, width, item->name); + + if (e != 0) + printf("", e); + else + display_field_value(&context, item, data.val); + + printf(";\n"); + } + } + + /* Display SDRAM parameters */ + e = g_soc_config->get_value(token_num_sdram_sets, + &sdram_used, + context.bct); + + for (i = 0; (e == 0) && (i < sdram_used); ++i) { + field_item const *item; + + printf("\n"); + + int width = max_width(g_soc_config->sdram_field_table); + + for (item = g_soc_config->sdram_field_table; item->name != NULL; ++item) { + e = g_soc_config->get_sdram_param(&context, + i, + item->token, + &data.val); + printf("SDRAM[%d].%-*s = ", i, width, item->name); + + if (e != 0) + printf("", e); + else + display_field_value(&context, item, data.val); + + printf(";\n"); + } + } + + /* Clean up memory. */ + cleanup_context(&context); + + return e; +} +/*****************************************************************************/ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/cbootimage.1.in b/firmware/coreboot/util/nvidia/cbootimage/src/cbootimage.1.in new file mode 100644 index 0000000000..89606339bb --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/cbootimage.1.in @@ -0,0 +1,84 @@ +.TH cbootimage 1 "6 October 2015" "cbootimage-VERSION" "NVIDIA Tegra Firmware Signing Tool" +.IX cbootimage +.SH NAME +cbootimage \- tegra BCT compiler +.SH SYNOPSIS +.B cbootimage +[ +.I options +] configfile [ +.I inputimage +] +.I outputimage +.SH DESCRIPTION +This program is used to create images suitable to place into the boot flash of a +device using a Tegra SoC. There are two primary modes of operation of +cbootimage: + +.nr step 1 1 +.IP \n[step] 3 +Compile a textual representation of a BCT into a binary image. +.IP \n+[step] +Generate an entire boot image from a previously compiled BCT and a bootloader +binary. + +.SS Platforms supported +.IP \(bu +.B Tegra20 +.IP \(bu +.B Tegra30 +.IP \(bu +.B Tegra114 +.IP \(bu +.B Tegra124 +.IP \(bu +.B Tegra132 +.IP \(bu +.B Tegra210 + +.SH COMMANDS +.TP +.B \-gbct +Generate the new bct file from the given config file. +.TP +.B \-h, \-\-help, \-? +Print help text and exit. + +.SH OPTIONS +.TP +.B \-d, \-\-debug +Output debugging information. +.TP +.B \-o\fIodm_data\fP +Specify the odm_data value (in hex). +.TP +.B \-t, \-\-tegra \fINN\fP +Select target device. Must be one of: 20, 30, 114, 124, 132, 210. +.TP +.B \-s, \-\-ssoc \fItegraNN\fP +Select target device. Must be one of: tegra20, tegra30, tegra114, tegra124, +tegra32, tegra210. +.TP +.B \-u \-\-update +Copy input image data and update bct configs into new image file + +.SH EXAMPLES +To generate a bct file from a text description obtained either through +bct_dump(1) or cbootimage-configs: + +.nf +$ cbootimage -gbct -t124 PM375_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.bct.cfg PM375_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.bct +New BCT file PM375_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.bct has been successfully generated! +.fi + +To generate a boot image file including the newly generated bct: +.nf +cbootimage -t124 jetson-tk1-emmc.img.cfg jetson-tk1-emmc.img +Image file jetson-tk1-emmc.img has been successfully generated! +.fi + +.SH RETURN VALUE +If any error occurs a non zero exit status is returned. + +.SH SEE ALSO +.BR tegrarcm(1), bct_dump(1) diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/cbootimage.c b/firmware/coreboot/util/nvidia/cbootimage/src/cbootimage.c new file mode 100644 index 0000000000..ca781fa6da --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/cbootimage.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * cbootimage.c - Implementation of the cbootimage tool. + */ + +#include +#include "cbootimage.h" +#include "crypto.h" +#include "data_layout.h" +#include "parse.h" +#include "set.h" +#include "context.h" +#include + +/* + * Global data + */ +int enable_debug; +static int help_only; // Only print help & exit +cbootimage_soc_config * g_soc_config; + +/* + * Function prototypes + */ +int main(int argc, char *argv[]); + +struct option cbootcmd[] = { + {"help", 0, NULL, 'h'}, + {"debug", 0, NULL, 'd'}, + {"generate", 1, NULL, 'g'}, + {"tegra", 1, NULL, 't'}, + {"odmdata", 1, NULL, 'o'}, + {"soc", 1, NULL, 's'}, + {"update", 0, NULL, 'u'}, + {0, 0, 0, 0}, +}; + +int +write_image_file(build_image_context *context) +{ + assert(context != NULL); + + return write_block_raw(context); +} + +static void +usage(void) +{ + printf("Usage: cbootimage [options] configfile [inputimage] outputimage\n"); + printf(" options:\n"); + printf(" -h, --help, -? Display this message.\n"); + printf(" -d, --debug Output debugging information.\n"); + printf(" -gbct Generate the new bct file.\n"); + printf(" -o Specify the odm_data(in hex).\n"); + printf(" -t|--tegra NN Select target device. Must be one of:\n"); + printf(" 20, 30, 114, 124, 132, 210.\n"); + printf(" Default: 20.\n"); + printf(" -s|--soc tegraNN Select target device. Must be one of:\n"); + printf(" tegra20, tegra30, tegra114, tegra124,\n"); + printf(" tegra132, tegra210.\n"); + printf(" Default: tegra20.\n"); + printf(" -u|--update Copy input image data and update bct\n"); + printf(" configs into new image file.\n"); + printf(" This feature is currently not supported on Tegra20/30.\n"); + printf(" configfile File with configuration information\n"); + printf(" inputimage Input image name. This is required\n"); + printf(" if -u|--update option is used.\n"); + printf(" outputimage Output image name\n"); +} + +static int +process_command_line(int argc, char *argv[], build_image_context *context) +{ + int c, num_filenames = 2; + + context->generate_bct = 0; + + while ((c = getopt_long(argc, argv, "hdg:t:o:s:u", cbootcmd, NULL)) != -1) { + switch (c) { + case 'h': + help_only = 1; + usage(); + return 0; + case 'd': + enable_debug = 1; + break; + case 'g': + if (!strcasecmp("bct", optarg)) { + context->generate_bct = 1; + } else { + printf("Invalid argument!\n"); + usage(); + return -EINVAL; + } + break; + case 's': + if (strncmp("tegra", optarg, 5)) { + printf("Unsupported chipname!\n"); + usage(); + return -EINVAL; + } + optarg += 5; + /* Deliberate fall-through */ + case 't': + /* Assign the soc_config based on the chip. */ + if (!strcasecmp("20", optarg)) { + t20_get_soc_config(context, &g_soc_config); + } else if (!strcasecmp("30", optarg)) { + t30_get_soc_config(context, &g_soc_config); + } else if (!strcasecmp("114", optarg)) { + t114_get_soc_config(context, &g_soc_config); + } else if (!strcasecmp("124", optarg)) { + t124_get_soc_config(context, &g_soc_config); + } else if (!strcasecmp("132", optarg)) { + t132_get_soc_config(context, &g_soc_config); + } else if (!strcasecmp("210", optarg)) { + t210_get_soc_config(context, &g_soc_config); + } else { + printf("Unsupported chipname!\n"); + usage(); + return -EINVAL; + } + break; + case 'o': + context->odm_data = strtoul(optarg, NULL, 16); + break; + case 'u': + context->update_image = 1; + num_filenames = 3; + break; + } + } + + if (argc - optind != num_filenames) { + printf("Missing configuration and/or image file name.\n"); + usage(); + return -EINVAL; + } + + /* If SoC is not specified, make the default soc_config to t20. */ + if (!context->boot_data_version) + t20_get_soc_config(context, &g_soc_config); + + /* Open the configuration file. */ + context->config_file = fopen(argv[optind++], "r"); + if (context->config_file == NULL) { + printf("Error opening config file.\n"); + return -ENODATA; + } + + /* Record the input image filename if update_image is necessary */ + if (context->update_image) + { + if (context->boot_data_version == BOOTDATA_VERSION_T20 || + context->boot_data_version == BOOTDATA_VERSION_T30) { + printf("Update image feature is not supported on" + " Tegra20/30.\n"); + return -EINVAL; + } + + context->input_image_filename = argv[optind++]; + } + + /* Record the output filename */ + context->output_image_filename = argv[optind++]; + + return 0; +} + +int +main(int argc, char *argv[]) +{ + int e = 0; + build_image_context context; + + memset(&context, 0, sizeof(build_image_context)); + + /* Process command line arguments. */ + if (process_command_line(argc, argv, &context) != 0) + return -EINVAL; + + if (help_only) + return 1; + + assert(g_soc_config != NULL); + + g_soc_config->get_value(token_bct_size, + &context.bct_size, + context.bct); + + e = init_context(&context); + if (e != 0) { + printf("context initialization failed. Aborting.\n"); + return e; + } + + if (enable_debug) { + /* Debugging information... */ + printf("bct size: %d\n", context.bct_size); + } + + /* Open the raw output file. */ + context.raw_file = fopen(context.output_image_filename, "w+"); + if (context.raw_file == NULL) { + printf("Error opening raw file %s.\n", + context.output_image_filename); + goto fail; + } + + /* Read the bct data from image if bct configs needs to be updated */ + if (context.update_image) { + uint32_t offset = 0, bct_size, actual_size; + uint8_t *data_block; + struct stat stats; + + if (stat(context.input_image_filename, &stats) != 0) { + printf("Error: Unable to query info on input file path %s\n", + context.input_image_filename); + goto fail; + } + + /* Get BCT_SIZE from input image file */ + bct_size = get_bct_size_from_image(&context); + if (bct_size < 0) { + printf("Error: Invalid input image file %s\n", + context.input_image_filename); + goto fail; + } + + while (stats.st_size > offset) { + /* Read a block of data into memory */ + if (read_from_image(context.input_image_filename, offset, bct_size, + &data_block, &actual_size, file_type_bct)) { + printf("Error reading image file %s.\n", context.input_image_filename); + goto fail; + } + + /* Check if memory data is valid BCT */ + context.bct = data_block; + if (data_is_valid_bct(&context)) { + fseek(context.config_file, 0, SEEK_SET); + process_config_file(&context, 0); + e = sign_bct(&context, context.bct); + if (e != 0) { + printf("Signing BCT failed, error: %d.\n", e); + goto fail; + } + } + + /* Write the block of data to file */ + if (actual_size != write_data_block(context.raw_file, offset, actual_size, data_block)) { + printf("Error writing image file %s.\n", context.output_image_filename); + goto fail; + } + + offset += bct_size; + } + + printf("Image file %s has been successfully generated!\n", + context.output_image_filename); + goto fail; + } + /* If we aren't generating the bct, read in config file */ + else if (context.generate_bct == 0) + process_config_file(&context, 1); + /* Generate the new bct file */ + else { + /* Initialize the bct memory */ + init_bct(&context); + /* Parse & process the contents of the config file. */ + process_config_file(&context, 0); + /* Update the BCT */ + begin_update(&context); + /* Signing the bct. */ + e = sign_bct(&context, context.bct); + if (e != 0) + printf("Signing BCT failed, error: %d.\n", e); + + fwrite(context.bct, 1, context.bct_size, + context.raw_file); + printf("New BCT file %s has been successfully generated!\n", + context.output_image_filename); + goto fail; + } + + /* Peform final signing & encryption of bct. */ + e = sign_bct(&context, context.bct); + if (e != 0) { + printf("Signing BCT failed, error: %d.\n", e); + goto fail; + } + /* Write the image file. */ + /* The image hasn't been written yet. */ + if (write_image_file(&context) != 0) + printf("Error writing image file.\n"); + else + printf("Image file %s has been successfully generated!\n", + context.output_image_filename); + + fail: + /* Close the file(s). */ + if (context.raw_file) + fclose(context.raw_file); + + /* Clean up memory. */ + cleanup_context(&context); + return e; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/cbootimage.h b/firmware/coreboot/util/nvidia/cbootimage/src/cbootimage.h new file mode 100644 index 0000000000..1cc4c27d65 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/cbootimage.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * cbootimage.h - Definitions for the cbootimage code. + */ + +#ifndef INCLUDED_BUILDIMAGE_H +#define INCLUDED_BUILDIMAGE_H + +#include +#include +#include +#include +#include +#include +#include + +#define NVBOOT_AES_BLOCK_SIZE_LOG2 4 +#define MAX_BUFFER 200 +#define MAX_STR_LEN 20 +#define MAX_BOOTLOADER_SIZE (16 * 1024 * 1024) +#define NVBOOT_BOOTDATA_VERSION(a, b) ((((a)&0xffff) << 16) | ((b)&0xffff)) +#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096 +#define NV_MAX(a, b) (((a) > (b)) ? (a) : (b)) +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +#define BOOTDATA_VERSION_T20 NVBOOT_BOOTDATA_VERSION(0x2, 0x1) +#define BOOTDATA_VERSION_T30 NVBOOT_BOOTDATA_VERSION(0x3, 0x1) +#define BOOTDATA_VERSION_T114 NVBOOT_BOOTDATA_VERSION(0x35, 0x1) +#define BOOTDATA_VERSION_T124 NVBOOT_BOOTDATA_VERSION(0x40, 0x1) +#define BOOTDATA_VERSION_T132 NVBOOT_BOOTDATA_VERSION(0x13, 0x1) +#define BOOTDATA_VERSION_T210 NVBOOT_BOOTDATA_VERSION(0x21, 0x1) + +#define MAX_MTS_SIZE (4 * 1024 * 1024) + +/* Minimum size to read to at least be able to validate a BCT, it must + * include the boot_data_version field with any BCT version while not + * beeing larger than the smallest possible BCT. The currently supported + * BCT are as follow: + * + * Chip Version offset Total size + * T20 32 4080 + * T30 32 6128 + * T114 1792 8192 + * T124 1744 8192 + * T132 1744 8704 + * T210 1328 10240 + */ +#define NVBOOT_CONFIG_TABLE_SIZE_MIN 4080 +#define NVBOOT_CONFIG_TABLE_SIZE_MAX (10 * 1024) + +/* + * Enumerations + */ + +typedef enum +{ + file_type_bl = 0, + file_type_bct, + file_type_mts, + file_type_bin, +} file_type; + +/* + * The main context data structure of cbootimage tool + */ +typedef struct build_image_context_rec +{ + FILE *config_file; + char *output_image_filename; + char *input_image_filename; + FILE *raw_file; + uint32_t block_size; + uint32_t block_size_log2; + uint32_t page_size; + uint32_t page_size_log2; + uint32_t pages_per_blk; + uint32_t partition_size; + uint32_t redundancy; + uint32_t version; + uint32_t bct_copy; + /* + * Number of blocks at start of device to skip before the BCT. + * This may be used to reserve space for a partition table, for + * example, in order to write the resultant boot image to e.g. an + * SD card while using the remaining space for a user filesystem. + */ + uint32_t pre_bct_pad_blocks; + /* Allocation data. */ + struct blk_data_rec *memory; /* Representation of memory */ + /* block number for the BCT block */ + uint32_t next_bct_blk; + + char *newbl_filename; + uint32_t newbl_load_addr; + uint32_t newbl_entry_point; + uint32_t newbl_attr; + uint8_t generate_bct; + uint8_t *bct; + + char *mts_filename; + uint32_t mts_load_addr; + uint32_t mts_entry_point; + uint32_t mts_attr; + + char *bct_filename; + uint32_t last_blk; + uint32_t bct_size; /* The BCT file size */ + uint32_t boot_data_version; /* The boot data version of BCT */ + uint8_t bct_init; /* The flag for the memory allocation of bct */ + uint32_t odm_data; /* The odm data value */ + uint8_t unique_chip_id[16]; /* The unique chip uid */ + uint8_t secure_jtag_control; /* The flag for enabling jtag control */ + uint32_t secure_debug_control; /* The flag for enabling jtag control */ + uint8_t update_image; /* The flag for updating image */ +} build_image_context; + +/* Function prototypes */ + +int write_image_file(build_image_context *context); + +/* Global data */ +extern int enable_debug; + +#endif /* #ifndef INCLUDED_BUILDIMAGE_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/context.c b/firmware/coreboot/util/nvidia/cbootimage/src/context.c new file mode 100644 index 0000000000..f90f826986 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/context.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include "cbootimage.h" +#include "data_layout.h" +#include "set.h" + +void +cleanup_context(build_image_context *context) +{ + destroy_block_list(context->memory); + free(context->bct); +} + +int +init_context(build_image_context *context) +{ + uint32_t value; + + /* Set defaults */ + context->memory = new_block_list(); + context->next_bct_blk = 0; /* Default to block 0 */ + value = 1; + context_set_value(context, token_redundancy, &value); + context_set_value(context, token_version, &value); + value = 2; + context_set_value(context, token_bct_copy, &value); + + return 0; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/context.h b/firmware/coreboot/util/nvidia/cbootimage/src/context.h new file mode 100644 index 0000000000..6e724718b6 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/context.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#ifndef INCLUDED_CONTEXT_H +#define INCLUDED_CONTEXT_H + +#include "cbootimage.h" + +int init_context(build_image_context *context); +void cleanup_context(build_image_context *context); + +#endif /* #ifndef INCLUDED_CONTEXT_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/crypto.c b/firmware/coreboot/util/nvidia/cbootimage/src/crypto.c new file mode 100644 index 0000000000..67d90e3684 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/crypto.c @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * crypto.c - Cryptography support + */ +#include "crypto.h" +#include "parse.h" +#include "nvaes_ref.h" +#include + +/* Local function declarations */ +static void +apply_cbc_chain_data(uint8_t *cbc_chain_data, + uint8_t *src, + uint8_t *dst); + +static void +generate_key_schedule(uint8_t *key, uint8_t *key_schedule); + +static void +encrypt_object( uint8_t *key_schedule, + uint8_t *src, + uint8_t *dst, + uint32_t num_aes_blocks); + +static int +encrypt_and_sign(uint8_t *key, + uint8_t *src, + uint32_t length, + uint8_t *sig_dst); + +uint8_t enable_debug_crypto = 0; + +/* Implementation */ +static uint8_t zero_key[16] = { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; + +static void +print_vector(char *name, uint32_t num_bytes, uint8_t *data) +{ + uint32_t i; + + printf("%s [%d] @%p", name, num_bytes, data); + for (i=0; i> 7; /* get most significant bit */ + } +} + +static void +sign_objext( + uint8_t *key, + uint8_t *key_schedule, + uint8_t *src, + uint8_t *dst, + uint32_t num_aes_blocks) +{ + uint32_t i; + uint8_t *cbc_chain_data; + + uint8_t l[KEY_LENGTH]; + uint8_t k1[KEY_LENGTH]; + uint8_t tmp_data[KEY_LENGTH]; + + cbc_chain_data = zero_key; /* Convenient array of 0's for IV */ + + /* compute k1 constant needed by AES-CMAC calculation */ + + for (i=0; i> 7) != 0 ) /* get MSB of L */ + k1[KEY_LENGTH-1] ^= AES_CMAC_CONST_RB; + + if (enable_debug_crypto) + print_vector("K1", KEY_LENGTH, k1); + + /* compute the AES-CMAC value */ + for (i = 0; i < num_aes_blocks; i++) { + /* Apply the chain data */ + apply_cbc_chain_data(cbc_chain_data, src, tmp_data); + + /* for the final block, XOR k1 into the IV */ + if ( i == num_aes_blocks-1 ) + apply_cbc_chain_data(tmp_data, k1, tmp_data); + + /* encrypt the AES block */ + nv_aes_encrypt(tmp_data, key_schedule, (uint8_t*)dst); + + if (enable_debug_crypto) { + printf("sign_objext: block %d of %d\n", i, + num_aes_blocks); + print_vector("AES-CMAC Src", KEY_LENGTH, src); + print_vector("AES-CMAC Xor", KEY_LENGTH, tmp_data); + print_vector("AES-CMAC Dst", + KEY_LENGTH, + (uint8_t*)dst); + } + + /* Update pointers for next loop. */ + cbc_chain_data = (uint8_t*)dst; + src += KEY_LENGTH; + } + + if (enable_debug_crypto) + print_vector("AES-CMAC Hash", KEY_LENGTH, (uint8_t*)dst); +} + +static int +encrypt_and_sign(uint8_t *key, + uint8_t *src, + uint32_t length, + uint8_t *sig_dst) +{ + uint32_t num_aes_blocks; + uint8_t key_schedule[4*NVAES_STATECOLS*(NVAES_ROUNDS+1)]; + + if (enable_debug_crypto) { + printf("encrypt_and_sign: length = %d\n", length); + print_vector("AES key", KEY_LENGTH, key); + } + + generate_key_schedule(key, key_schedule); + + num_aes_blocks = ICEIL(length, KEY_LENGTH); + + if (enable_debug_crypto) + printf("encrypt_and_sign: begin signing\n"); + + /* encrypt the data, overwriting the result in signature. */ + sign_objext(key, key_schedule, src, sig_dst, num_aes_blocks); + + if (enable_debug_crypto) + printf("encrypt_and_sign: end signing\n"); + + return 0; +} + +int +sign_data_block(uint8_t *source, + uint32_t length, + uint8_t *signature) +{ + return encrypt_and_sign(zero_key, + source, + length, + signature); +} + +int +sign_bct(build_image_context *context, + uint8_t *bct) +{ + uint32_t Offset; + uint32_t length; + uint32_t hash_size; + uint8_t *hash_buffer = NULL; + int e = 0; + + assert(bct != NULL); + + if (g_soc_config->get_value(token_hash_size, + &hash_size, + bct) != 0) + return -ENODATA; + if (g_soc_config->get_value(token_crypto_offset, + &Offset, + bct) != 0) + return -ENODATA; + if (g_soc_config->get_value(token_crypto_length, + &length, + bct) != 0) + return -ENODATA; + + hash_buffer = calloc(1, hash_size); + if (hash_buffer == NULL) + return -ENOMEM; + e = sign_data_block(bct + Offset, length, hash_buffer); + if (e != 0) + goto fail; + e = g_soc_config->set_data(token_crypto_hash, + hash_buffer, + hash_size, + bct); + if (e != 0) + goto fail; + + fail: + free(hash_buffer); + return e; +} + +/* + * reverse_byte_order + * + * Reverse the order of bytes pointed by 'in' and place the results + * to location pointed by 'out'. If 'out' is the same as 'in', then + * order of bytes pointed by 'in' is reversed. + */ +void +reverse_byte_order( + uint8_t *out, + const uint8_t *in, + const uint32_t size) +{ + uint32_t i, j; + uint8_t b1, b2; + + for (i = 0; i < size / 2; i++) { + j = size - 1 - i; + b1 = in[i]; + b2 = in[j]; + out[i] = b2; + out[j] = b1; + } + + /* In case odd number of bytes */ + if (size % 2) + out[size / 2] = in[size / 2]; +} + +int +sign_bl(build_image_context *context, + uint8_t *bootloader, + uint32_t length, + uint32_t image_instance) +{ + int e = 0; + uint8_t *hash_buffer; + uint32_t hash_size; + + g_soc_config->get_value(token_hash_size, + &hash_size, context->bct); + + hash_buffer = calloc(1, hash_size); + if (hash_buffer == NULL) + return -ENOMEM; + + /* Encrypt and compute hash */ + if ((e = sign_data_block(bootloader, + length, + hash_buffer)) != 0) + goto fail; + + if ((e = g_soc_config->setbl_param(image_instance, + token_bl_crypto_hash, + (uint32_t*)hash_buffer, + context->bct)) != 0) + goto fail; + + fail: + free(hash_buffer); + return e; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/crypto.h b/firmware/coreboot/util/nvidia/cbootimage/src/crypto.h new file mode 100644 index 0000000000..7bcbc84261 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/crypto.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * crypto.h - Definitions for the crypto support. + */ + +#ifndef INCLUDED_CRYPTO_H_N +#define INCLUDED_CRYPTO_H_N + +#include "cbootimage.h" + +/* lengths, in bytes */ +#define KEY_LENGTH (128/8) + +#define ICEIL(a, b) (((a) + (b) - 1)/(b)) + +#define AES_CMAC_CONST_RB 0x87 // from RFC 4493, Figure 2.2 + +/* Function prototypes */ + +int +sign_bct(build_image_context *context, + uint8_t *bct); + +int +sign_data_block(uint8_t *source, + uint32_t length, + uint8_t *signature); + +void +reverse_byte_order( + uint8_t *out, + const uint8_t *in, + const uint32_t size); + +int +sign_bl(build_image_context *context, + uint8_t *bootloader, + uint32_t length, + uint32_t image_instance); + +#endif /* #ifndef INCLUDED_CRYPTO_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/data_layout.c b/firmware/coreboot/util/nvidia/cbootimage/src/data_layout.c new file mode 100644 index 0000000000..2ed486bf12 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/data_layout.c @@ -0,0 +1,1118 @@ +/* + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * data_layout.c - Code to manage the layout of data in the boot device. + * + */ + +#include "data_layout.h" +#include "cbootimage.h" +#include "crypto.h" +#include "set.h" +#include "context.h" +#include "parse.h" +#include + +typedef struct blk_data_rec +{ + uint32_t blk_number; + uint32_t pages_used; /* pages always used starting from 0. */ + uint8_t *data; + + /* Pointer to ECC errors? */ + + struct blk_data_rec *next; +} block_data; + +/* Function prototypes */ +static block_data +*new_block(uint32_t blk_number, uint32_t block_size); +static block_data +*find_block(uint32_t blk_number, block_data *block_list); +static block_data +*add_block(uint32_t blk_number, block_data **block_list, + uint32_t block_size); +static int +erase_block(build_image_context *context, uint32_t blk_number); + +static int +write_page(build_image_context *context, + uint32_t blk_number, + uint32_t page_number, + uint8_t *data); + +static void +insert_padding(uint8_t *data, uint32_t length); + +static void +write_padding(uint8_t *data, uint32_t length); + +static int write_bct(build_image_context *context, + uint32_t block, + uint32_t bct_slot); + +static void +set_bl_data(build_image_context *context, + uint32_t instance, + uint32_t start_blk, + uint32_t start_page, + uint32_t length); + +static int write_image(build_image_context *context, file_type image_type); + +static void find_new_bct_blk(build_image_context *context); +static int finish_update(build_image_context *context); + +uint32_t +iceil_log2(uint32_t a, uint32_t b) +{ + return (a + (1 << b) - 1) >> b; +} + +/* Returns the smallest power of 2 >= a */ +uint32_t +ceil_log2(uint32_t a) +{ + uint32_t result; + + result = log2(a); + if ((1UL << result) < a) + result++; + + return result; +} + +static block_data *new_block(uint32_t blk_number, uint32_t block_size) +{ + block_data *new_block = malloc(sizeof(block_data)); + if (new_block == NULL) + return NULL; + + new_block->blk_number = blk_number; + new_block->pages_used = 0; + new_block->data = malloc(block_size); + if (new_block->data == NULL) { + free(new_block); + return NULL; + } + new_block->next = NULL; + + memset(new_block->data, 0, block_size); + + return new_block; +} + +block_data *new_block_list(void) +{ + return NULL; +} + +void destroy_block_list(block_data *block_list) +{ + block_data *next; + + while (block_list) { + next = block_list->next; + free(block_list->data); + free(block_list); + block_list = next; + } +} + +static block_data *find_block(uint32_t blk_number, block_data *block_list) +{ + while (block_list) { + if (block_list->blk_number == blk_number) + return block_list; + + block_list = block_list->next; + } + + return NULL; +} + +/* Returns pointer to block after adding it to block_list, if needed. */ +static block_data *add_block(uint32_t blk_number, + block_data **block_list, + uint32_t block_size) +{ + block_data *block = find_block(blk_number,*block_list); + block_data *parent; + + if (block == NULL) { + block = new_block(blk_number, block_size); + if (block == NULL) + return block; + + /* Insert block into the list */ + if ((*block_list == NULL) || + (blk_number < (*block_list)->blk_number)) { + block->next = *block_list; + *block_list = block; + } else { + /* Search for the correct place to insert the block. */ + parent = *block_list; + while (parent->next != NULL && + parent->next->blk_number < blk_number) { + parent = parent->next; + } + + block->next = parent->next; + parent->next = block; + } + } + + return block; +} + +static int +erase_block(build_image_context *context, uint32_t blk_number) +{ + block_data *block; + + assert(context != NULL); + + block = add_block(blk_number, &(context->memory), context->block_size); + + if (block == NULL) + return -ENOMEM; + if (block->data == NULL) + return -ENOMEM; + + memset(block->data, 0, context->block_size); + block->pages_used = 0; + return 0; +} + +static int +write_page(build_image_context *context, + uint32_t blk_number, + uint32_t page_number, + uint8_t *data) +{ + block_data *block; + uint8_t *page_ptr; + + assert(context); + + block = add_block(blk_number, &(context->memory), context->block_size); + + if (block == NULL) + return -ENOMEM; + if (block->data == NULL) + return -ENOMEM; + assert(((page_number + 1) * context->page_size) + <= context->block_size); + + if (block->pages_used != page_number) { + printf("Warning: Writing page in block out of order.\n"); + printf(" block=%d page=%d\n", blk_number, page_number); + } + + page_ptr = block->data + (page_number * context->page_size); + memcpy(page_ptr, data, context->page_size); + if (block->pages_used < (page_number+1)) + block->pages_used = page_number+1; + return 0; +} + +static void +insert_padding(uint8_t *data, uint32_t length) +{ + uint32_t aes_blks; + uint32_t remaining; + + aes_blks = iceil_log2(length, NVBOOT_AES_BLOCK_SIZE_LOG2); + remaining = (aes_blks << NVBOOT_AES_BLOCK_SIZE_LOG2) - length; + + write_padding(data + length, remaining); +} + +static void +write_padding(uint8_t *p, uint32_t remaining) +{ + uint8_t value = 0x80; + + while (remaining) { + *p++ = value; + remaining--; + value = 0x00; + } +} + +static int +write_bct(build_image_context *context, + uint32_t block, + uint32_t bct_slot) +{ + uint32_t pagesremaining; + uint32_t page; + uint32_t pages_per_bct; + uint8_t *buffer; + uint8_t *data; + int err = 0; + + assert(context); + + pages_per_bct = iceil_log2(context->bct_size, context->page_size_log2); + pagesremaining = pages_per_bct; + page = bct_slot * pages_per_bct; + + /* Create a local copy of the BCT data */ + buffer = malloc(pages_per_bct * context->page_size); + if (buffer == NULL) + return -ENOMEM; + memset(buffer, 0, pages_per_bct * context->page_size); + + memcpy(buffer, context->bct, context->bct_size); + + insert_padding(buffer, context->bct_size); + + /* Encrypt and compute hash */ + err = sign_bct(context, buffer); + if (err != 0) + goto fail; + + /* Write the BCT data to the storage device, picking up ECC errors */ + data = buffer; + while (pagesremaining > 0) { + err = write_page(context, block, page, data); + if (err != 0) + goto fail; + page++; + pagesremaining--; + data += context->page_size; + } +fail: + /* Cleanup */ + free(buffer); + return err; +} + +#define SET_BL_FIELD(instance, field, value) \ +do { \ + g_soc_config->setbl_param(instance, \ + token_bl_##field, \ + &(value), \ + context->bct); \ +} while (0); + +#define GET_BL_FIELD(instance, field, ptr) \ +g_soc_config->getbl_param(instance, \ + token_bl_##field, \ + ptr, \ + context->bct); + +#define COPY_BL_FIELD(from, to, field) \ +do { \ + uint32_t v; \ + GET_BL_FIELD(from, field, &v); \ + SET_BL_FIELD(to, field, v); \ +} while (0); + +#define SET_MTS_FIELD(instance, field, value) \ +do { \ + g_soc_config->set_mts_info(context, \ + instance, \ + token_mts_info_##field, \ + value); \ +} while (0); + +#define GET_MTS_FIELD(instance, field, ptr) \ +g_soc_config->get_mts_info(context, \ + instance, \ + token_mts_info_##field, \ + ptr); + +#define COPY_MTS_FIELD(from, to, field) \ +do { \ + uint32_t v; \ + GET_MTS_FIELD(from, field, &v); \ + SET_MTS_FIELD(to, field, v); \ +} while (0); + +#define SET_FIELD(is_bl, instance, field, value)\ +do { \ + if (is_bl) { \ + SET_BL_FIELD(instance, field,value); \ + } \ + else { \ + SET_MTS_FIELD(instance, field, value); \ + } \ +} while (0); + +#define GET_FIELD(is_bl, instance, field, ptr) \ +do { \ + if (is_bl) { \ + GET_BL_FIELD(instance, field, ptr); \ + } \ + else { \ + GET_MTS_FIELD(instance, field, ptr); \ + } \ +} while (0); + +#define COPY_FIELD(is_bl, from, to, field) \ +do { \ + if (is_bl) { \ + COPY_BL_FIELD(from, to, field); \ + } \ + else { \ + COPY_MTS_FIELD(from, to, field); \ + } \ +} while (0); + +static void +set_bl_data(build_image_context *context, + uint32_t instance, + uint32_t start_blk, + uint32_t start_page, + uint32_t length) +{ + assert(context); + + SET_BL_FIELD(instance, version, context->version); + SET_BL_FIELD(instance, start_blk, start_blk); + SET_BL_FIELD(instance, start_page, start_page); + SET_BL_FIELD(instance, length, length); + SET_BL_FIELD(instance, load_addr, context->newbl_load_addr); + SET_BL_FIELD(instance, entry_point, context->newbl_entry_point); + SET_BL_FIELD(instance, attribute, context->newbl_attr); +} + +static void +set_mts_data(build_image_context *context, + uint32_t instance, + uint32_t start_blk, + uint32_t start_page, + uint32_t length) +{ + assert(context); + + SET_MTS_FIELD(instance, version, context->version); + SET_MTS_FIELD(instance, start_blk, start_blk); + SET_MTS_FIELD(instance, start_page, start_page); + SET_MTS_FIELD(instance, length, length); + SET_MTS_FIELD(instance, load_addr, context->mts_load_addr); + SET_MTS_FIELD(instance, entry_point, context->mts_entry_point); + SET_MTS_FIELD(instance, attribute, context->mts_attr); +} + +#define SET_DATA(is_bl, context, instance, start_blk, start_page, length) \ +do { \ + if (is_bl) \ + set_bl_data(context, instance, start_blk, start_page, length); \ + else \ + set_mts_data(context, instance, start_blk, start_page, length); \ +} while (0); + +/* + * Load the image then update it with the information from config file. + * In the interest of expediency, all image's allocated from bottom to top + * start at page 0 of a block, and all image's allocated from top to bottom + * end at the end of a block. + * + * @param context The main context pointer + * @param image_type The image type. Can be file_type_bl or file_type_mts + * only right now + * @return 0 for success + */ +static int +write_image(build_image_context *context, file_type image_type) +{ + uint32_t i, j; + uint32_t image_instance; + uint32_t image_move_count = 0; + uint32_t image_move_remaining; + uint32_t current_blk; + uint32_t current_page; + uint32_t pages_in_image; + uint32_t image_used; + uint8_t *image_storage; /* Holds the image after reading */ + uint8_t *buffer; /* Holds the image for writing */ + uint8_t *src; /* Scans through the image during writing */ + uint32_t image_actual_size; /* In bytes */ + uint32_t pagesremaining; + uint32_t virtual_blk; + uint32_t pages_per_blk; + uint32_t image_version; + uint8_t *hash_buffer; + uint32_t hash_size; + uint32_t image_max; + parse_token token; + int err = 0, is_bl; + + assert(context); + + /* Only support bootloader and mts image right now */ + if (image_type == file_type_bl) { + is_bl = 1; + } + else if (image_type == file_type_mts) { + is_bl = 0; + } + else { + printf("Not supported image type!\n"); + return -EINVAL; + } + + pages_per_blk = 1 << (context->block_size_log2 + - context->page_size_log2); + + g_soc_config->get_value(token_hash_size, + &hash_size, context->bct); + token = is_bl ? token_bootloaders_max : token_mts_max; + g_soc_config->get_value(token, &image_max, context->bct); + + hash_buffer = calloc(1, hash_size); + if (hash_buffer == NULL) + return -ENOMEM; + + if (enable_debug) { + printf("writing %s\n", is_bl ? "bootloader" : "mts image"); + printf(" redundancy = %d\n", context->redundancy); + } + + /* Make room for the image in the BCT. */ + + /* Determine how many to move. + * Note that this code will count Mts[0] only if there is already + * a mts in the device. + */ + GET_FIELD(is_bl, 0, version, &image_version); + token = is_bl ? token_bootloader_used : token_mts_used; + g_soc_config->get_value(token, &image_used, context->bct); + for (image_instance = 0; image_instance < image_used; image_instance++) { + uint32_t tmp; + GET_FIELD(is_bl, image_instance, version, &tmp); + if (tmp == image_version) + image_move_count++; + } + + /* Adjust the move count, if needed, to avoid overflowing the mts table. + * This can happen due to too much redundancy. + */ + image_move_count = MIN(image_move_count, image_max - context->redundancy); + + /* Move the mts entries down. */ + image_move_remaining = image_move_count; + while (image_move_remaining > 0) { + uint32_t inst_from = image_move_remaining - 1; + uint32_t inst_to = + image_move_remaining + context->redundancy - 1; + + COPY_FIELD(is_bl, inst_from, inst_to, version); + COPY_FIELD(is_bl, inst_from, inst_to, start_blk); + COPY_FIELD(is_bl, inst_from, inst_to, start_page); + COPY_FIELD(is_bl, inst_from, inst_to, length); + COPY_FIELD(is_bl, inst_from, inst_to, load_addr); + COPY_FIELD(is_bl, inst_from, inst_to, entry_point); + COPY_FIELD(is_bl, inst_from, inst_to, attribute); + + if (is_bl) { + g_soc_config->getbl_param(inst_from, + token_bl_crypto_hash, + (uint32_t*)hash_buffer, + context->bct); + g_soc_config->setbl_param(inst_to, + token_bl_crypto_hash, + (uint32_t*)hash_buffer, + context->bct); + } + + image_move_remaining--; + } + + /* Read the image into memory. */ + if (read_from_image( + is_bl ? context->newbl_filename : context->mts_filename, + 0, + is_bl ? MAX_BOOTLOADER_SIZE : MAX_MTS_SIZE, + &image_storage, + &image_actual_size, + image_type) == 1) { + printf("Error reading image %s.\n", + is_bl ? context->newbl_filename : context->mts_filename); + exit(1); + } + + pages_in_image = iceil_log2(image_actual_size, context->page_size_log2); + + current_blk = context->next_bct_blk; + current_page = 0; + for (image_instance = 0; image_instance < context->redundancy; + image_instance++) { + + pagesremaining = pages_in_image; + /* Advance to the next block if needed. */ + if (current_page > 0) { + current_blk++; + current_page = 0; + } + + virtual_blk = 0; + + while (pagesremaining > 0) { + /* Update the bad block table with relative + * bad blocks. + */ + if (virtual_blk == 0) { + SET_DATA(is_bl, + context, + image_instance, + current_blk, + current_page, + image_actual_size); + } + + if (pagesremaining > pages_per_blk) { + current_blk++; + virtual_blk++; + pagesremaining -= pages_per_blk; + } else { + current_page = pagesremaining; + pagesremaining = 0; + } + } + } + + /* Scan forwards to write each copy. */ + for (image_instance = 0; image_instance < context->redundancy; + image_instance++) { + + /* Create a local copy of the BCT data */ + buffer = malloc(pages_in_image * context->page_size); + if (buffer == NULL) + return -ENOMEM; + + memset(buffer, 0, pages_in_image * context->page_size); + memcpy(buffer, image_storage, image_actual_size); + + insert_padding(buffer, image_actual_size); + + pagesremaining = pages_in_image; + + if (is_bl) { + GET_BL_FIELD(image_instance, start_blk, ¤t_blk); + GET_BL_FIELD(image_instance, start_page, ¤t_page); + + /* Encrypt and compute hash */ + sign_data_block(buffer, + image_actual_size, + hash_buffer); + g_soc_config->setbl_param(image_instance, + token_bl_crypto_hash, + (uint32_t*)hash_buffer, + context->bct); + } + + GET_FIELD(is_bl, image_instance, start_blk, ¤t_blk); + GET_FIELD(is_bl, image_instance, start_page, ¤t_page); + + /* Write the BCT data to the storage device, + * picking up ECC errors + */ + src = buffer; + + /* Write pages as we go. */ + virtual_blk = 0; + while (pagesremaining) { + if (current_page == 0) { + /* Erase the block before writing into it. */ + erase_block(context, current_blk); + } + + err = write_page(context, + current_blk, current_page, src); + if (err != 0) + goto fail; + pagesremaining--; + src += context->page_size; + current_page++; + if (current_page >= pages_per_blk) { + current_page = 0; + current_blk++; + virtual_blk++; + } + context->last_blk = current_blk; + } + context->next_bct_blk = context->last_blk + 1; + free(buffer); + } + + image_used = context->redundancy + image_move_count; + token = is_bl ? token_bootloader_used : token_mts_used; + g_soc_config->set_value(token, &image_used, context->bct); + + if (enable_debug) { + for (i = 0; i < image_max; i++) { + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + + GET_FIELD(is_bl, i, version, &version); + GET_FIELD(is_bl, i, start_blk, &start_blk); + GET_FIELD(is_bl, i, start_page, &start_page); + GET_FIELD(is_bl, i, length, &length); + GET_FIELD(is_bl, i, load_addr, &load_addr); + GET_FIELD(is_bl, i, entry_point, &entry_point); + + printf("%s%s[%d]: %d %04d %04d %04d 0x%08x 0x%08x\n", + i < image_used ? " " : "**", + is_bl ? "BL" : "MTS", + i, + version, + start_blk, + start_page, + length, + load_addr, + entry_point); + if (is_bl) { + g_soc_config->getbl_param(i, + token_bl_crypto_hash, + (uint32_t*)hash_buffer, + context->bct); + for (j = 0; j < hash_size / 4; j++) { + printf("%08x", + *((uint32_t*)(hash_buffer + 4*j))); + } + printf("\n"); + } + } + } + free(image_storage); + free(hash_buffer); + return 0; + +fail: + /* Cleanup. */ + free(buffer); + free(image_storage); + free(hash_buffer); + printf("Write image failed, error: %d.\n", err); + return err; +} + +void +update_context(struct build_image_context_rec *context) +{ + g_soc_config->get_value(token_partition_size, + &context->partition_size, + context->bct); + g_soc_config->get_value(token_page_size_log2, + &context->page_size_log2, + context->bct); + g_soc_config->get_value(token_block_size_log2, + &context->block_size_log2, + context->bct); + g_soc_config->get_value(token_odm_data, + &context->odm_data, + context->bct); + + context->page_size = 1 << context->page_size_log2; + context->block_size = 1 << context->block_size_log2; + context->pages_per_blk = 1 << (context->block_size_log2 - + context->page_size_log2); +} + +/* + * Allocate and initialize the memory for bct data. + * + * @param context The main context pointer + * @return 0 for success + */ +int +init_bct(struct build_image_context_rec *context) +{ + /* Allocate space for the bct. */ + context->bct = malloc(context->bct_size); + + if (context->bct == NULL) + return -ENOMEM; + + memset(context->bct, 0, context->bct_size); + context->bct_init = 1; + + return 0; +} + +/* + * Read the bct data from given file to allocated memory. + * Assign the global parse interface to corresponding hardware interface + * according to the boot data version in bct file. + * + * @param context The main context pointer + * @return 0 for success + */ +int +read_bct_file(struct build_image_context_rec *context) +{ + uint8_t *bct_storage; /* Holds the Bl after reading */ + uint32_t bct_actual_size; /* In bytes */ + file_type bct_filetype = file_type_bct; + int err = 0; + + if (read_from_image(context->bct_filename, + 0, + NVBOOT_CONFIG_TABLE_SIZE_MAX, + &bct_storage, + &bct_actual_size, + bct_filetype) == 1) { + printf("Error reading bct file %s.\n", context->bct_filename); + exit(1); + } + + context->bct_size = bct_actual_size; + if (context->bct_init != 1) + err = init_bct(context); + if (err != 0) { + printf("Context initialization failed. Aborting.\n"); + return err; + } + memcpy(context->bct, bct_storage, context->bct_size); + free(bct_storage); + + if (!data_is_valid_bct(context)) + return -ENODATA; + + return err; +} + +/* + * Update the next_bct_blk and make it point to the next + * new blank block according to bct_copy given. + * + * @param context The main context pointer + */ +static void +find_new_bct_blk(build_image_context *context) +{ + uint32_t max_bct_search_blks; + + assert(context); + + g_soc_config->get_value(token_max_bct_search_blks, + &max_bct_search_blks, context->bct); + + if (context->next_bct_blk > max_bct_search_blks) { + printf("Error: Unable to locate a journal block.\n"); + exit(1); + } + context->next_bct_blk++; +} + +/* + * Initialization before bct and bootloader update. + * Find the new blank block and erase it. + * + * @param context The main context pointer + * @return 0 for success + */ +int +begin_update(build_image_context *context) +{ + uint32_t hash_size; + uint32_t reserved_size; + uint32_t reserved_offset; + int err = 0; + int i; + + assert(context); + + /* Ensure that the BCT block & page data is current. */ + if (enable_debug) { + uint32_t block_size_log2; + uint32_t page_size_log2; + + g_soc_config->get_value(token_block_size_log2, + &block_size_log2, context->bct); + g_soc_config->get_value(token_page_size_log2, + &page_size_log2, context->bct); + + printf("begin_update(): bct data: b=%d p=%d\n", + block_size_log2, page_size_log2); + } + + g_soc_config->set_value(token_boot_data_version, + &(context->boot_data_version), context->bct); + g_soc_config->get_value(token_hash_size, + &hash_size, context->bct); + g_soc_config->get_value(token_reserved_size, + &reserved_size, context->bct); + g_soc_config->get_value(token_reserved_offset, + &reserved_offset, context->bct); + /* Set the odm data */ + g_soc_config->set_value(token_odm_data, + &(context->odm_data), context->bct); + + /* Initialize the bad block table field. */ + g_soc_config->init_bad_block_table(context); + /* Fill the reserved data w/the padding pattern. */ + write_padding(context->bct + reserved_offset, reserved_size); + + /* Create the pad before the BCT starting at block 1 */ + for (i = 0; i < context->pre_bct_pad_blocks; i++) { + find_new_bct_blk(context); + err = erase_block(context, i); + if (err != 0) + goto fail; + } + /* Find the next bct block starting at block pre_bct_pad_blocks. */ + for (i = 0; i < context->bct_copy; i++) { + find_new_bct_blk(context); + err = erase_block(context, i + context->pre_bct_pad_blocks); + if (err != 0) + goto fail; + } + return 0; +fail: + printf("Erase block failed, error: %d.\n", err); + return err; +} + +/* + * Write the BCT(s) starting at slot 0 of block context->pre_bct_pad_blocks. + * + * @param context The main context pointer + * @return 0 for success + */ +static int +finish_update(build_image_context *context) +{ + int err = 0; + int i; + + for (i = 0; i < context->bct_copy; i++) { + err = write_bct(context, i + context->pre_bct_pad_blocks, 0); + if (err != 0) + goto fail; + } + + return 0; +fail: + printf("Write BCT failed, error: %d.\n", err); + return err; +} + +/* + * For now, ignore end state. + */ +int +update_bl(build_image_context *context) +{ + if (enable_debug) + printf("**update_bl()\n"); + + if (begin_update(context) != 0) + return 1; + if (write_image(context, file_type_bl) != 0) + return 1; + if (finish_update(context) != 0) + return 1; + return 0; +} + +int +update_mts_image(build_image_context *context) +{ + if (enable_debug) + printf("**update_mts()\n"); + + if (begin_update(context) != 0) + return 1; + if (write_image(context, file_type_mts) != 0) + return 1; + if (finish_update(context) != 0) + return 1; + return 0; +} + +/* + * To write the current image: + * Loop over all blocks in the block data list: + * Write out the data of real blocks. + * Write out 0's for unused blocks. + * Stop on the last used page of the last used block. + * + * @param context The main context pointer + * @return 0 for success + */ +int +write_block_raw(build_image_context *context) +{ + block_data *block_list; + block_data *block; + uint32_t blk_number; + uint32_t last_blk; + uint32_t pages_to_write; + uint8_t *data; + uint8_t *empty_blk = NULL; + + assert(context != NULL); + assert(context->memory); + + block_list = context->memory; + + /* Compute the end of the image. */ + block_list = context->memory; + while (block_list->next) + block_list = block_list->next; + + last_blk = block_list->blk_number; + + /* Loop over all the storage from block 0, page 0 to + *last_blk, Lastpage + */ + for (blk_number = 0; blk_number <= last_blk; blk_number++) { + block = find_block(blk_number, context->memory); + if (block) { + pages_to_write = (blk_number == last_blk) ? + block->pages_used : + context->pages_per_blk; + data = block->data; + } else { + /* Allocate empty_blk if needed. */ + if (empty_blk == NULL) { + empty_blk = malloc(context->block_size); + if (!empty_blk) + return -ENOMEM; + memset(empty_blk, 0, context->block_size); + } + pages_to_write = context->pages_per_blk; + data = empty_blk; + } + /* Write the data */ + { + size_t bytes = pages_to_write * context->page_size; + + if (fwrite(data, 1, bytes, context->raw_file) != bytes) { + if (empty_blk) free(empty_blk); + return -1; + } + } + } + + if (empty_blk) free(empty_blk); + return 0; +} + +int write_data_block(FILE *fp, uint32_t offset, uint32_t size, uint8_t *buffer) +{ + if (fseek(fp, offset, 0)) + return -1; + + return fwrite(buffer, 1, size, fp); +} + +int data_is_valid_bct(build_image_context *context) +{ + /* get proper soc_config pointer by polling each supported chip */ + if (if_bct_is_t20_get_soc_config(context, &g_soc_config)) + return 1; + if (if_bct_is_t30_get_soc_config(context, &g_soc_config)) + return 1; + if (if_bct_is_t114_get_soc_config(context, &g_soc_config)) + return 1; + if (if_bct_is_t124_get_soc_config(context, &g_soc_config)) + return 1; + if (if_bct_is_t132_get_soc_config(context, &g_soc_config)) + return 1; + if (if_bct_is_t210_get_soc_config(context, &g_soc_config)) + return 1; + + return 0; +} + +int get_bct_size_from_image(build_image_context *context) +{ + uint8_t buffer[NVBOOT_CONFIG_TABLE_SIZE_MIN]; + uint32_t bct_size = 0; + FILE *fp; + + fp = fopen(context->input_image_filename, "r"); + if (!fp) + return -ENODATA; + + if (fread(buffer, 1, NVBOOT_CONFIG_TABLE_SIZE_MIN, fp) != NVBOOT_CONFIG_TABLE_SIZE_MIN) { + fclose(fp); + return -ENODATA; + } + + context->bct = buffer; + if (data_is_valid_bct(context) && g_soc_config->get_bct_size) + bct_size = g_soc_config->get_bct_size(); + + fclose(fp); + context->bct = 0; + return bct_size; +} + +int resign_bl(build_image_context *context) +{ + int ret; + uint8_t *buffer, *image; + uint32_t image_instance = 0; /* support only one instance */ + uint32_t image_actual_size; /* In bytes */ + uint32_t bl_length; + uint32_t pages_in_image; + uint32_t blk_size, page_size, current_blk, current_page; + uint32_t offset; + + /* read in bl from image */ + g_soc_config->get_value(token_block_size, &blk_size, context->bct); + g_soc_config->get_value(token_page_size, &page_size, context->bct); + + GET_BL_FIELD(image_instance, start_blk, ¤t_blk); + GET_BL_FIELD(image_instance, start_page, ¤t_page); + GET_BL_FIELD(image_instance, length, &bl_length); + + offset = current_blk * blk_size + + current_page * page_size; + + if (read_from_image(context->input_image_filename, + offset, bl_length, + &image, &image_actual_size, file_type_bin)) { + printf("Error reading image file %s.\n", + context->input_image_filename); + return -ENOMEM; + } + + pages_in_image = ICEIL(image_actual_size, page_size); + + /* Create a local copy of the bl */ + if ((buffer = malloc(pages_in_image * page_size)) == NULL) { + ret = -ENOMEM; + goto fail; + } + + memset(buffer, 0, pages_in_image * page_size); + memcpy(buffer, image, image_actual_size); + + insert_padding(buffer, image_actual_size); + + /* sign bl */ + ret = sign_bl(context, buffer, image_actual_size, image_instance); + free (buffer); + fail: + free (image); + return ret; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/data_layout.h b/firmware/coreboot/util/nvidia/cbootimage/src/data_layout.h new file mode 100644 index 0000000000..90b0410bab --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/data_layout.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * data_layout.h - Definitions for the cbootimage data layout code. + */ + +#ifndef INCLUDED_DATA_LAYOUT_H +#define INCLUDED_DATA_LAYOUT_H + +#include "cbootimage.h" + +/* Foward declarations */ +struct build_image_context_rec; + +typedef struct blk_data_rec *blk_data_handle; + +blk_data_handle new_block_list(void); +void destroy_block_list(blk_data_handle); + +int +update_bl(struct build_image_context_rec *context); + +int +update_mts_image(build_image_context *context); + +void +update_context(struct build_image_context_rec *context); + +int +read_bct_file(struct build_image_context_rec *context); + +int +init_bct(struct build_image_context_rec *context); + +int +write_block_raw(struct build_image_context_rec *context); + +int +write_data_block(FILE *fp, uint32_t offset, uint32_t size, uint8_t *buffer); + +int +data_is_valid_bct(build_image_context *context); + +int +get_bct_size_from_image(build_image_context *context); + +int +begin_update(build_image_context *context); + +int +resign_bl(build_image_context *context); +#endif /* #ifndef INCLUDED_DATA_LAYOUT_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/nvaes_ref.h b/firmware/coreboot/util/nvidia/cbootimage/src/nvaes_ref.h new file mode 100644 index 0000000000..00fc6e05e8 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/nvaes_ref.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include "cbootimage.h" +#include "string.h" + +#ifndef INCLUDED_NVAES_REF_H +#define INCLUDED_NVAES_REF_H + +#define NVAES_STATECOLS 4 +#define NVAES_KEYCOLS 4 +#define NVAES_ROUNDS 10 + +void nv_aes_expand_key(uint8_t *key, uint8_t *expkey); +void nv_aes_encrypt(uint8_t *in, + uint8_t *expkey, + uint8_t *out); + +#endif // INCLUDED_NVAES_REF_H diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/parse.c b/firmware/coreboot/util/nvidia/cbootimage/src/parse.c new file mode 100644 index 0000000000..99cb428b26 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/parse.c @@ -0,0 +1,990 @@ +/* + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * parse.c - Parsing support for the cbootimage tool + */ + +#include +#include "parse.h" +#include "cbootimage.h" +#include "data_layout.h" +#include "crypto.h" +#include "set.h" + +/* + * Function prototypes + * + * ParseXXX() parses XXX in the input + * SetXXX() sets state based on the parsing results but does not perform + * any parsing of its own + * A ParseXXX() function may call other parse functions and set functions. + * A SetXXX() function may not call any parseing functions. + */ + +static int +set_array(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); +static char *parse_u32(char *str, uint32_t *val); +static char *parse_u8(char *str, uint32_t *val); +static char *parse_chipuid(char *str, uint8_t *val); +static char *parse_filename(char *str, char *name, int chars_remaining); +static char *parse_enum(build_image_context *context, + char *str, + enum_item *table, + uint32_t *val); +static char +*parse_field_name(char *rest, field_item *field_table, field_item **field); +static char +*parse_field_value(build_image_context *context, + char *rest, + field_item *field, + uint32_t *value); +static int +parse_array(build_image_context *context, parse_token token, char *rest); +static int +parse_bootloader(build_image_context *context, parse_token token, char *rest); +static int +parse_mts_image(build_image_context *context, parse_token token, char *rest); +static int +parse_rsa_param(build_image_context *context, parse_token token, char *rest); +static int +parse_value_u32(build_image_context *context, parse_token token, char *rest); +static int +parse_value_chipuid(build_image_context *context, + parse_token token, + char *rest); +static int +parse_bct_file(build_image_context *context, parse_token token, char *rest); +static char +*parse_end_state(char *str, char *uname, int chars_remaining); +static int +parse_dev_param(build_image_context *context, parse_token token, char *rest); +static int +parse_sdram_param(build_image_context *context, parse_token token, char *rest); +static int +parse_sign_bl(build_image_context *context, parse_token token, char *rest); + +static int process_statement(build_image_context *context, + char *str, + uint8_t simple_parse); + +static parse_item parse_simple_items[] = +{ + { "Bctfile=", token_bct_file, parse_bct_file }, + { "BootLoader=", token_bootloader, parse_bootloader }, + { "Redundancy=", token_redundancy, parse_value_u32 }, + { "Bctcopy=", token_bct_copy, parse_value_u32 }, + { "MtsPreboot=", token_mts_preboot, parse_mts_image}, + { "Mts=", token_mts, parse_mts_image}, + { "Version=", token_version, parse_value_u32 }, + { "PreBctPadBlocks=", token_pre_bct_pad_blocks, parse_value_u32 }, + { NULL, 0, NULL } /* Must be last */ +}; + +static parse_item s_top_level_items[] = { + { "Bctfile=", token_bct_file, parse_bct_file }, + { "Attribute=", token_attribute, parse_value_u32 }, + { "Attribute[", token_attribute, parse_array }, + { "PageSize=", token_page_size, parse_value_u32 }, + { "BlockSize=", token_block_size, parse_value_u32 }, + { "PartitionSize=", token_partition_size, parse_value_u32 }, + { "DevType[", token_dev_type, parse_array }, + { "DeviceParam[", token_dev_param, parse_dev_param }, + { "SDRAM[", token_sdram, parse_sdram_param }, + { "BootLoader=", token_bootloader, parse_bootloader }, + { "Redundancy=", token_redundancy, parse_value_u32 }, + { "Bctcopy=", token_bct_copy, parse_value_u32 }, + { "MtsPreboot=", token_mts_preboot, parse_mts_image}, + { "Mts=", token_mts, parse_mts_image}, + { "Version=", token_version, parse_value_u32 }, + { "OdmData=", token_odm_data, parse_value_u32 }, + { "ChipUid=", token_unique_chip_id, parse_value_chipuid }, + { "JtagCtrl=", token_secure_jtag_control, parse_value_u32 }, + { "DebugCtrl=", token_secure_debug_control, parse_value_u32 }, + { "RsaKeyModulusFile=", token_rsa_key_modulus, parse_rsa_param }, + { "RsaPssSigBlFile=", token_rsa_pss_sig_bl, parse_rsa_param }, + { "RsaPssSigBctFile=", token_rsa_pss_sig_bct, parse_rsa_param }, + { "RehashBl", token_sign_bl, parse_sign_bl }, + { NULL, 0, NULL } /* Must be last */ +}; + +/* Macro to simplify parser code a bit. */ +#define PARSE_COMMA(x) if (*rest != ',') return (x); rest++ + +/* + * Parse the given string and find the u32 dec/hex number. + * + * @param str String to parse + * @param val Returns value that was parsed + * @return the remainder of the string after the number was parsed + */ +static char * +parse_u32(char *str, uint32_t *val) +{ + uint32_t value = 0; + uint32_t digit; + + while (*str == '0') + str++; + + if (tolower(*str) == 'x') { + str++; + while (isxdigit(*str)) { + value *= 16; + digit = tolower(*str); + value += digit <= '9' ? digit - '0' : digit - 'a' + 10; + str++; + } + } else { + while (*str >= '0' && *str <= '9') { + value = value*10 + (*str - '0'); + str++; + } + } + *val = value; + return str; +} + +/* + * Parse the given string and find the u8 dec/hex number. + * + * @param str String to parse + * @param val Returns value that was parsed + * @return the remainder of the string after the number was parsed + */ +static char * +parse_u8(char *str, uint32_t *val) +{ + char *retval; + + retval = parse_u32(str, val); + + if (*val > 0xff) { + printf("Warning: Parsed 8-bit value that exceeded 8-bits.\n"); + printf(" Parsed value = %d. Remaining text = %s\n", + *val, retval); + } + + return retval; +} + +/* + * Parse the given string and transfer to chip uid. + * + * @param str String to parse + * @param chipuid Returns chip uid that was parsed + * @return the remainder of the string after the number was parsed + */ +static char * +parse_chipuid(char *str, uint8_t *chipuid) +{ + int byte_index = 0; + int paddings = 0; + char byte_str[3]; + + if (*str++ != '0') + return NULL; + + if (*str++ != 'x') + return NULL; + + paddings = strlen(str) % 2; + byte_index = strlen(str) / 2 + paddings; + + if (byte_index > 16) + return NULL; + + memset(chipuid, 0, 16); + + while (*str != '\0' && byte_index > 0) { + char *endptr; + + strncpy(byte_str, str, 2 - paddings); + byte_str[2 - paddings] = '\0'; + str += 2 - paddings; + + chipuid[byte_index - 1] = strtoul(byte_str, &endptr, 16); + if (*endptr) + return NULL; + + byte_index--; + paddings = 0; + } + + return str; +} + +/* + * Parse the given string and find the file name then + * return the rest of the string. + * + * @param str String to parse + * @param name Returns the filename that was parsed + * @param chars_remaining The maximum length of filename + * @return the remainder of the string after the name was parsed + */ +static char * +parse_filename(char *str, char *name, int chars_remaining) +{ + /* + * Check if the filename buffer is out of space, preserving one + * character to null terminate the string. + */ + while (isalnum(*str) || strchr("\\/~_-+:.@", *str)) { + + chars_remaining--; + + if (chars_remaining < 1) + return NULL; + *name++ = *str++; + } + + /* Null terminate the filename. */ + *name = '\0'; + + return str; +} + +/* + * Parse the given string and find the match field name listed + * in field table. + * + * @param rest String to parse + * @param field_table The field table to parse + * @param field Returns the field item that was parsed + * @return NULL or the remainder of the string after the field item was parsed + */ +static char +*parse_field_name(char *rest, field_item *field_table, field_item **field) +{ + uint32_t i; + uint32_t field_name_len = 0; + + assert(field_table != NULL); + assert(rest != NULL); + assert(field != NULL); + + while (rest[field_name_len] != '=') + field_name_len++; + + /* Parse the field name. */ + for (i = 0; field_table[i].name != NULL; i++) { + if ((strlen(field_table[i].name) == field_name_len) && + !strncmp(field_table[i].name, + rest, + field_name_len)) { + + *field = &(field_table[i]); + rest = rest + field_name_len; + return rest; + } + } + + /* Field wasn't found or a parse error occurred. */ + return NULL; +} + +/* + * Parse the value based on the field table + * + * @param context The main context pointer + * @param rest String to parse + * @param field Field item to parse + * @param value Returns the value that was parsed + * @return the remainder of the string after the value was parsed + */ +static char +*parse_field_value(build_image_context *context, + char *rest, + field_item *field, + uint32_t *value) +{ + assert(rest != NULL); + assert(field != NULL); + assert((field->type != field_type_enum) + || (field->enum_table != NULL)); + + switch (field->type) { + case field_type_enum: + rest = parse_enum(context, rest, field->enum_table, value); + break; + + case field_type_u32: + rest = parse_u32(rest, value); + break; + + case field_type_u8: + rest = parse_u8(rest, value); + break; + + default: + printf("Unexpected field type %d at line %d\n", + field->type, __LINE__); + rest = NULL; + break; + } + + return rest; +} + +/* + * Parse the given string and find the match enum item listed + * in table. + * + * @param context The main context pointer + * @param str String to parse + * @param table Enum item table to parse + * @param value Returns the value that was parsed + * @return the remainder of the string after the item was parsed + */ +static char * +parse_enum(build_image_context *context, + char *str, + enum_item *table, + uint32_t *val) +{ + int i; + char *rest; + + for (i = 0; table[i].name != NULL; i++) { + if (!strncmp(table[i].name, str, + strlen(table[i].name))) { + *val = table[i].value; + rest = str + strlen(table[i].name); + return rest; + } + } + return parse_u32(str, val); + +} + +/* + * Parse the given string and find the bootloader file name, load address and + * entry point information then call set_bootloader function. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ +static int parse_bootloader(build_image_context *context, + parse_token token, + char *rest) +{ + char filename[MAX_BUFFER]; + char e_state[MAX_STR_LEN]; + uint32_t load_addr; + uint32_t entry_point; + + assert(context != NULL); + assert(rest != NULL); + + if (context->generate_bct != 0) + return 0; + /* Parse the file name. */ + rest = parse_filename(rest, filename, MAX_BUFFER); + if (rest == NULL) + return 1; + + PARSE_COMMA(1); + + /* Parse the load address. */ + rest = parse_u32(rest, &load_addr); + if (rest == NULL) + return 1; + + PARSE_COMMA(1); + + /* Parse the entry point. */ + rest = parse_u32(rest, &entry_point); + if (rest == NULL) + return 1; + + PARSE_COMMA(1); + + /* Parse the end state. */ + rest = parse_end_state(rest, e_state, MAX_STR_LEN); + if (rest == NULL) + return 1; + if (strncmp(e_state, "Complete", strlen("Complete"))) + return 1; + + /* Parsing has finished - set the bootloader */ + return set_bootloader(context, filename, load_addr, entry_point); +} + +/* + * Parse the given string and find the MTS file name, load address and + * entry point information then call set_mts_image function. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ +static int parse_mts_image(build_image_context *context, + parse_token token, + char *rest) +{ + char filename[MAX_BUFFER]; + char e_state[MAX_STR_LEN]; + uint32_t load_addr; + uint32_t entry_point; + + assert(context != NULL); + assert(rest != NULL); + + if (context->generate_bct != 0) + return 0; + /* Parse the file name. */ + rest = parse_filename(rest, filename, MAX_BUFFER); + if (rest == NULL) + return 1; + + PARSE_COMMA(1); + + /* Parse the load address. */ + rest = parse_u32(rest, &load_addr); + if (rest == NULL) + return 1; + + PARSE_COMMA(1); + + /* Parse the entry point. */ + rest = parse_u32(rest, &entry_point); + if (rest == NULL) + return 1; + + PARSE_COMMA(1); + + /* Parse the end state. */ + rest = parse_end_state(rest, e_state, MAX_STR_LEN); + if (rest == NULL) + return 1; + if (strncmp(e_state, "Complete", strlen("Complete"))) + return 1; + + /* Parsing has finished - set the bootloader */ + return set_mts_image(context, filename, load_addr, entry_point); +} + +/* + * Parse the given rsa modulus/key/signature file name + * then call set_rsa_settings to set proper rsa field. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ +static int parse_rsa_param(build_image_context *context, + parse_token token, + char *rest) +{ + char filename[MAX_BUFFER]; + + assert(context != NULL); + assert(rest != NULL); + + if (context->generate_bct != 0) + return 0; + + /* Parse the file name. */ + rest = parse_filename(rest, filename, MAX_BUFFER); + if (rest == NULL) + return 1; + + /* Parsing has finished - set the bootloader */ + return set_rsa_param(context, token, filename); +} + +/* + * Parse the given string and find the array items in config file. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ +static int +parse_array(build_image_context *context, parse_token token, char *rest) +{ + uint32_t index; + uint32_t value; + + assert(context != NULL); + assert(rest != NULL); + + /* Parse the index. */ + rest = parse_u32(rest, &index); + if (rest == NULL) + return 1; + + /* Parse the closing bracket. */ + if (*rest != ']') + return 1; + rest++; + + /* Parse the equals sign.*/ + if (*rest != '=') + return 1; + rest++; + + /* Parse the value based on the field table. */ + switch (token) { + case token_attribute: + rest = parse_u32(rest, &value); + break; + case token_dev_type: + rest = parse_enum(context, + rest, + g_soc_config->devtype_table, + &value); + break; + + default: + /* Unknown token */ + return 1; + } + + if (rest == NULL) + return 1; + + /* Store the result. */ + return set_array(context, index, token, value); +} + +/* + * Call hw interface to set the value for array item in bct such as device + * type and bootloader attribute. + * + * @param context The main context pointer + * @param index The index for array + * @param token The parse token value + * @param value The value to set + * @return 0 and -ENODATA for success and failure + */ + +static int +set_array(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + int err = 0; + + assert(context != NULL); + + switch (token) { + case token_attribute: + err = g_soc_config->setbl_param(index, + token_bl_attribute, + &value, + context->bct); + break; + case token_dev_type: + err = g_soc_config->set_dev_param(context, + index, + token_dev_type, + value); + break; + default: + break; + } + return err; +} + +/* + * General handler for setting uint32_t values in config files. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ +static int parse_value_u32(build_image_context *context, + parse_token token, + char *rest) +{ + uint32_t value; + + assert(context != NULL); + assert(rest != NULL); + + rest = parse_u32(rest, &value); + if (rest == NULL) + return 1; + + return context_set_value(context, token, &value); +} + +/* + * General handler for setting chip uid in config files. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ +static int parse_value_chipuid(build_image_context *context, + parse_token token, + char *rest) +{ + uint8_t value[16]; + + assert(context != NULL); + assert(rest != NULL); + + rest = parse_chipuid(rest, value); + if (rest == NULL) + return 1; + + return context_set_value(context, token, value); +} + +/* + * Parse the given string and find the bct file name. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ +static int +parse_bct_file(build_image_context *context, parse_token token, char *rest) +{ + char filename[MAX_BUFFER]; + + assert(context != NULL); + assert(rest != NULL); + + /* Parse the file name. */ + rest = parse_filename(rest, filename, MAX_BUFFER); + if (rest == NULL) + return 1; + + /* Parsing has finished - set the bctfile */ + context->bct_filename = filename; + /* Read the bct file to buffer */ + if (read_bct_file(context)) + return 1; + + update_context(context); + return 0; +} + +static int +parse_sign_bl(build_image_context *context, parse_token token, char *rest) +{ + return resign_bl(context); +} + +static char * +parse_end_state(char *str, char *uname, int chars_remaining) +{ + while (isalpha(*str)) { + + *uname++ = *str++; + if (--chars_remaining < 0) + return NULL; + } + *uname = '\0'; + return str; +} + +/* + * Parse the given string and find device parameter listed in device table + * and value for this device parameter. If match, call the corresponding + * function in the table to set device parameter. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ +static int +parse_dev_param(build_image_context *context, parse_token token, char *rest) +{ + uint32_t i; + uint32_t value; + field_item *field; + uint32_t index; + parse_subfield_item *device_item = NULL; + + assert(context != NULL); + assert(rest != NULL); + + /* Parse the index. */ + rest = parse_u32(rest, &index); + if (rest == NULL) + return 1; + + /* Parse the closing bracket. */ + if (*rest != ']') + return 1; + rest++; + + /* Parse the following '.' */ + if (*rest != '.') + return 1; + rest++; + + /* Parse the device name. */ + for (i = 0; g_soc_config->device_type_table[i].prefix != NULL; i++) { + if (!strncmp(g_soc_config->device_type_table[i].prefix, + rest, strlen(g_soc_config->device_type_table[i].prefix))) { + + device_item = &(g_soc_config->device_type_table[i]); + rest = rest + strlen(g_soc_config->device_type_table[i].prefix); + + /* Parse the field name. */ + rest = parse_field_name(rest, + g_soc_config->device_type_table[i].field_table, + &field); + if (rest == NULL) + return 1; + + /* Parse the equals sign.*/ + if (*rest != '=') + return 1; + rest++; + + /* Parse the value based on the field table. */ + rest = parse_field_value(context, rest, field, &value); + if (rest == NULL) + return 1; + return device_item->process(context, + index, field->token, value); + } + } + return 1; +} + +/* + * Parse the given string and find sdram parameter and value in config + * file. If match, call the corresponding function set the sdram parameter. + * + * @param context The main context pointer + * @param token The parse token value + * @param rest String to parse + * @return 0 and 1 for success and failure + */ +static int +parse_sdram_param(build_image_context *context, parse_token token, char *rest) +{ + uint32_t value; + field_item *field; + uint32_t index; + + assert(context != NULL); + assert(rest != NULL); + + /* Parse the index. */ + rest = parse_u32(rest, &index); + if (rest == NULL) + return 1; + + /* Parse the closing bracket. */ + if (*rest != ']') + return 1; + rest++; + + /* Parse the following '.' */ + if (*rest != '.') + return 1; + rest++; + + /* Parse the field name. */ + rest = parse_field_name(rest, g_soc_config->sdram_field_table, &field); + + if (rest == NULL) + return 1; + + /* Parse the equals sign.*/ + if (*rest != '=') + return 1; + rest++; + + /* Parse the value based on the field table. */ + rest = parse_field_value(context, rest, field, &value); + if (rest == NULL) + return 1; + + /* Store the result. */ + return g_soc_config->set_sdram_param(context, + index, + field->token, + value); +} + +/* + * Compare the given string with item listed in table. + * Execute the proper process function if match. + * + * @param context The main context pointer + * @param str String to parse + * @param simple_parse Simple parse flag + * @return 0 and 1 for success and failure + */ +static int +process_statement(build_image_context *context, + char *str, + uint8_t simple_parse) +{ + int i; + char *rest; + parse_item *cfg_parse_item; + + if (simple_parse == 0) + cfg_parse_item = s_top_level_items; + else + cfg_parse_item = parse_simple_items; + + for (i = 0; cfg_parse_item[i].prefix != NULL; i++) { + if (!strncmp(cfg_parse_item[i].prefix, str, + strlen(cfg_parse_item[i].prefix))) { + rest = str + strlen(cfg_parse_item[i].prefix); + + return cfg_parse_item[i].process(context, + cfg_parse_item[i].token, + rest); + } + } + + /* If this point was reached, there was a processing error. */ + return 1; +} + +/* + * The main function parse the config file. + * + * @param context The main context pointer + * @param simple_parse Simple parse flag + */ +void process_config_file(build_image_context *context, uint8_t simple_parse) +{ + char buffer[MAX_BUFFER]; + int space = 0; + int current; + uint8_t c_eol_comment_start = 0; /* True after first slash */ + uint8_t comment = 0; + uint8_t string = 0; + uint8_t equal_encounter = 0; + + assert(context != NULL); + assert(context->config_file != NULL); + + while ((current = fgetc(context->config_file)) != EOF) { + if (space >= (MAX_BUFFER-1)) { + /* if we exceeded the max buffer size, it is likely + due to a missing semi-colon at the end of a line */ + printf("Config file parsing error!"); + exit(1); + } + + /* Handle failure to complete "//" comment token. + Insert the '/' into the busffer and proceed with + processing the current character. */ + if (c_eol_comment_start && current != '/') { + c_eol_comment_start = 0; + buffer[space++] = '/'; + } + + switch (current) { + case '\"': /* " indicates start or end of a string */ + if (!comment) { + string ^= 1; + buffer[space++] = current; + } + break; + case ';': + if (!string && !comment) { + buffer[space++] = '\0'; + + if (process_statement(context, + buffer, + simple_parse)) + goto error; + space = 0; + equal_encounter = 0; + } else if (string) + buffer[space++] = current; + break; + + case '/': + if (!string && !comment) { + if (c_eol_comment_start) { + /* EOL comment started. */ + comment = 1; + c_eol_comment_start = 0; + } else { + /* Potential start of eol comment. */ + c_eol_comment_start = 1; + } + } else if (!comment) + buffer[space++] = current; + break; + + /* ignore whitespace. uses fallthrough */ + case '\n': + case '\r': /* carriage returns end comments */ + string = 0; + comment = 0; + c_eol_comment_start = 0; + case ' ': + case '\t': + if (string) + buffer[space++] = current; + break; + + case '#': + if (!string) + comment = 1; + else + buffer[space++] = current; + break; + + default: + if (!comment) { + buffer[space++] = current; + if (current == '=') { + if (!equal_encounter) + equal_encounter = 1; + else + goto error; + } + } + break; + } + } + + return; + + error: + printf("Error parsing: %s\n", buffer); + exit(1); +} + +int bct_get_unsupported(parse_token id) +{ + return -ENODATA; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/parse.h b/firmware/coreboot/util/nvidia/cbootimage/src/parse.h new file mode 100644 index 0000000000..d53cfbcaa7 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/parse.h @@ -0,0 +1,1423 @@ +/* + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * parse.h - Definitions for the cbootimage parsing code. + */ + +/* + * TODO / Notes + * - Add doxygen commentary + */ + +#ifndef INCLUDED_PARSE_H +#define INCLUDED_PARSE_H + +#include "cbootimage.h" + + +/* + * Enums + */ + +typedef enum +{ + token_none = 0, + token_attribute, + token_bootloader, + token_mts_preboot, + token_mts, + token_block_size, + token_page_size, + token_partition_size, + token_dev_type, + token_dev_param, + token_redundancy, + token_version, + token_odm_data, + token_bct_file, + token_bct_copy, + token_bct_size, + token_nand_params, + token_sdmmc_params, + token_spiflash_params, + token_data_width, + token_clock_divider, + token_clock_source, + token_read_command_type_fast, + token_max_power_class_supported, + token_sd_controller, + token_nand_timing2, + token_nand_timing, + token_block_size_log2, + token_page_size_log2, + token_nand_async_timing0, + token_nand_async_timing1, + token_nand_async_timing2, + token_nand_async_timing3, + token_nand_sddr_timing0, + token_nand_sddr_timing1, + token_nand_tddr_timing0, + token_nand_tddr_timing1, + token_nand_fbio_dqsib_dly_byte, + token_nand_fbio_quse_dly_byte, + token_nand_fbio_cfg_quse_late, + token_async_timing0, + token_async_timing1, + token_async_timing2, + token_async_timing3, + token_sddr_timing0, + token_sddr_timing1, + token_tddr_timing0, + token_tddr_timing1, + token_fbio_dqsib_dly_byte, + token_fbio_quse_dly_byte, + token_fbio_cfg_quse_late, + token_disable_sync_ddr, + token_nand_disable_sync_ddr, + token_sdram, + token_crypto_hash, + token_random_aes_blk, + token_boot_data_version, + token_bootloader_used, + token_bootloaders_max, + token_reserved, + token_reserved_size, + token_reserved_offset, + token_hash_size, + token_crypto_offset, + token_crypto_length, + token_max_bct_search_blks, + token_num_param_sets, + token_dev_type_nand, + token_dev_type_sdmmc, + token_dev_type_spi, + token_num_sdram_sets, + token_pre_bct_pad_blocks, + token_unique_chip_id, + token_secure_jtag_control, + token_secure_debug_control, + + token_rsa_key_modulus, + token_rsa_pss_sig_bl, + token_rsa_pss_sig_bct, + token_sign_bl, + + token_nand_clock_divider, + token_nand_nand_timing, + token_nand_nand_timing2, + token_nand_block_size_log2, + token_nand_page_size_log2, + token_sdmmc_clock_divider, + token_sdmmc_data_width, + token_sdmmc_multi_page_support, + token_sdmmc_sd_controller, + token_sdmmc_max_power_class_supported, + token_spiflash_read_command_type_fast, + token_spiflash_page_size_2k_or_16k, + token_spiflash_clock_source, + token_spiflash_clock_divider, + token_sdmmc_data_width_4bit, + token_sdmmc_data_width_8bit, + token_spi_clock_source_pllp_out0, + token_spi_clock_source_pllc_out0, + token_spi_clock_source_pllm_out0, + token_spi_clock_source_clockm, + token_memory_type_none, + token_memory_type_ddr, + token_memory_type_lpddr, + token_memory_type_ddr2, + token_memory_type_lpddr2, + token_memory_type_ddr3, + token_memory_type_lpddr4, + + token_bl_version, + token_bl_start_blk, + token_bl_start_page, + token_bl_length, + token_bl_load_addr, + token_bl_entry_point, + token_bl_attribute, + token_bl_crypto_hash, + + token_memory_type, + token_pllm_charge_pump_setup_ctrl, + token_pllm_loop_filter_setup_ctrl, + token_pllm_input_divider, + token_pllm_feedback_divider, + token_pllm_post_divider, + token_pllm_stable_time, + token_pllm_setup_control, + token_pllm_select_div2, + token_pllm_pdlshift_ph45, + token_pllm_pdlshift_ph90, + token_pllm_pdlshift_ph135, + token_pllm_kcp, + token_pllm_kvco, + token_emc_bct_spare0, + token_emc_bct_spare1, + token_emc_bct_spare2, + token_emc_bct_spare3, + token_emc_bct_spare4, + token_emc_bct_spare5, + token_emc_bct_spare6, + token_emc_bct_spare7, + token_emc_bct_spare8, + token_emc_bct_spare9, + token_emc_bct_spare10, + token_emc_bct_spare11, + token_emc_bct_spare12, + token_emc_bct_spare13, + token_emc_clock_divider, + token_emc_auto_cal_interval, + token_emc_auto_cal_config, + token_emc_auto_cal_config2, + token_emc_auto_cal_config3, + token_emc_auto_cal_wait, + + token_emc_xm2_comp_pad_ctrl, + token_emc_xm2_comp_pad_ctrl2, + token_emc_xm2_comp_pad_ctrl3, + + token_emc_pin_program_wait, + token_emc_rc, + token_emc_rfc, + + token_emc_rfc_pb, + token_emc_ref_ctrl2, + + token_emc_rfc_slr, + token_emc_ras, + token_emc_rp, + token_emc_r2r, + token_emc_w2w, + token_emc_r2w, + token_emc_w2r, + token_emc_r2p, + token_emc_w2p, + + token_emc_tppd, + token_emc_ccdmw, + + token_emc_rd_rcd, + token_emc_wr_rcd, + token_emc_rrd, + token_emc_rext, + token_emc_wdv, + + token_emc_wdv_chk, + token_emc_wsv, + token_emc_wev, + + token_emc_wdv_mask, + + token_emc_ws_duration, + token_emc_we_duration, + + token_emc_quse, + token_emc_quse_width, + token_emc_ibdly, + + token_emc_obdly, + + token_emc_einput, + token_emc_einput_duration, + token_emc_puterm_extra, + token_emc_puterm_width, + token_emc_puterm_adj, + token_emc_cdb_cntl1, + token_emc_cdb_cntl2, + token_emc_cdb_cntl3, + token_emc_qrst, + token_emc_qsafe, + token_emc_rdv, + token_emc_rdv_mask, + + token_emc_rdv_early, + token_emc_rdv_early_mask, + + token_emc_qpop, + token_emc_refresh, + token_emc_burst_refresh_num, + token_emc_pdex2wr, + token_emc_pdex2rd, + token_emc_pchg2pden, + token_emc_act2pden, + token_emc_ar2pden, + token_emc_rw2pden, + + token_emc_cke2pden, + token_emc_pdex2che, + token_emc_pdex2mrr, + + token_emc_txsr, + token_emc_tcke, + token_emc_tckesr, + token_emc_tpd, + token_emc_tfaw, + token_emc_trpab, + token_emc_tclkstable, + token_emc_tclkstop, + token_emc_trefbw, + token_emc_quse_extra, + token_emc_fbio_cfg5, + token_emc_fbio_cfg6, + + token_emc_fbio_cfg7, + token_emc_fbio_cfg8, + + /* Command mapping for CMD brick 0 */ + token_emc_cmd_mapping_cmd0_0, + token_emc_cmd_mapping_cmd0_1, + token_emc_cmd_mapping_cmd0_2, + token_emc_cmd_mapping_cmd1_0, + token_emc_cmd_mapping_cmd1_1, + token_emc_cmd_mapping_cmd1_2, + token_emc_cmd_mapping_cmd2_0, + token_emc_cmd_mapping_cmd2_1, + token_emc_cmd_mapping_cmd2_2, + token_emc_cmd_mapping_cmd3_0, + token_emc_cmd_mapping_cmd3_1, + token_emc_cmd_mapping_cmd3_2, + token_emc_cmd_mapping_byte, + + token_emc_fbio_spare, + token_emc_mrs, + token_emc_emrs, + token_emc_emrs2, + token_emc_emrs3, + token_emc_mrw1, + token_emc_mrw2, + token_emc_mrw3, + token_emc_mrw4, + + /* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */ + token_emc_mrw6, + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + token_emc_mrw8, + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + token_emc_mrw9, + /* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */ + token_emc_mrw10, + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + token_emc_mrw12, + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + token_emc_mrw13, + /* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */ + token_emc_mrw14, + + token_emc_mrw_reset_command, + token_emc_mrw_reset_ninit_wait, + token_emc_adr_cfg, + token_mc_emem_cfg, + token_emc_cfg, + token_emc_cfg2, + token_emc_cfg_pipe, + + token_emc_cfg_pipe_clk, + token_emc_fdpd_ctrl_cmd_no_ramp, + token_emc_cfg_update, + + token_emc_dbg, + + token_emc_dbg_write_mux, + + token_emc_cfg_dig_dll, + token_emc_cfg_dig_dll_1, + token_emc_cfg_dig_dll_period, + token_warm_boot_wait, + token_emc_ctt_term_ctrl, + token_emc_odt_write, + token_emc_odt_read, + token_emc_zcal_ref_cnt, + token_emc_zcal_wait_cnt, + token_emc_zcal_mrw_cmd, + token_emc_mrs_reset_dll, + token_emc_mrs_reset_dll_wait, + token_emc_emrs_emr2, + token_emc_emrs_emr3, + token_emc_emrs_ddr2_dll_enable, + token_emc_mrs_ddr2_dll_reset, + token_emc_emrs_ddr2_ocd_calib, + token_emc_ddr2_wait, + token_pmc_ddr_pwr, + + token_emc_fbio_cfg1, + token_emc_fbio_dqsib_dly, + token_emc_fbio_dqsib_dly_msb, + token_emc_fbio_quse_dly, + token_emc_fbio_quse_dly_msb, + token_emc_adr_cfg1, + token_mc_lowlatency_config, + token_emc_cfg_clktrim0, + token_emc_cfg_clktrim1, + token_emc_cfg_clktrim2, + token_ahb_arbitration_xbar_ctrl, + token_emc_dll_xform_dqs, + token_emc_dll_xform_quse, + token_emc_mrw_zq_init_dev0, + token_emc_mrw_zq_init_dev1, + token_emc_mrw_zq_init_wait, + token_apb_misc_gp_xm2cfga_pad_ctrl, + token_apb_misc_gp_xm2cfgc_pad_ctrl, + token_apb_misc_gp_xm2cfgc_pad_ctrl2, + token_apb_misc_gp_xm2cfgd_pad_ctrl, + token_apb_misc_gp_xm2cfgd_pad_ctrl2, + token_apb_misc_gp_xm2clkcfg_Pad_ctrl, + token_apb_misc_gp_xm2comp_pad_ctrl, + token_apb_misc_gp_xm2vttgen_pad_ctrl, + + token_emc_clock_source, + + token_emc_clock_source_dll, + token_clk_rst_pllm_misc20_override, + token_clk_rst_pllm_misc20_override_enable, + token_clear_clock2_mc1, + + token_emc_clock_use_pll_mud, + token_emc_pin_extra_wait, + + token_emc_pin_gpio_enable, + token_emc_pin_gpio, + + token_emc_timing_control_wait, + token_emc_wext, + token_emc_ctt, + token_emc_ctt_duration, + token_emc_prerefresh_req_cnt, + token_emc_txsr_dll, + token_emc_cfg_rsv, + token_emc_mrw_extra, + token_emc_warm_boot_mrw1, + token_emc_warm_boot_mrw2, + token_emc_warm_boot_mrw3, + token_emc_warm_boot_mrw_extra, + token_emc_warm_boot_extramode_reg_write_enable, + token_emc_extramode_reg_write_enable, + token_emc_mrs_wait_cnt, + token_emc_mrs_wait_cnt2, + token_emc_cmd_q, + token_emc_mc2emc_q, + token_emc_dyn_self_ref_control, + token_ahb_arbitration_xbar_ctrl_meminit_done, + token_emc_dev_select, + token_emc_sel_dpd_ctrl, + + /* Pads trimmer delays */ + token_emc_fdpd_ctrl_dq, + token_emc_fdpd_ctrl_cmd, + token_emc_pmacro_ib_vref_dq_0, + token_emc_pmacro_ib_vref_dq_1, + token_emc_pmacro_ib_vref_dqs_0, + token_emc_pmacro_ib_vref_dqs_1, + token_emc_pmacro_ib_rxrt, + token_emc_cfg_pipe1, + token_emc_cfg_pipe2, + + /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ + token_emc_pmacro_quse_ddll_rank0_0, + token_emc_pmacro_quse_ddll_rank0_1, + token_emc_pmacro_quse_ddll_rank0_2, + token_emc_pmacro_quse_ddll_rank0_3, + token_emc_pmacro_quse_ddll_rank0_4, + token_emc_pmacro_quse_ddll_rank0_5, + token_emc_pmacro_quse_ddll_rank1_0, + token_emc_pmacro_quse_ddll_rank1_1, + token_emc_pmacro_quse_ddll_rank1_2, + token_emc_pmacro_quse_ddll_rank1_3, + token_emc_pmacro_quse_ddll_rank1_4, + token_emc_pmacro_quse_ddll_rank1_5, + + token_emc_pmacro_ob_ddll_long_dq_rank0_0, + token_emc_pmacro_ob_ddll_long_dq_rank0_1, + token_emc_pmacro_ob_ddll_long_dq_rank0_2, + token_emc_pmacro_ob_ddll_long_dq_rank0_3, + token_emc_pmacro_ob_ddll_long_dq_rank0_4, + token_emc_pmacro_ob_ddll_long_dq_rank0_5, + token_emc_pmacro_ob_ddll_long_dq_rank1_0, + token_emc_pmacro_ob_ddll_long_dq_rank1_1, + token_emc_pmacro_ob_ddll_long_dq_rank1_2, + token_emc_pmacro_ob_ddll_long_dq_rank1_3, + token_emc_pmacro_ob_ddll_long_dq_rank1_4, + token_emc_pmacro_ob_ddll_long_dq_rank1_5, + + token_emc_pmacro_ob_ddll_long_dqs_rank0_0, + token_emc_pmacro_ob_ddll_long_dqs_rank0_1, + token_emc_pmacro_ob_ddll_long_dqs_rank0_2, + token_emc_pmacro_ob_ddll_long_dqs_rank0_3, + token_emc_pmacro_ob_ddll_long_dqs_rank0_4, + token_emc_pmacro_ob_ddll_long_dqs_rank0_5, + token_emc_pmacro_ob_ddll_long_dqs_rank1_0, + token_emc_pmacro_ob_ddll_long_dqs_rank1_1, + token_emc_pmacro_ob_ddll_long_dqs_rank1_2, + token_emc_pmacro_ob_ddll_long_dqs_rank1_3, + token_emc_pmacro_ob_ddll_long_dqs_rank1_4, + token_emc_pmacro_ob_ddll_long_dqs_rank1_5, + + token_emc_pmacro_ib_ddll_long_dqs_rank0_0, + token_emc_pmacro_ib_ddll_long_dqs_rank0_1, + token_emc_pmacro_ib_ddll_long_dqs_rank0_2, + token_emc_pmacro_ib_ddll_long_dqs_rank0_3, + token_emc_pmacro_ib_ddll_long_dqs_rank1_0, + token_emc_pmacro_ib_ddll_long_dqs_rank1_1, + token_emc_pmacro_ib_ddll_long_dqs_rank1_2, + token_emc_pmacro_ib_ddll_long_dqs_rank1_3, + + token_emc_pmacro_ddll_long_cmd_0, + token_emc_pmacro_ddll_long_cmd_1, + token_emc_pmacro_ddll_long_cmd_2, + token_emc_pmacro_ddll_long_cmd_3, + token_emc_pmacro_ddll_long_cmd_4, + token_emc_pmacro_ddll_short_cmd_0, + token_emc_pmacro_ddll_short_cmd_1, + token_emc_pmacro_ddll_short_cmd_2, + + token_emc_dll_xform_dqs0, + token_emc_dll_xform_dqs1, + token_emc_dll_xform_dqs2, + token_emc_dll_xform_dqs3, + token_emc_dll_xform_dqs4, + token_emc_dll_xform_dqs5, + token_emc_dll_xform_dqs6, + token_emc_dll_xform_dqs7, + token_emc_dll_xform_dqs8, + token_emc_dll_xform_dqs9, + token_emc_dll_xform_dqs10, + token_emc_dll_xform_dqs11, + token_emc_dll_xform_dqs12, + token_emc_dll_xform_dqs13, + token_emc_dll_xform_dqs14, + token_emc_dll_xform_dqs15, + token_emc_dll_xform_quse0, + token_emc_dll_xform_quse1, + token_emc_dll_xform_quse2, + token_emc_dll_xform_quse3, + token_emc_dll_xform_quse4, + token_emc_dll_xform_quse5, + token_emc_dll_xform_quse6, + token_emc_dll_xform_quse7, + token_emc_dll_xform_addr0, + token_emc_dll_xform_addr1, + token_emc_dll_xform_addr2, + token_emc_dll_xform_addr3, + token_emc_dll_xform_addr4, + token_emc_dll_xform_addr5, + token_emc_dll_xform_quse8, + token_emc_dll_xform_quse9, + token_emc_dll_xform_quse10, + token_emc_dll_xform_quse11, + token_emc_dll_xform_quse12, + token_emc_dll_xform_quse13, + token_emc_dll_xform_quse14, + token_emc_dll_xform_quse15, + token_emc_dli_trim_tx_dqs0, + token_emc_dli_trim_tx_dqs1, + token_emc_dli_trim_tx_dqs2, + token_emc_dli_trim_tx_dqs3, + token_emc_dli_trim_tx_dqs4, + token_emc_dli_trim_tx_dqs5, + token_emc_dli_trim_tx_dqs6, + token_emc_dli_trim_tx_dqs7, + token_emc_dli_trim_tx_dqs8, + token_emc_dli_trim_tx_dqs9, + token_emc_dli_trim_tx_dqs10, + token_emc_dli_trim_tx_dqs11, + token_emc_dli_trim_tx_dqs12, + token_emc_dli_trim_tx_dqs13, + token_emc_dli_trim_tx_dqs14, + token_emc_dli_trim_tx_dqs15, + token_emc_dll_xform_dq0, + token_emc_dll_xform_dq1, + token_emc_dll_xform_dq2, + token_emc_dll_xform_dq3, + token_emc_dll_xform_dq4, + token_emc_dll_xform_dq5, + token_emc_dll_xform_dq6, + token_emc_dll_xform_dq7, + token_emc_zcal_interval, + token_emc_zcal_init_dev0, + token_emc_zcal_init_dev1, + token_emc_zcal_init_wait, + token_emc_zcal_cold_boot_enable, + token_emc_zcal_warm_boot_enable, + token_emc_zcal_warm_cold_boot_enables, + token_emc_mrw_lpddr2zcal_warm_boot, + token_emc_zqcal_ddr3_warm_boot, + token_emc_zqcal_lpddr4_warm_boot, + token_emc_zcal_warm_boot_wait, + token_emc_mrs_warm_boot_enable, + token_emc_mrs_extra, + token_emc_warm_boot_mrs, + token_emc_warm_boot_emrs, + token_emc_warm_boot_emr2, + token_emc_warm_boot_emr3, + token_emc_warm_boot_mrs_extra, + token_emc_clken_override, + token_mc_dis_extra_snap_levels, + token_emc_extra_refresh_num, + token_emc_clken_override_allwarm_boot, + token_mc_clken_override_allwarm_boot, + token_emc_cfg_dig_dll_period_warm_boot, + token_pmc_vddp_sel, + token_pmc_vddp_sel_wait, + token_pmc_ddr_cfg, + token_pmc_io_dpd_req, + token_pmc_io_dpd2_req, + token_pmc_io_dpd3_req, + token_pmc_io_dpd3_req_wait, + token_pmc_io_dpd4_req_wait, + token_pmc_reg_short, + token_pmc_eno_vtt_gen, + token_pmc_no_io_power, + + token_pmc_ddr_ctrl_wait, + token_pmc_ddr_ctrl, + + token_pmc_por_dpd_ctrl_wait, + token_emc_xm2cmd_pad_ctrl, + token_emc_xm2cmd_pad_ctrl2, + token_emc_xm2cmd_pad_ctrl3, + token_emc_xm2cmd_pad_ctrl4, + token_emc_xm2cmd_pad_ctrl5, + token_emc_xm2dqs_pad_ctrl, + token_emc_xm2dqs_pad_ctrl2, + token_emc_xm2dqs_pad_ctrl3, + token_emc_xm2dqs_pad_ctrl4, + token_emc_xm2dqs_pad_ctrl5, + token_emc_xm2dqs_pad_ctrl6, + token_emc_xm2dq_pad_ctrl, + token_emc_xm2dq_pad_ctrl2, + token_emc_xm2dq_pad_ctrl3, + token_emc_xm2clk_pad_ctrl, + token_emc_xm2clk_pad_ctrl2, + token_emc_xm2comp_pad_ctrl, + token_emc_xm2vttgen_pad_ctrl, + token_emc_xm2vttgen_pad_ctrl2, + token_emc_xm2vttgen_pad_ctrl3, + token_emc_xm2quse_pad_ctrl, + token_emc_acpd_control, + token_emc_swizzle_rank0_byte_cfg, + token_emc_swizzle_rank0_byte0, + token_emc_swizzle_rank0_byte1, + token_emc_swizzle_rank0_byte2, + token_emc_swizzle_rank0_byte3, + token_emc_swizzle_rank1_byte_cfg, + token_emc_swizzle_rank1_byte0, + token_emc_swizzle_rank1_byte1, + token_emc_swizzle_rank1_byte2, + token_emc_swizzle_rank1_byte3, + token_emc_addr_swizzle_stack1a, + token_emc_addr_swizzle_stack1b, + token_emc_addr_swizzle_stack2a, + token_emc_addr_swizzle_stack2b, + token_emc_addr_swizzle_stack3, + token_emc_dsr_vttgen_drv, + token_emc_txdsrvttgen, + + /* Specifies the value for EMC_DATA_BRLSHFT_0 */ + token_emc_data_brlshft0, + token_emc_data_brlshft1, + + token_emc_dqs_brlshft0, + token_emc_dqs_brlshft1, + + token_emc_cmd_brlshft0, + token_emc_cmd_brlshft1, + token_emc_cmd_brlshft2, + token_emc_cmd_brlshft3, + + token_emc_quse_brlshft0, + token_emc_quse_brlshft1, + token_emc_quse_brlshft2, + token_emc_quse_brlshft3, + + token_emc_dll_cfg0, + token_emc_dll_cfg1, + + token_emc_pmc_scratch1, + token_emc_pmc_scratch2, + token_emc_pmc_scratch3, + + token_emc_pmacro_pad_cfg_ctrl, + + token_emc_pmacro_vttgen_ctrl0, + token_emc_pmacro_vttgen_ctrl1, + token_emc_pmacro_vttgen_ctrl2, + + token_emc_pmacro_brick_ctrl_rfu1, + token_emc_pmacro_cmd_brick_ctrl_fdpd, + token_emc_pmacro_brick_ctrl_rfu2, + token_emc_pmacro_data_brick_ctrl_fdpd, + token_emc_pmacro_bg_bias_ctrl0, + token_emc_pmacro_data_pad_rx_ctrl, + token_emc_pmacro_cmd_pad_rx_ctrl, + token_emc_pmacro_data_rx_term_mode, + token_emc_pmacro_cmd_rx_term_mode, + token_emc_pmacro_data_pad_tx_ctrl, + token_emc_pmacro_common_pad_tx_ctrl, + token_emc_pmacro_cmd_pad_tx_ctrl, + token_emc_cfg3, + + token_emc_pmacro_tx_pwrd0, + token_emc_pmacro_tx_pwrd1, + token_emc_pmacro_tx_pwrd2, + token_emc_pmacro_tx_pwrd3, + token_emc_pmacro_tx_pwrd4, + token_emc_pmacro_tx_pwrd5, + + token_emc_config_sample_delay, + + token_emc_pmacro_brick_mapping0, + token_emc_pmacro_brick_mapping1, + token_emc_pmacro_brick_mapping2, + + token_emc_pmacro_tx_sel_clk_src0, + token_emc_pmacro_tx_sel_clk_src1, + token_emc_pmacro_tx_sel_clk_src2, + token_emc_pmacro_tx_sel_clk_src3, + token_emc_pmacro_tx_sel_clk_src4, + token_emc_pmacro_tx_sel_clk_src5, + + token_emc_pmacro_ddll_bypass, + + token_emc_pmacro_ddll_pwrd0, + token_emc_pmacro_ddll_pwrd1, + token_emc_pmacro_ddll_pwrd2, + + token_emc_pmacro_cmd_ctrl0, + token_emc_pmacro_cmd_ctrl1, + token_emc_pmacro_cmd_ctrl2, + + token_emc_bgbias_ctl0, + token_mc_emem_adr_cfg, + token_mc_emem_adr_cfg_dev0, + token_mc_emem_adr_cfg_dev1, + token_mc_emem_adr_cfg_channel_mask, + token_mc_emem_adr_cfg_channel_mask_propagation_count, + token_mc_emem_adr_cfg_bank_mask0, + token_mc_emem_adr_cfg_bank_mask1, + token_mc_emem_adr_cfg_bank_mask2, + token_mc_emem_adr_cfg_bank_swizzle3, + token_mc_emem_arb_cfg, + token_mc_emem_arb_outstanding_req, + + token_emc_emem_arb_refpb_hp_ctrl, + token_emc_emem_arb_refpb_bank_ctrl, + + token_mc_emem_arb_timing_rcd, + token_mc_emem_arb_timing_rp, + token_mc_emem_arb_timing_rc, + token_mc_emem_arb_timing_ras, + token_mc_emem_arb_timing_faw, + token_mc_emem_arb_timing_rrd, + token_mc_emem_arb_timing_rap2pre, + token_mc_emem_arb_timing_wap2pre, + token_mc_emem_arb_timing_r2r, + token_mc_emem_arb_timing_w2w, + token_mc_emem_arb_timing_r2w, + token_mc_emem_arb_timing_w2r, + + token_mc_emem_arb_timing_rfcpb, + + token_mc_emem_arb_da_turns, + token_mc_emem_arb_da_covers, + token_mc_emem_arb_misc0, + token_mc_emem_arb_misc1, + token_mc_emem_arb_misc2, + + token_mc_emem_arb_ring1_throttle, + token_mc_emem_arb_override, + token_mc_emem_arb_override1, + token_mc_emem_arb_rsv, + + token_mc_da_cfg0, + token_mc_emem_arb_timing_ccdmw, + + token_mc_clken_override, + token_mc_emc_reg_mode, + token_mc_stat_control, + token_mc_display_snap_ring, + token_mc_video_protect_bom, + token_mc_video_protect_bom_adr_hi, + token_mc_video_protect_size_mb, + token_mc_video_protect_vpr_override, + token_mc_video_protect_vpr_override1, + token_mc_video_protect_gpu_override0, + token_mc_video_protect_gpu_override1, + token_mc_sec_carveout_bom, + token_mc_sec_carveout_adr_hi, + token_mc_sec_carveout_size_mb, + token_mc_video_protect_write_access, + token_mc_sec_carveout_protect_write_access, + + token_mc_generalized_carveout1_bom, + token_mc_generalized_carveout1_bom_hi, + token_mc_generalized_carveout1_size_128kb, + token_mc_generalized_carveout1_access0, + token_mc_generalized_carveout1_access1, + token_mc_generalized_carveout1_access2, + token_mc_generalized_carveout1_access3, + token_mc_generalized_carveout1_access4, + token_mc_generalized_carveout1_force_internal_access0, + token_mc_generalized_carveout1_force_internal_access1, + token_mc_generalized_carveout1_force_internal_access2, + token_mc_generalized_carveout1_force_internal_access3, + token_mc_generalized_carveout1_force_internal_access4, + token_mc_generalized_carveout1_cfg0, + + token_mc_generalized_carveout2_bom, + token_mc_generalized_carveout2_bom_hi, + token_mc_generalized_carveout2_size_128kb, + token_mc_generalized_carveout2_access0, + token_mc_generalized_carveout2_access1, + token_mc_generalized_carveout2_access2, + token_mc_generalized_carveout2_access3, + token_mc_generalized_carveout2_access4, + token_mc_generalized_carveout2_force_internal_access0, + token_mc_generalized_carveout2_force_internal_access1, + token_mc_generalized_carveout2_force_internal_access2, + token_mc_generalized_carveout2_force_internal_access3, + token_mc_generalized_carveout2_force_internal_access4, + token_mc_generalized_carveout2_cfg0, + + token_mc_generalized_carveout3_bom, + token_mc_generalized_carveout3_bom_hi, + token_mc_generalized_carveout3_size_128kb, + token_mc_generalized_carveout3_access0, + token_mc_generalized_carveout3_access1, + token_mc_generalized_carveout3_access2, + token_mc_generalized_carveout3_access3, + token_mc_generalized_carveout3_access4, + token_mc_generalized_carveout3_force_internal_access0, + token_mc_generalized_carveout3_force_internal_access1, + token_mc_generalized_carveout3_force_internal_access2, + token_mc_generalized_carveout3_force_internal_access3, + token_mc_generalized_carveout3_force_internal_access4, + token_mc_generalized_carveout3_cfg0, + + token_mc_generalized_carveout4_bom, + token_mc_generalized_carveout4_bom_hi, + token_mc_generalized_carveout4_size_128kb, + token_mc_generalized_carveout4_access0, + token_mc_generalized_carveout4_access1, + token_mc_generalized_carveout4_access2, + token_mc_generalized_carveout4_access3, + token_mc_generalized_carveout4_access4, + token_mc_generalized_carveout4_force_internal_access0, + token_mc_generalized_carveout4_force_internal_access1, + token_mc_generalized_carveout4_force_internal_access2, + token_mc_generalized_carveout4_force_internal_access3, + token_mc_generalized_carveout4_force_internal_access4, + token_mc_generalized_carveout4_cfg0, + + token_mc_generalized_carveout5_bom, + token_mc_generalized_carveout5_bom_hi, + token_mc_generalized_carveout5_size_128kb, + token_mc_generalized_carveout5_access0, + token_mc_generalized_carveout5_access1, + token_mc_generalized_carveout5_access2, + token_mc_generalized_carveout5_access3, + token_mc_generalized_carveout5_access4, + token_mc_generalized_carveout5_force_internal_access0, + token_mc_generalized_carveout5_force_internal_access1, + token_mc_generalized_carveout5_force_internal_access2, + token_mc_generalized_carveout5_force_internal_access3, + token_mc_generalized_carveout5_force_internal_access4, + token_mc_generalized_carveout5_cfg0, + + token_emc_ca_training_enable, + token_emc_ca_training_timing_cntl1, + token_emc_ca_training_timing_cntl2, + token_swizzle_rank_byte_encode, + token_boot_rom_patch_control, + token_boot_rom_patch_data, + token_ch1_emc_dll_xform_dqs0, + token_ch1_emc_dll_xform_dqs1, + token_ch1_emc_dll_xform_dqs2, + token_ch1_emc_dll_xform_dqs3, + token_ch1_emc_dll_xform_dqs4, + token_ch1_emc_dll_xform_dqs5, + token_ch1_emc_dll_xform_dqs6, + token_ch1_emc_dll_xform_dqs7, + token_ch1_emc_dll_xform_quse0, + token_ch1_emc_dll_xform_quse1, + token_ch1_emc_dll_xform_quse2, + token_ch1_emc_dll_xform_quse3, + token_ch1_emc_dll_xform_quse4, + token_ch1_emc_dll_xform_quse5, + token_ch1_emc_dll_xform_quse6, + token_ch1_emc_dll_xform_quse7, + token_ch1_emc_dli_trim_tx_dqs0, + token_ch1_emc_dli_trim_tx_dqs1, + token_ch1_emc_dli_trim_tx_dqs2, + token_ch1_emc_dli_trim_tx_dqs3, + token_ch1_emc_dli_trim_tx_dqs4, + token_ch1_emc_dli_trim_tx_dqs5, + token_ch1_emc_dli_trim_tx_dqs6, + token_ch1_emc_dli_trim_tx_dqs7, + token_ch1_emc_dll_xform_dq0, + token_ch1_emc_dll_xform_dq1, + token_ch1_emc_dll_xform_dq2, + token_ch1_emc_dll_xform_dq3, + token_ch1_emc_swizzle_rank0_byte_cfg, + token_ch1_emc_swizzle_rank0_byte0, + token_ch1_emc_swizzle_rank0_byte1, + token_ch1_emc_swizzle_rank0_byte2, + token_ch1_emc_swizzle_rank0_byte3, + token_ch1_emc_swizzle_rank1_byte_cfg, + token_ch1_emc_swizzle_rank1_byte0, + token_ch1_emc_swizzle_rank1_byte1, + token_ch1_emc_swizzle_rank1_byte2, + token_ch1_emc_swizzle_rank1_byte3, + token_ch1_emc_addr_swizzle_stack1a, + token_ch1_emc_addr_swizzle_stack1b, + token_ch1_emc_addr_swizzle_stack2a, + token_ch1_emc_addr_swizzle_stack2b, + token_ch1_emc_addr_swizzle_stack3, + token_ch1_emc_auto_cal_config, + token_ch1_emc_auto_cal_config2, + token_ch1_emc_auto_cal_config3, + + token_emc_auto_cal_config4, + token_emc_auto_cal_config5, + token_emc_auto_cal_config6, + token_emc_auto_cal_config7, + token_emc_auto_cal_config8, + /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ + token_emc_auto_cal_vref_sel0, + token_emc_auto_cal_vref_sel1, + + /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ + token_emc_auto_cal_channel, + + /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ + token_emc_pmacro_auto_cal_cfg0, + token_emc_pmacro_auto_cal_cfg1, + token_emc_pmacro_auto_cal_cfg2, + + token_emc_pmacro_rx_term, + token_emc_pmacro_dq_tx_drive, + token_emc_pmacro_ca_tx_drive, + token_emc_pmacro_cmd_tx_drive, + token_emc_pmacro_auto_cal_common, + token_emc_pmacro_zcrtl, + + token_ch1_emc_cdb_cntl1, + token_ch1_emc_dll_xform_addr0, + token_ch1_emc_dll_xform_addr1, + token_ch1_emc_dll_xform_addr2, + token_ch1_emc_fbio_spare, + token_ch1_emc_xm2_clk_pad_ctrl, + token_ch1_emc_xm2_clk_pad_ctrl2, + token_ch1_emc_xm2_cmd_pad_ctrl2, + token_ch1_emc_xm2_cmd_pad_ctrl3, + token_ch1_emc_xm2_cmd_pad_ctrl4, + token_ch1_emc_xm2_dq_pad_ctrl, + token_ch1_emc_xm2_dq_pad_ctrl2, + token_ch1_emc_xm2_dqs_pad_ctrl, + token_ch1_emc_xm2_dqs_pad_ctrl3, + token_ch1_emc_xm2_dqs_pad_ctrl4, + token_mc_mts_carveout_bom, + token_mc_mts_carveout_adr_hi, + token_mc_mts_carveout_size_mb, + token_mc_mts_carveout_reg_ctrl, + + token_mts_info_version, + token_mts_info_start_blk, + token_mts_info_start_page, + token_mts_info_length, + token_mts_info_load_addr, + token_mts_info_entry_point, + token_mts_info_attribute, + + token_mts_used, + token_mts_max, + + token_force32 = 0x7fffffff +} parse_token; + +typedef enum +{ + field_type_none = 0, + field_type_enum, + field_type_u32, + field_type_u8, + field_type_force32 = 0x7fffffff +} field_type; + +/* Forward declarations */ +typedef int (*process_function)(build_image_context *context, + parse_token token, + char *remainder); + +typedef int (*process_subfield_function)(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); + + +typedef struct +{ + char *name; + uint32_t value; +} enum_item; + +typedef struct +{ + char *name; + uint32_t token; + field_type type; + enum_item *enum_table; +} field_item; + + +typedef struct +{ + char *prefix; + parse_token token; + field_item *field_table; + process_subfield_function process; +} parse_subfield_item; + +typedef struct +{ + char *prefix; + parse_token token; + process_function process; +} parse_item; + +/* + * Set of function pointers and table pointers to be used to access the different hardware + * interface for setting/getting bct information. + */ +typedef struct cbootimage_soc_config_rec { + /* + * Set device parameters in bct according to the value listed + * + * @param context The main context pointer + * @param index The device index in bct field + * @param token The parse token value + * @param value Value to set + * @return 0 and -ENODATA for success and failure + */ + int (*set_dev_param)(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); + /* + * Get the specified device parameters from bct data stored + * in context. + * + * @param context The main context pointer + * @param index The device index in bct field + * @param token The parse token value + * @param value Return value get from bct field + * @return 0 and -ENODATA for success and failure + */ + int (*get_dev_param)(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); + /* + * Set sdram parameters in bct according to the value listed + * in config file. + * + * @param context The main context pointer + * @param index The sdram index in bct field + * @param token The parse token value + * @param value Value to set + * @return 0 and 1 for success and failure + */ + int (*set_sdram_param)(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); + /* + * Get the specified sdram parameters from bct data stored + * in context. + * + * @param context The main context pointer + * @param index The sdram index in bct field + * @param token The parse token value + * @param value Return value get from bct field + * @return 0 and 1 for success and failure + */ + int (*get_sdram_param)(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); + /* + * Set bootloader parameters in bct according to the value listed + * in config file. + * + * @param set Bootloader index + * @param id The parse token value + * @param data Value to set + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*setbl_param)(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct); + /* + * Get the specified bootloader parameters from bct data stored + * in context. + * + * @param set Bootloader index + * @param id The parse token value + * @param data Return value get from bct data + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*getbl_param)(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct); + /* + * Set the specified bct value stored in context bct data structure. + * + * @param id The parse token value + * @param data Pointer of value to set + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*set_value)(parse_token id, + void *data, + uint8_t *bct); + /* + * Get the specified bct value or some constant value of clocks and + * hw type. + * + * @param id The parse token value + * @param data Return value get from bct data + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*get_value)(parse_token id, + void *data, + uint8_t *bct); + /* + * Get the size of specified bct field + * + * @param id The parse token + * @return size or 0/-ENODATA for failure + */ + int (*get_value_size)(parse_token id); + + /* + * Set the bct crypto hash data. + * + * @param id The parse token value + * @param data Value to set + * @param length Length of data to set + * @param bct Bct pointer + * @return 0 and -ENODATA for success and failure + */ + int (*set_data)(parse_token id, + uint8_t *data, + uint32_t length, + uint8_t *bct); + + /* + * Get the BCT structure size + * + * @return BCT size + */ + int (*get_bct_size)(); + + /* + * Set MTS infomation in bct according to the value listed + * in config file. + * + * @param context The main context pointer + * @param index The mts_info index in bct field + * @param token The parse token value + * @param value Value to set + * @return 0 and 1 for success and failure + */ + int (*set_mts_info)(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); + /* + * Get the specified MTS information from bct data stored + * in context. + * + * @param context The main context pointer + * @param index The mts_info index in bct field + * @param token The parse token value + * @param value Return value get from bct field + * @return 0 and 1 for success and failure + */ + int (*get_mts_info)(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); + + /* + * Check if the token is supported to dump + * + * @param id The parse token value + * @return 0 and 1 for unsupported and supported + */ + int (*token_supported)(parse_token id); + + void (*init_bad_block_table)(build_image_context *context); + + enum_item *devtype_table; + enum_item *sdmmc_data_width_table; + enum_item *spi_clock_source_table; + enum_item *nvboot_memory_type_table; + field_item *sdram_field_table; + field_item *nand_table; + field_item *sdmmc_table; + field_item *spiflash_table; + parse_subfield_item *device_type_table; +} cbootimage_soc_config; + +void process_config_file(build_image_context *context, uint8_t simple_parse); + +void t210_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +void t132_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +void t124_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +void t114_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +void t30_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +void t20_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); + +int if_bct_is_t210_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +int if_bct_is_t132_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +int if_bct_is_t124_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +int if_bct_is_t114_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +int if_bct_is_t30_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); +int if_bct_is_t20_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config); + +int +t132_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t132_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); +int +t132_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t132_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); + +int +t210_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t210_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); +int +t210_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t210_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); + +int +t124_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t124_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); +int +t124_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t124_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); +int +t114_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t114_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); +int +t114_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t114_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); +int +t30_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t30_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); +int +t30_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t30_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); +int +t20_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t20_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); + +int +t20_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value); +int +t20_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value); + +uint32_t iceil_log2(uint32_t a, uint32_t b); + +/* Returns the smallest power of 2 >= a */ +uint32_t ceil_log2(uint32_t a); + +extern cbootimage_soc_config *g_soc_config; + +/* + * Dummy function for unsupported token + */ +int bct_get_unsupported(parse_token id); + +/* + * Provide access to enum and field tables. These tables are useful when + * pretty printing a BCT file using bct_dump. + */ + +extern enum_item s_devtype_table_t20[]; +extern enum_item s_devtype_table_t30[]; +extern enum_item s_devtype_table_t114[]; +extern enum_item s_devtype_table_t124[]; +extern enum_item s_devtype_table_t132[]; +extern enum_item s_devtype_table_t210[]; + +extern enum_item s_sdmmc_data_width_table_t20[]; +extern enum_item s_sdmmc_data_width_table_t30[]; +extern enum_item s_sdmmc_data_width_table_t114[]; +extern enum_item s_sdmmc_data_width_table_t124[]; +extern enum_item s_sdmmc_data_width_table_t132[]; +extern enum_item s_sdmmc_data_width_table_t210[]; + +extern enum_item s_spi_clock_source_table_t20[]; +extern enum_item s_spi_clock_source_table_t30[]; +extern enum_item s_spi_clock_source_table_t114[]; +extern enum_item s_spi_clock_source_table_t124[]; +extern enum_item s_spi_clock_source_table_t132[]; +extern enum_item s_spi_clock_source_table_t210[]; + +extern enum_item s_nvboot_memory_type_table_t20[]; +extern enum_item s_nvboot_memory_type_table_t30[]; +extern enum_item s_nvboot_memory_type_table_t114[]; +extern enum_item s_nvboot_memory_type_table_t124[]; +extern enum_item s_nvboot_memory_type_table_t132[]; +extern enum_item s_nvboot_memory_type_table_t210[]; + +extern field_item s_sdram_field_table_t20[]; +extern field_item s_sdram_field_table_t30[]; +extern field_item s_sdram_field_table_t114[]; +extern field_item s_sdram_field_table_t124[]; +extern field_item s_sdram_field_table_t132[]; +extern field_item s_sdram_field_table_t210[]; + +extern field_item s_nand_table_t20[]; +extern field_item s_nand_table_t30[]; + +extern field_item s_sdmmc_table_t20[]; +extern field_item s_sdmmc_table_t30[]; +extern field_item s_sdmmc_table_t114[]; +extern field_item s_sdmmc_table_t124[]; +extern field_item s_sdmmc_table_t132[]; +extern field_item s_sdmmc_table_t210[]; + +extern field_item s_spiflash_table_t20[]; +extern field_item s_spiflash_table_t30[]; +extern field_item s_spiflash_table_t114[]; +extern field_item s_spiflash_table_t124[]; +extern field_item s_spiflash_table_t132[]; +extern field_item s_spiflash_table_t210[]; + +extern parse_subfield_item s_device_type_table_t20[]; +extern parse_subfield_item s_device_type_table_t30[]; +extern parse_subfield_item s_device_type_table_t114[]; +extern parse_subfield_item s_device_type_table_t124[]; +extern parse_subfield_item s_device_type_table_t132[]; +extern parse_subfield_item s_device_type_table_t210[]; + +#endif /* #ifndef INCLUDED_PARSE_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/set.c b/firmware/coreboot/util/nvidia/cbootimage/src/set.c new file mode 100644 index 0000000000..934a58de1f --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/set.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * set.c - State setting support for the cbootimage tool + */ + +#include "set.h" +#include "cbootimage.h" +#include "crypto.h" +#include "data_layout.h" + +/* + * Function prototypes + * + * ParseXXX() parses XXX in the input + * SetXXX() sets state based on the parsing results but does not perform + * any parsing of its own + * A ParseXXX() function may call other parse functions and set functions. + * A SetXXX() function may not call any parseing functions. + */ +#define DEFAULT() \ + default: \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +int +read_from_image(char *filename, + uint32_t offset, + uint32_t max_size, + uint8_t **image, + uint32_t *actual_size, + file_type f_type) +{ + int result = 0; /* 0 = success, 1 = failure */ + FILE *fp; + struct stat stats; + + fp = fopen(filename, "rb"); + if (fp == NULL) { + result = 1; + return result; + } + + if (fseek(fp, offset, SEEK_SET) == -1) { + printf("Error: Couldn't seek to %s(%d)\n", filename, offset); + result = 1; + goto cleanup; + } + + if (stat(filename, &stats) != 0) { + printf("Error: Unable to query info on bootloader path %s\n", + filename); + result = 1; + goto cleanup; + } + + if (f_type == file_type_bl) { + if ((stats.st_size - offset) > max_size) { + printf("Error: Bootloader file %s is too large.\n", + filename); + result = 1; + goto cleanup; + } + *actual_size = (uint32_t)stats.st_size; + } else { + if ((stats.st_size - offset) < max_size) + *actual_size = stats.st_size - offset; + else + *actual_size = max_size; + } + + *image = malloc(*actual_size); + if (*image == NULL) { + result = 1; + goto cleanup; + } + + memset(*image, 0, *actual_size); + + if (fread(*image, 1, (size_t)(*actual_size), fp) != + (size_t)(*actual_size)) { + result = 1; + goto cleanup; + } + +cleanup: + fclose(fp); + return result; +} + +/* + * Processes commands to set a bootloader. + * + * @param context The main context pointer + * @param filename The file name of bootloader + * @param load_addr The load address value for bootloader + * @param entry_point The entry point value for bootloader + * @return 0 and 1 for success and failure + */ +int +set_bootloader(build_image_context *context, + char *filename, + uint32_t load_addr, + uint32_t entry_point) +{ + context->newbl_filename = filename; + context->newbl_load_addr = load_addr; + context->newbl_entry_point = entry_point; + return update_bl(context); +} + +/* + * Processes commands to set a MTS image. + * + * @param context The main context pointer + * @param filename The file name of MTS image + * @param load_addr The load address value for MTS image + * @param entry_point The entry point value for MTS image + * @return 0 and 1 for success and failure + */ +int +set_mts_image(build_image_context *context, + char *filename, + uint32_t load_addr, + uint32_t entry_point) +{ + context->mts_filename = filename; + context->mts_load_addr = load_addr; + context->mts_entry_point = entry_point; + return update_mts_image(context); +} + +int +set_rsa_param(build_image_context *context, parse_token token, + char *filename) +{ + int result; + uint8_t *rsa_storage; /* Holds the rsa param after reading */ + int32_t size; /* Bytes to read */ + uint32_t actual_size; /* In bytes */ + + if ((size = g_soc_config->get_value_size(token)) <= 0) { + printf("Error: Unsupported token %d for value size.\n", token); + exit(1); + } + + /* Read the image into memory. */ + result = read_from_image(filename, + 0, + (uint32_t)size, + &rsa_storage, + &actual_size, + file_type_bin); + + if (result) { + printf("Error reading file %s.\n", filename); + exit(1); + } + + if (actual_size != size) { + printf("Error: invalid size, file %s.\n", filename); + exit(1); + } + + if (enable_debug) + printf("Updating token %d with file %s\n", (int)token, filename); + + /* set to appropriate bct field */ + result = g_soc_config->set_value(token, + rsa_storage, context->bct); + + free(rsa_storage); + return result; +} + +#define DEFAULT() \ + default: \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +/* + * General handler for setting values in config files. + * + * @param context The main context pointer + * @param token The parse token value + * @param value The pointer of value to set + * @return 0 for success + */ +int context_set_value(build_image_context *context, + parse_token token, + void *value) +{ + assert(context != NULL); + + switch (token) { + case token_attribute: + context->newbl_attr = *((uint32_t *)value); + break; + + case token_block_size: + context->block_size = *((uint32_t *)value); + context->block_size_log2 = log2(*((uint32_t *)value)); + + if (context->memory != NULL) { + printf("Error: Too late to change block size.\n"); + return 1; + } + + if (context->block_size != (uint32_t)(1 << context->block_size_log2)) { + printf("Error: Block size must be a power of 2.\n"); + return 1; + } + context->pages_per_blk= 1 << (context->block_size_log2- + context->page_size_log2); + g_soc_config->set_value(token_block_size_log2, + &(context->block_size_log2), context->bct); + break; + + case token_partition_size: + if (context->memory != NULL) { + printf("Error: Too late to change block size.\n"); + return 1; + } + + context->partition_size= *((uint32_t *)value); + g_soc_config->set_value(token_partition_size, + value, context->bct); + break; + + case token_page_size: + context->page_size = *((uint32_t *)value); + context->page_size_log2 = log2(*((uint32_t *)value)); + + if (context->page_size != (uint32_t)(1 << context->page_size_log2)) { + printf("Error: Page size must be a power of 2.\n"); + return 1; + } + context->pages_per_blk= 1 << (context->block_size_log2- + context->page_size_log2); + + g_soc_config->set_value(token_page_size_log2, + &(context->page_size_log2), context->bct); + break; + case token_redundancy: + context->redundancy = *((uint32_t *)value); + break; + + case token_version: + context->version = *((uint32_t *)value); + break; + + case token_bct_copy: + context->bct_copy = *((uint32_t *)value); + break; + + case token_odm_data: + context->odm_data = *((uint32_t *)value); + break; + + case token_pre_bct_pad_blocks: + if (context->bct_init) { + printf("Error: Too late to pre-BCT pad.\n"); + return 1; + } + context->pre_bct_pad_blocks = *((uint32_t *)value); + break; + + case token_secure_jtag_control: + context->secure_jtag_control = *((uint32_t *)value); + g_soc_config->set_value(token_secure_jtag_control, + value, context->bct); + break; + + case token_secure_debug_control: + context->secure_debug_control = *((uint32_t *)value); + g_soc_config->set_value(token_secure_debug_control, + value, context->bct); + break; + + case token_unique_chip_id: + memcpy(context->unique_chip_id, value, 16); + g_soc_config->set_value(token_unique_chip_id, + value, context->bct); + break; + + DEFAULT(); + } + + return 0; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/set.h b/firmware/coreboot/util/nvidia/cbootimage/src/set.h new file mode 100644 index 0000000000..8548febae2 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/set.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * set.h - Definitions for the cbootimage state setting code. + */ + +#ifndef INCLUDED_SET_H +#define INCLUDED_SET_H + +#include "cbootimage.h" +#include "parse.h" +#include "string.h" +#include "sys/stat.h" + +int +set_bootloader(build_image_context *context, + char *filename, + uint32_t load_addr, + uint32_t entry_point); + +int +set_mts_image(build_image_context *context, + char *filename, + uint32_t load_addr, + uint32_t entry_point); + +int +set_rsa_param(build_image_context *context, + parse_token token, + char *filename); + +int +context_set_value(build_image_context *context, + parse_token token, + void *value); + +int +read_from_image(char *filename, + uint32_t offset, + uint32_t max_size, + uint8_t **Image, + uint32_t *actual_size, + file_type f_type); + +#endif /* #ifndef INCLUDED_SET_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t114/nvbctlib_t114.c b/firmware/coreboot/util/nvidia/cbootimage/src/t114/nvbctlib_t114.c new file mode 100644 index 0000000000..dd0ccdee15 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t114/nvbctlib_t114.c @@ -0,0 +1,1149 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include "../cbootimage.h" +#include "../parse.h" +#include "../crypto.h" +#include "nvboot_bct_t114.h" +#include "string.h" + +/* nvbctlib_t114.c: The implementation of the nvbctlib API for t114. */ + +/* Definitions that simplify the code which follows. */ +#define CASE_GET_SDRAM_PARAM(x) \ +case token_##x:\ + *value = params->x; \ + break + +#define CASE_SET_SDRAM_PARAM(x) \ +case token_##x:\ + params->x = value; \ + break + +#define CASE_GET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + *value = bct->dev_params[index].dev##_params.x; \ + break + +#define CASE_SET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + bct->dev_params[index].dev##_params.x = value; \ + break + +#define CASE_GET_BL_PARAM(x) \ +case token_bl_##x:\ + *data = bct_ptr->bootloader[set].x; \ + break + +#define CASE_SET_BL_PARAM(x) \ +case token_bl_##x:\ + bct_ptr->bootloader[set].x = *data; \ + break + +#define CASE_GET_NVU32(id) \ +case token_##id:\ + if (bct == NULL) return -ENODATA; \ + *((uint32_t *)data) = bct_ptr->id; \ + break + +#define CASE_GET_CONST(id, val) \ +case token_##id:\ + *((uint32_t *)data) = val; \ + break + +#define CASE_GET_CONST_PREFIX(id, val_prefix) \ +case token_##id:\ + *((uint32_t *)data) = val_prefix##_##id; \ + break + +#define CASE_SET_NVU32(id) \ +case token_##id:\ + bct_ptr->id = *((uint32_t *)data); \ + break + +#define CASE_GET_DATA(id, size) \ +case token_##id:\ + if (*length < size) return -ENODATA;\ + memcpy(data, &(bct_ptr->id), size); \ + *length = size;\ + break + +#define CASE_SET_DATA(id, size) \ +case token_##id:\ + if (length < size) return -ENODATA;\ + memcpy(&(bct_ptr->id), data, size); \ + break + +#define DEFAULT() \ +default : \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +parse_token t114_root_token_list[] = { + token_boot_data_version, + token_block_size, + token_page_size, + token_partition_size, + token_odm_data, + token_bootloader_used, + token_bootloaders_max, + token_bct_size, + token_hash_size, + token_crypto_offset, + token_crypto_length, + token_max_bct_search_blks +}; + +int +t114_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1); + + switch (token) { + CASE_SET_DEV_PARAM(sdmmc, clock_divider); + CASE_SET_DEV_PARAM(sdmmc, data_width); + CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_SET_DEV_PARAM(sdmmc, multi_page_support); + + CASE_SET_DEV_PARAM(spiflash, clock_source); + CASE_SET_DEV_PARAM(spiflash, clock_divider); + CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + CASE_SET_DEV_PARAM(spiflash, page_size_2k_or_16k); + + case token_dev_type: + bct->dev_type[index] = value; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t114_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + switch (token) { + CASE_GET_DEV_PARAM(sdmmc, clock_divider); + CASE_GET_DEV_PARAM(sdmmc, data_width); + CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_GET_DEV_PARAM(sdmmc, multi_page_support); + + CASE_GET_DEV_PARAM(spiflash, clock_source); + CASE_GET_DEV_PARAM(spiflash, clock_divider); + CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); + CASE_GET_DEV_PARAM(spiflash, page_size_2k_or_16k); + + case token_dev_type: + *value = bct->dev_type[index]; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t114_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + + switch (token) { + CASE_GET_SDRAM_PARAM(memory_type); + CASE_GET_SDRAM_PARAM(pllm_input_divider); + CASE_GET_SDRAM_PARAM(pllm_feedback_divider); + CASE_GET_SDRAM_PARAM(pllm_stable_time); + CASE_GET_SDRAM_PARAM(pllm_setup_control); + CASE_GET_SDRAM_PARAM(pllm_select_div2); + CASE_GET_SDRAM_PARAM(pllm_pdlshift_ph45); + CASE_GET_SDRAM_PARAM(pllm_pdlshift_ph90); + CASE_GET_SDRAM_PARAM(pllm_pdlshift_ph135); + CASE_GET_SDRAM_PARAM(pllm_kcp); + CASE_GET_SDRAM_PARAM(pllm_kvco); + CASE_GET_SDRAM_PARAM(emc_bct_spare0); + CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config2); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config3); + CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_GET_SDRAM_PARAM(emc_pin_program_wait); + CASE_GET_SDRAM_PARAM(emc_rc); + CASE_GET_SDRAM_PARAM(emc_rfc); + CASE_GET_SDRAM_PARAM(emc_rfc_slr); + CASE_GET_SDRAM_PARAM(emc_ras); + CASE_GET_SDRAM_PARAM(emc_rp); + CASE_GET_SDRAM_PARAM(emc_r2r); + CASE_GET_SDRAM_PARAM(emc_w2w); + CASE_GET_SDRAM_PARAM(emc_r2w); + CASE_GET_SDRAM_PARAM(emc_w2r); + CASE_GET_SDRAM_PARAM(emc_r2p); + CASE_GET_SDRAM_PARAM(emc_w2p); + CASE_GET_SDRAM_PARAM(emc_rd_rcd); + CASE_GET_SDRAM_PARAM(emc_wr_rcd); + CASE_GET_SDRAM_PARAM(emc_rrd); + CASE_GET_SDRAM_PARAM(emc_rext); + CASE_GET_SDRAM_PARAM(emc_wdv); + CASE_GET_SDRAM_PARAM(emc_wdv_mask); + CASE_GET_SDRAM_PARAM(emc_quse); + CASE_GET_SDRAM_PARAM(emc_ibdly); + CASE_GET_SDRAM_PARAM(emc_einput); + CASE_GET_SDRAM_PARAM(emc_einput_duration); + CASE_GET_SDRAM_PARAM(emc_puterm_extra); + CASE_GET_SDRAM_PARAM(emc_cdb_cntl1); + CASE_GET_SDRAM_PARAM(emc_cdb_cntl2); + CASE_GET_SDRAM_PARAM(emc_qrst); + CASE_GET_SDRAM_PARAM(emc_qsafe); + CASE_GET_SDRAM_PARAM(emc_rdv); + CASE_GET_SDRAM_PARAM(emc_rdv_mask); + CASE_GET_SDRAM_PARAM(emc_refresh); + CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_GET_SDRAM_PARAM(emc_pdex2wr); + CASE_GET_SDRAM_PARAM(emc_pdex2rd); + CASE_GET_SDRAM_PARAM(emc_pchg2pden); + CASE_GET_SDRAM_PARAM(emc_act2pden); + CASE_GET_SDRAM_PARAM(emc_ar2pden); + CASE_GET_SDRAM_PARAM(emc_rw2pden); + CASE_GET_SDRAM_PARAM(emc_txsr); + CASE_GET_SDRAM_PARAM(emc_tcke); + CASE_GET_SDRAM_PARAM(emc_tckesr); + CASE_GET_SDRAM_PARAM(emc_tpd); + CASE_GET_SDRAM_PARAM(emc_tfaw); + CASE_GET_SDRAM_PARAM(emc_trpab); + CASE_GET_SDRAM_PARAM(emc_tclkstable); + CASE_GET_SDRAM_PARAM(emc_tclkstop); + CASE_GET_SDRAM_PARAM(emc_trefbw); + CASE_GET_SDRAM_PARAM(emc_quse_extra); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_GET_SDRAM_PARAM(emc_fbio_spare); + CASE_GET_SDRAM_PARAM(emc_mrs); + CASE_GET_SDRAM_PARAM(emc_emrs); + CASE_GET_SDRAM_PARAM(emc_emrs2); + CASE_GET_SDRAM_PARAM(emc_emrs3); + CASE_GET_SDRAM_PARAM(emc_mrw1); + CASE_GET_SDRAM_PARAM(emc_mrw2); + CASE_GET_SDRAM_PARAM(emc_mrw3); + CASE_GET_SDRAM_PARAM(emc_mrw4); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_GET_SDRAM_PARAM(emc_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg2); + CASE_GET_SDRAM_PARAM(emc_dbg); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_GET_SDRAM_PARAM(warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_GET_SDRAM_PARAM(emc_odt_write); + CASE_GET_SDRAM_PARAM(emc_odt_read); + CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_GET_SDRAM_PARAM(emc_ddr2_wait); + CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_GET_SDRAM_PARAM(emc_clock_source); + CASE_GET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_GET_SDRAM_PARAM(emc_timing_control_wait); + CASE_GET_SDRAM_PARAM(emc_wext); + CASE_GET_SDRAM_PARAM(emc_ctt); + CASE_GET_SDRAM_PARAM(emc_ctt_duration); + CASE_GET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_GET_SDRAM_PARAM(emc_txsr_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_rsv); + CASE_GET_SDRAM_PARAM(emc_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt2); + CASE_GET_SDRAM_PARAM(emc_cmd_q); + CASE_GET_SDRAM_PARAM(emc_mc2emc_q); + CASE_GET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_GET_SDRAM_PARAM(emc_dev_select); + CASE_GET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr2); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_GET_SDRAM_PARAM(emc_zcal_interval); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_GET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_cold_boot_enables); + CASE_GET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_clken_override); + CASE_GET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_GET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_GET_SDRAM_PARAM(pmc_vddp_sel); + CASE_GET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_GET_SDRAM_PARAM(pmc_io_dpd_req); + CASE_GET_SDRAM_PARAM(pmc_io_dpd2_req); + CASE_GET_SDRAM_PARAM(pmc_reg_short); + CASE_GET_SDRAM_PARAM(pmc_eno_vtt_gen); + CASE_GET_SDRAM_PARAM(pmc_no_io_power); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl4); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl4); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2clk_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_acpd_control); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte_cfg); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte0); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte1); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte2); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte3); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte_cfg); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte0); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte1); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte2); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte3); + CASE_GET_SDRAM_PARAM(emc_addr_swizzle_stack1a); + CASE_GET_SDRAM_PARAM(emc_addr_swizzle_stack1b); + CASE_GET_SDRAM_PARAM(emc_addr_swizzle_stack2a); + CASE_GET_SDRAM_PARAM(emc_addr_swizzle_stack2b); + CASE_GET_SDRAM_PARAM(emc_addr_swizzle_stack3); + CASE_GET_SDRAM_PARAM(emc_dsr_vttgen_drv); + CASE_GET_SDRAM_PARAM(emc_txdsrvttgen); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_channel_mask); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_channel_mask_propagation_count); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask1); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask2); + CASE_GET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_GET_SDRAM_PARAM(mc_emem_arb_override); + CASE_GET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_GET_SDRAM_PARAM(mc_clken_override); + CASE_GET_SDRAM_PARAM(mc_emc_reg_mode); + CASE_GET_SDRAM_PARAM(mc_video_protect_bom); + CASE_GET_SDRAM_PARAM(mc_video_protect_size_mb); + CASE_GET_SDRAM_PARAM(mc_video_protect_vpr_override); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_bom); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_size_mb); + CASE_GET_SDRAM_PARAM(mc_video_protect_write_access); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_protect_write_access); + CASE_GET_SDRAM_PARAM(emc_ca_training_enable); + CASE_GET_SDRAM_PARAM(emc_ca_training_timing_cntl1); + CASE_GET_SDRAM_PARAM(emc_ca_training_timing_cntl2); + CASE_GET_SDRAM_PARAM(swizzle_rank_byte_encode); + CASE_GET_SDRAM_PARAM(boot_rom_patch_control); + CASE_GET_SDRAM_PARAM(boot_rom_patch_data); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dqs0); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dqs1); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dqs2); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dqs3); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dqs4); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dqs5); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dqs6); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dqs7); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_quse0); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_quse1); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_quse2); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_quse3); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_quse4); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_quse5); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_quse6); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_quse7); + CASE_GET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs0); + CASE_GET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs1); + CASE_GET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs2); + CASE_GET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs3); + CASE_GET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs4); + CASE_GET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs5); + CASE_GET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs6); + CASE_GET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs7); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dq0); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dq1); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dq2); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_dq3); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte_cfg); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte0); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte1); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte2); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte3); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte_cfg); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte0); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte1); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte2); + CASE_GET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte3); + CASE_GET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack1a); + CASE_GET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack1b); + CASE_GET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack2a); + CASE_GET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack2b); + CASE_GET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack3); + CASE_GET_SDRAM_PARAM(ch1_emc_auto_cal_config); + CASE_GET_SDRAM_PARAM(ch1_emc_auto_cal_config2); + CASE_GET_SDRAM_PARAM(ch1_emc_auto_cal_config3); + CASE_GET_SDRAM_PARAM(ch1_emc_cdb_cntl1); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_addr0); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_addr1); + CASE_GET_SDRAM_PARAM(ch1_emc_dll_xform_addr2); + CASE_GET_SDRAM_PARAM(ch1_emc_fbio_spare); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_clk_pad_ctrl); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_clk_pad_ctrl2); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_cmd_pad_ctrl2); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_cmd_pad_ctrl3); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_cmd_pad_ctrl4); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_dq_pad_ctrl); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_dq_pad_ctrl2); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_dqs_pad_ctrl); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_dqs_pad_ctrl3); + CASE_GET_SDRAM_PARAM(ch1_emc_xm2_dqs_pad_ctrl4); + + DEFAULT(); + } + return 0; +} + +int +t114_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + /* Update the number of SDRAM parameter sets. */ + bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1); + + switch (token) { + CASE_SET_SDRAM_PARAM(memory_type); + CASE_SET_SDRAM_PARAM(pllm_input_divider); + CASE_SET_SDRAM_PARAM(pllm_feedback_divider); + CASE_SET_SDRAM_PARAM(pllm_stable_time); + CASE_SET_SDRAM_PARAM(pllm_setup_control); + CASE_SET_SDRAM_PARAM(pllm_select_div2); + CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph45); + CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph90); + CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph135); + CASE_SET_SDRAM_PARAM(pllm_kcp); + CASE_SET_SDRAM_PARAM(pllm_kvco); + CASE_SET_SDRAM_PARAM(emc_bct_spare0); + CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config2); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config3); + CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_SET_SDRAM_PARAM(emc_pin_program_wait); + CASE_SET_SDRAM_PARAM(emc_rc); + CASE_SET_SDRAM_PARAM(emc_rfc); + CASE_SET_SDRAM_PARAM(emc_rfc_slr); + CASE_SET_SDRAM_PARAM(emc_ras); + CASE_SET_SDRAM_PARAM(emc_rp); + CASE_SET_SDRAM_PARAM(emc_r2r); + CASE_SET_SDRAM_PARAM(emc_w2w); + CASE_SET_SDRAM_PARAM(emc_r2w); + CASE_SET_SDRAM_PARAM(emc_w2r); + CASE_SET_SDRAM_PARAM(emc_r2p); + CASE_SET_SDRAM_PARAM(emc_w2p); + CASE_SET_SDRAM_PARAM(emc_rd_rcd); + CASE_SET_SDRAM_PARAM(emc_wr_rcd); + CASE_SET_SDRAM_PARAM(emc_rrd); + CASE_SET_SDRAM_PARAM(emc_rext); + CASE_SET_SDRAM_PARAM(emc_wdv); + CASE_SET_SDRAM_PARAM(emc_wdv_mask); + CASE_SET_SDRAM_PARAM(emc_quse); + CASE_SET_SDRAM_PARAM(emc_ibdly); + CASE_SET_SDRAM_PARAM(emc_einput); + CASE_SET_SDRAM_PARAM(emc_einput_duration); + CASE_SET_SDRAM_PARAM(emc_puterm_extra); + CASE_SET_SDRAM_PARAM(emc_cdb_cntl1); + CASE_SET_SDRAM_PARAM(emc_cdb_cntl2); + CASE_SET_SDRAM_PARAM(emc_qrst); + CASE_SET_SDRAM_PARAM(emc_qsafe); + CASE_SET_SDRAM_PARAM(emc_rdv); + CASE_SET_SDRAM_PARAM(emc_rdv_mask); + CASE_SET_SDRAM_PARAM(emc_refresh); + CASE_SET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_SET_SDRAM_PARAM(emc_pdex2wr); + CASE_SET_SDRAM_PARAM(emc_pdex2rd); + CASE_SET_SDRAM_PARAM(emc_pchg2pden); + CASE_SET_SDRAM_PARAM(emc_act2pden); + CASE_SET_SDRAM_PARAM(emc_ar2pden); + CASE_SET_SDRAM_PARAM(emc_rw2pden); + CASE_SET_SDRAM_PARAM(emc_txsr); + CASE_SET_SDRAM_PARAM(emc_tcke); + CASE_SET_SDRAM_PARAM(emc_tckesr); + CASE_SET_SDRAM_PARAM(emc_tpd); + CASE_SET_SDRAM_PARAM(emc_tfaw); + CASE_SET_SDRAM_PARAM(emc_trpab); + CASE_SET_SDRAM_PARAM(emc_tclkstable); + CASE_SET_SDRAM_PARAM(emc_tclkstop); + CASE_SET_SDRAM_PARAM(emc_trefbw); + CASE_SET_SDRAM_PARAM(emc_quse_extra); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_SET_SDRAM_PARAM(emc_fbio_spare); + CASE_SET_SDRAM_PARAM(emc_mrs); + CASE_SET_SDRAM_PARAM(emc_emrs); + CASE_SET_SDRAM_PARAM(emc_emrs2); + CASE_SET_SDRAM_PARAM(emc_emrs3); + CASE_SET_SDRAM_PARAM(emc_mrw1); + CASE_SET_SDRAM_PARAM(emc_mrw2); + CASE_SET_SDRAM_PARAM(emc_mrw3); + CASE_SET_SDRAM_PARAM(emc_mrw4); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_SET_SDRAM_PARAM(emc_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg2); + CASE_SET_SDRAM_PARAM(emc_dbg); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_SET_SDRAM_PARAM(warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_SET_SDRAM_PARAM(emc_odt_write); + CASE_SET_SDRAM_PARAM(emc_odt_read); + CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_SET_SDRAM_PARAM(emc_ddr2_wait); + CASE_SET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_SET_SDRAM_PARAM(emc_clock_source); + CASE_SET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_SET_SDRAM_PARAM(emc_timing_control_wait); + CASE_SET_SDRAM_PARAM(emc_wext); + CASE_SET_SDRAM_PARAM(emc_ctt); + CASE_SET_SDRAM_PARAM(emc_ctt_duration); + CASE_SET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_SET_SDRAM_PARAM(emc_txsr_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_rsv); + CASE_SET_SDRAM_PARAM(emc_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt2); + CASE_SET_SDRAM_PARAM(emc_cmd_q); + CASE_SET_SDRAM_PARAM(emc_mc2emc_q); + CASE_SET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_SET_SDRAM_PARAM(emc_dev_select); + CASE_SET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr2); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_SET_SDRAM_PARAM(emc_zcal_interval); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_SET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_cold_boot_enables); + CASE_SET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_clken_override); + CASE_SET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_SET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_SET_SDRAM_PARAM(pmc_vddp_sel); + CASE_SET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_SET_SDRAM_PARAM(pmc_io_dpd_req); + CASE_SET_SDRAM_PARAM(pmc_io_dpd2_req); + CASE_SET_SDRAM_PARAM(pmc_reg_short); + CASE_SET_SDRAM_PARAM(pmc_eno_vtt_gen); + CASE_SET_SDRAM_PARAM(pmc_no_io_power); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl4); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl4); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_acpd_control); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte_cfg); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte0); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte1); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte2); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte3); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte_cfg); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte0); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte1); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte2); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte3); + CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack1a); + CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack1b); + CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack2a); + CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack2b); + CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack3); + CASE_SET_SDRAM_PARAM(emc_dsr_vttgen_drv); + CASE_SET_SDRAM_PARAM(emc_txdsrvttgen); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_channel_mask); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_channel_mask_propagation_count); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask1); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask2); + CASE_SET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_SET_SDRAM_PARAM(mc_emem_arb_override); + CASE_SET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_SET_SDRAM_PARAM(mc_clken_override); + CASE_SET_SDRAM_PARAM(mc_emc_reg_mode); + CASE_SET_SDRAM_PARAM(mc_video_protect_bom); + CASE_SET_SDRAM_PARAM(mc_video_protect_size_mb); + CASE_SET_SDRAM_PARAM(mc_video_protect_vpr_override); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_bom); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_size_mb); + CASE_SET_SDRAM_PARAM(mc_video_protect_write_access); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_protect_write_access); + CASE_SET_SDRAM_PARAM(emc_ca_training_enable); + CASE_SET_SDRAM_PARAM(emc_ca_training_timing_cntl1); + CASE_SET_SDRAM_PARAM(emc_ca_training_timing_cntl2); + CASE_SET_SDRAM_PARAM(swizzle_rank_byte_encode); + CASE_SET_SDRAM_PARAM(boot_rom_patch_control); + CASE_SET_SDRAM_PARAM(boot_rom_patch_data); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs0); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs1); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs2); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs3); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs4); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs5); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs6); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs7); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse0); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse1); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse2); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse3); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse4); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse5); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse6); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse7); + CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs0); + CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs1); + CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs2); + CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs3); + CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs4); + CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs5); + CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs6); + CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs7); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dq0); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dq1); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dq2); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dq3); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte_cfg); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte0); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte1); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte2); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte3); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte_cfg); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte0); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte1); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte2); + CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte3); + CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack1a); + CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack1b); + CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack2a); + CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack2b); + CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack3); + CASE_SET_SDRAM_PARAM(ch1_emc_auto_cal_config); + CASE_SET_SDRAM_PARAM(ch1_emc_auto_cal_config2); + CASE_SET_SDRAM_PARAM(ch1_emc_auto_cal_config3); + CASE_SET_SDRAM_PARAM(ch1_emc_cdb_cntl1); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_addr0); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_addr1); + CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_addr2); + CASE_SET_SDRAM_PARAM(ch1_emc_fbio_spare); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_clk_pad_ctrl); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_clk_pad_ctrl2); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_cmd_pad_ctrl2); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_cmd_pad_ctrl3); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_cmd_pad_ctrl4); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dq_pad_ctrl); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dq_pad_ctrl2); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dqs_pad_ctrl); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dqs_pad_ctrl3); + CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dqs_pad_ctrl4); + + DEFAULT(); + } + return 0; +} + +int +t114_getbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_GET_BL_PARAM(version); + CASE_GET_BL_PARAM(start_blk); + CASE_GET_BL_PARAM(start_page); + CASE_GET_BL_PARAM(length); + CASE_GET_BL_PARAM(load_addr); + CASE_GET_BL_PARAM(entry_point); + CASE_GET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(data, + &(bct_ptr->bootloader[set].signature.crypto_hash), + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t114_setbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_SET_BL_PARAM(version); + CASE_SET_BL_PARAM(start_blk); + CASE_SET_BL_PARAM(start_page); + CASE_SET_BL_PARAM(length); + CASE_SET_BL_PARAM(load_addr); + CASE_SET_BL_PARAM(entry_point); + CASE_SET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(&(bct_ptr->bootloader[set].signature.crypto_hash), + data, + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t114_bct_get_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + nvboot_config_table samplebct; /* Used for computing offsets. */ + + /* + * Note: Not all queries require use of the BCT, so testing for a + * valid BCT is distributed within the code. + */ + if (data == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_GET_NVU32(boot_data_version); + CASE_GET_NVU32(block_size_log2); + CASE_GET_NVU32(page_size_log2); + CASE_GET_NVU32(partition_size); + CASE_GET_NVU32(num_param_sets); + CASE_GET_NVU32(num_sdram_sets); + CASE_GET_NVU32(bootloader_used); + CASE_GET_NVU32(odm_data); + + case token_block_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->block_size_log2; + break; + + case token_page_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->page_size_log2; + break; + + /* + * Constants. + */ + + CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); + CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); + + case token_crypto_hash: + memcpy(data, + &(bct_ptr->signature.crypto_hash), + sizeof(nvboot_hash)); + break; + + case token_reserved_offset: + *((uint32_t *)data) = (uint8_t *)&(samplebct.reserved) + - (uint8_t *)&samplebct; + break; + + case token_bct_size: + *((uint32_t *)data) = sizeof(nvboot_config_table); + break; + + CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); + + case token_crypto_offset: + /* Offset to region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)&(samplebct.random_aes_blk) + - (uint8_t *)&samplebct; + break; + + case token_crypto_length: + /* size of region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)bct_ptr + sizeof(nvboot_config_table) + - (uint8_t *)&(bct_ptr->random_aes_blk); + break; + + CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); + + CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); + CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); + + CASE_GET_CONST_PREFIX(memory_type_none, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr3, nvboot); + + default: + return -ENODATA; + } + return 0; +} + +int +t114_bct_set_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (bct == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_SET_NVU32(boot_data_version); + CASE_SET_NVU32(block_size_log2); + CASE_SET_NVU32(page_size_log2); + CASE_SET_NVU32(partition_size); + CASE_SET_NVU32(num_param_sets); + CASE_SET_NVU32(num_sdram_sets); + CASE_SET_NVU32(bootloader_used); + CASE_SET_NVU32(odm_data); + + default: + return -ENODATA; + } + + return 0; +} + +int +t114_bct_set_data(parse_token id, + uint8_t *data, + uint32_t length, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + + case token_crypto_hash: + if (length < sizeof(nvboot_hash)) return -ENODATA; + memcpy( &bct_ptr->signature.crypto_hash, data, sizeof(nvboot_hash) ); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int t114_get_bct_size() +{ + return sizeof(nvboot_config_table); +} + +int t114_bct_token_supported(parse_token token) +{ + int index; + + for (index = 0; index < ARRAY_SIZE(t114_root_token_list); index++) + if (t114_root_token_list[index] == token) + return 1; + + return 0; +} + +void t114_init_bad_block_table(build_image_context *context) +{ + uint32_t bytes_per_entry; + nvboot_badblock_table *table; + nvboot_config_table *bct; + + bct = (nvboot_config_table *)(context->bct); + + assert(context != NULL); + assert(bct != NULL); + + table = &bct->badblock_table; + + bytes_per_entry = ICEIL(context->partition_size, + NVBOOT_BAD_BLOCK_TABLE_SIZE); + table->block_size_log2 = context->block_size_log2; + table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), + table->block_size_log2); + table->entries_used = iceil_log2(context->partition_size, + table->virtual_blk_size_log2); +} + +cbootimage_soc_config tegra114_config = { + .init_bad_block_table = t114_init_bad_block_table, + .set_dev_param = t114_set_dev_param, + .get_dev_param = t114_get_dev_param, + .set_sdram_param = t114_set_sdram_param, + .get_sdram_param = t114_get_sdram_param, + .setbl_param = t114_setbl_param, + .getbl_param = t114_getbl_param, + .set_value = t114_bct_set_value, + .get_value = t114_bct_get_value, + .get_value_size = bct_get_unsupported, + .set_data = t114_bct_set_data, + .get_bct_size = t114_get_bct_size, + .token_supported = t114_bct_token_supported, + + .devtype_table = s_devtype_table_t114, + .sdmmc_data_width_table = s_sdmmc_data_width_table_t114, + .spi_clock_source_table = s_spi_clock_source_table_t114, + .nvboot_memory_type_table = s_nvboot_memory_type_table_t114, + .sdram_field_table = s_sdram_field_table_t114, + .nand_table = 0, + .sdmmc_table = s_sdmmc_table_t114, + .spiflash_table = s_spiflash_table_t114, + .device_type_table = s_device_type_table_t114, +}; + +void t114_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + context->boot_data_version = BOOTDATA_VERSION_T114; + *soc_config = &tegra114_config; +} + +int if_bct_is_t114_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + nvboot_config_table * bct = (nvboot_config_table *) context->bct; + + if (bct->boot_data_version == BOOTDATA_VERSION_T114) + { + t114_get_soc_config(context, soc_config); + return 1; + } + return 0; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t114/nvboot_bct_t114.h b/firmware/coreboot/util/nvidia/cbootimage/src/t114/nvboot_bct_t114.h new file mode 100644 index 0000000000..22450089c0 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t114/nvboot_bct_t114.h @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#ifndef INCLUDED_NVBOOT_BCT_T114_H +#define INCLUDED_NVBOOT_BCT_T114_H + +#include +#include "nvboot_sdram_param_t114.h" + +/** + * Defines the number of 32-bit words in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_WORDS 178 + +/** + * Defines the number of bytes in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_SIZE \ + (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) + +/** + * Defines the number of bytes in the reserved area of the BCT. + */ +#define NVBOOT_BCT_RESERVED_SIZE 2 + +/** + * Defines the maximum number of bootloader descriptions in the BCT. + */ +#define NVBOOT_MAX_BOOTLOADERS 4 + +/** + * Defines the maximum number of device parameter sets in the BCT. + * The value must be equal to (1 << # of device straps) + */ +#define NVBOOT_BCT_MAX_PARAM_SETS 4 + +/** + * Defines the maximum number of SDRAM parameter sets in the BCT. + * The value must be equal to (1 << # of SDRAM straps) + */ +#define NVBOOT_BCT_MAX_SDRAM_SETS 4 + +/** + * Defines the number of entries (bits) in the bad block table. + * The consequences of changing its value are as follows. Using P as the + * # of physical blocks in the boot loader and B as the value of this + * constant: + * B > P: There will be unused storage in the bad block table. + * B < P: The virtual block size will be greater than the physical block + * size, so the granularity of the bad block table will be less than + * one bit per physical block. + * + * 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one + * bit per block (1 virtual block = 1 physical block). This occupies 512 bytes + * of storage. + */ +#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096 + +/** + * Defines the amount of padding needed to pad the bad block table to a + * multiple of AES block size. + */ +#define NVBOOT_BAD_BLOCK_TABLE_PADDING 10 + +/** + * Defines the maximum number of blocks to search for BCTs. + * + * This value covers the initial block and a set of journal blocks. + * + * Ideally, this number will span several erase units for reliable updates + * and tolerance for blocks to become bad with use. Safe updates require + * a minimum of 2 erase units in which BCTs can appear. + * + * To ensure that the BCT search spans a sufficient range of configurations, + * the search block count has been set to 64. This allows for redundancy with + * a wide range of parts and provides room for greater problems in this + * region of the device. + */ +#define NVBOOT_MAX_BCT_SEARCH_BLOCKS 64 + +#define ARSE_RSA_MAX_MODULUS_SIZE 2048 + +/** + * Defines the RSA modulus length in bits and bytes used for PKC secure boot. + */ +enum {NVBOOT_SE_RSA_MODULUS_LENGTH_BITS = ARSE_RSA_MAX_MODULUS_SIZE}; + +/* + * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) + */ +enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; + +/** + * Defines the storage for a hash value (128 bits). + */ +typedef struct nvboot_hash_rec { + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; +} nvboot_hash; + +/* + * Defines the storage for the RSA public key's modulus + * in the BCT + */ +typedef struct nvboot_rsa_key_modulus_rec +{ + /// The modulus size is 2048-bits. + uint32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; +} nvboot_rsa_key_modulus; + +typedef struct nvboot_rsa_pss_sig_rec +{ + /* + * The RSA-PSS signature length is equal to the + * length in octets of the RSA modulus. + * In our case, it's 2048-bits. + */ + uint32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; +} nvboot_rsa_pss_sig; + +typedef union nvboot_object_signature_rec +{ + /* + * Specifies the AES-CMAC signature for the rest of the BCT structure if symmetric key + * encryption secure boot scheme is used. + */ + nvboot_hash crypto_hash; + + /* + * Specifies the RSASSA-PSS signature for the rest of the BCT structure if public + * key cryptography secure boot scheme is used. + */ + nvboot_rsa_pss_sig rsa_pss_sig; +} nvboot_object_signature; + +typedef struct nvboot_ecid_rec +{ + uint32_t ecid_0; + uint32_t ecid_1; + uint32_t ecid_2; + uint32_t ecid_3; +} nvboot_ecid; + +/* Defines various data widths supported. */ +typedef enum { + /** + * Specifies a 1 bit interface to eMMC. + * Note that 1-bit data width is only for the driver's internal use. + * Fuses doesn't provide option to select 1-bit data width. + * The driver selects 1-bit internally based on need. + * It is used for reading Extended CSD and when the power class + * requirements of a card for 4-bit or 8-bit transfers are not + * supported by the target board. + */ + nvboot_sdmmc_data_width_1bit = 0, + + /* Specifies a 4 bit interface to eMMC. */ + nvboot_sdmmc_data_width_4bit = 1, + + /* Specifies a 8 bit interface to eMMC. */ + nvboot_sdmmc_data_width_8bit = 2, + /* Specifies a 4 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_4bit = 5, + /* Specifies a 8 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_8bit = 6, + + nvboot_sdmmc_data_width_num, + nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF +} nvboot_sdmmc_data_width; + +/* Defines the parameters that can be changed after BCT is read. */ +typedef struct nvboot_sdmmc_params_rec { + /** + * Specifies the clock divider for the SDMMC controller's clock source, + * which is PLLP running at 216MHz. If it is set to 9, then the SDMMC + * controller runs at 216/9 = 24MHz. + */ + uint8_t clock_divider; + + /* Specifies the data bus width. Supported data widths are 4/8 bits. */ + nvboot_sdmmc_data_width data_width; + + /** + * Max Power class supported by the target board. + * The driver determines the best data width and clock frequency + * supported within the power class range (0 to Max) if the selected + * data width cannot be used at the chosen clock frequency. + */ + uint8_t max_power_class_supported; + + /* Specifies the max page size supported by driver */ + uint8_t multi_page_support; +} nvboot_sdmmc_params; + +typedef enum { + /* Specifies SPI clock source to be PLLP. */ + nvboot_spi_clock_source_pllp_out0 = 0, + + /* Specifies SPI clock source to be ClockM. */ + nvboot_spi_clock_source_clockm = 6, + + nvboot_spi_clock_source_num, + nvboot_spi_clock_source_force32 = 0x7FFFFFF +} nvboot_spi_clock_source; + +/** + * Defines the parameters SPI FLASH devices. + */ +typedef struct nvboot_spiflash_params_rec { + /** + * Specifies the clock source to use. + */ + uint32_t clock_source; + + /** + * Specifes the clock divider to use. + * The value is a 7-bit value based on an input clock of 432Mhz. + * Divider = (432+ DesiredFrequency-1)/DesiredFrequency; + * Typical values: + * NORMAL_READ at 20MHz: 22 + * FAST_READ at 33MHz: 14 + * FAST_READ at 40MHz: 11 + * FAST_READ at 50MHz: 9 + */ + uint8_t clock_divider; + + /** + * Specifies the type of command for read operations. + * NV_FALSE specifies a NORMAL_READ Command + * NV_TRUE specifies a FAST_READ Command + */ + uint8_t read_command_type_fast; + + /* 0 = 2k page size, 1 = 16K page size */ + uint8_t page_size_2k_or_16k; +} nvboot_spiflash_params; + +/** +* Defines the union of the parameters required by each device. +*/ +typedef union { + uint8_t size[64]; + /* Specifies optimized parameters for eMMC and eSD */ + nvboot_sdmmc_params sdmmc_params; + /* Specifies optimized parameters for SPI NOR */ + nvboot_spiflash_params spiflash_params; +} nvboot_dev_params; + +/** + * Identifies the types of devices from which the system booted. + * Used to identify primary and secondary boot devices. + * @note These no longer match the fuse API device values (for + * backward compatibility with AP15). + */ +typedef enum { + /* Specifies a default (unset) value. */ + nvboot_dev_type_none = 0, + + /* Specifies SPI NOR. */ + nvboot_dev_type_spi = 3, + + /* Specifies SDMMC (either eMMC or eSD). */ + nvboot_dev_type_sdmmc = 4, + + nvboot_dev_type_max, + + /* Ignore -- Forces compilers to make 32-bit enums. */ + nvboot_dev_type_force32 = 0x7FFFFFFF +} nvboot_dev_type; + +/** + * Stores information needed to locate and verify a boot loader. + * + * There is one \c nv_bootloader_info structure for each copy of a BL stored on + * the device. + */ +typedef struct nv_bootloader_info_rec { + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; + + /* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */ + nvboot_object_signature signature; +} nv_bootloader_info; + +/** + * Defines the bad block table structure stored in the BCT. + */ +typedef struct nvboot_badblock_table_rec { + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; + /* + * Add a reserved field as padding to make the bad block table structure + * a multiple of 16 bytes (AES block size). + */ + uint8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; +} nvboot_badblock_table; + +/** + * Contains the information needed to load BLs from the secondary boot device. + * + * - Supplying NumParamSets = 0 indicates not to load any of them. + * - Supplying NumDramSets = 0 indicates not to load any of them. + * - The \c random_aes_blk member exists to increase the difficulty of + * key attacks based on knowledge of this structure. + */ +typedef struct nvboot_config_table_rec { + nvboot_badblock_table badblock_table; + nvboot_rsa_key_modulus key; + nvboot_object_signature signature; + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + uint32_t odm_data; + uint32_t reserved1; + + /* START OF SIGNED SECTION OF THE BCT */ + nvboot_hash random_aes_blk; + nvboot_ecid unique_chip_id; + uint32_t boot_data_version; + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; + nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; + nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; + uint32_t num_sdram_sets; + nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; + + uint32_t bootloader_used; + nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; + + uint8_t enable_fail_back; + + /* + * Specify whether or not to enable JTAG access when the JTAG disable fuse + * has not been burned. + * SecureJtagControl = NV_FALSE (0) = Disable JTAG access. + * SecureJtagControl = NV_TRUE (1) = Enable JTAG access. + */ + uint8_t secure_jtag_control; + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; +} nvboot_config_table; +#endif /* #ifndef INCLUDED_NVBOOT_BCT_T114_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t114/nvboot_sdram_param_t114.h b/firmware/coreboot/util/nvidia/cbootimage/src/t114/nvboot_sdram_param_t114.h new file mode 100644 index 0000000000..1e3503fda2 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t114/nvboot_sdram_param_t114.h @@ -0,0 +1,806 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T114_H +#define INCLUDED_NVBOOT_SDRAM_PARAM_T114_H + +#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 + +typedef enum { + /* Specifies the memory type to be undefined */ + nvboot_memory_type_none = 0, + + /* Specifies the memory type to be DDR SDRAM */ + nvboot_memory_type_ddr = 0, + + /* Specifies the memory type to be LPDDR SDRAM */ + nvboot_memory_type_lpddr = 0, + + /* Specifies the memory type to be DDR2 SDRAM */ + nvboot_memory_type_ddr2 = 0, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + nvboot_memory_type_lpddr2, + + /* Specifies the memory type to be DDR3 SDRAM */ + nvboot_memory_type_ddr3, + + nvboot_memory_type_num, + nvboot_memory_type_force32 = 0x7FFFFFF +} nvboot_memory_type; + +/** + * Defines the SDRAM parameter structure + */ +typedef struct nvboot_sdram_params_rec { + /* sdram data structure generated by tool warmboot_code_gen */ + + /* Specifies the type of memory device */ + nvboot_memory_type memory_type; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t pllm_input_divider; + /* Specifies the N value for PllM */ + uint32_t pllm_feedback_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t pllm_stable_time; + /* Specifies misc. control bits */ + uint32_t pllm_setup_control; + /* Enables the Div by 2 */ + uint32_t pllm_select_div2; + /* Powers down VCO output Level shifter */ + uint32_t pllm_pdlshift_ph45; + /* Powers down VCO output Level shifter */ + uint32_t pllm_pdlshift_ph90; + /* Powers down VCO output Level shifter */ + uint32_t pllm_pdlshift_ph135; + /* Specifies value for Charge Pump Gain Control */ + uint32_t pllm_kcp; + /* Specifies VCO gain */ + uint32_t pllm_kvco; + /* Spare BCT param */ + uint32_t emc_bct_spare0; + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t emc_clock_source; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t emc_auto_cal_interval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t emc_auto_cal_config; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t emc_auto_cal_config2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t emc_auto_cal_config3; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t emc_auto_cal_wait; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t emc_adr_cfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t emc_pin_program_wait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t emc_pin_extra_wait; + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t emc_timing_control_wait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t emc_rc; + /* Specifies the value for EMC_RFC */ + uint32_t emc_rfc; + /* Specifies the value for EMC_RFC_SLR */ + uint32_t emc_rfc_slr; + /* Specifies the value for EMC_RAS */ + uint32_t emc_ras; + /* Specifies the value for EMC_RP */ + uint32_t emc_rp; + /* Specifies the value for EMC_R2R */ + uint32_t emc_r2r; + /* Specifies the value for EMC_W2W */ + uint32_t emc_w2w; + /* Specifies the value for EMC_R2W */ + uint32_t emc_r2w; + /* Specifies the value for EMC_R2W */ + uint32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + uint32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + uint32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + uint32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + uint32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + uint32_t emc_rext; + /* Specifies the value for EMC_WEXT */ + uint32_t emc_wext; + /* Specifies the value for EMC_WDV */ + uint32_t emc_wdv; + /* Specifies the value for EMC_WDV_MASK */ + uint32_t emc_wdv_mask; + /* Specifies the value for EMC_QUSE */ + uint32_t emc_quse; + /* Specifies the value for EMC_IBDLY */ + uint32_t emc_ibdly; + /* Specifies the value for EMC_EINPUT */ + uint32_t emc_einput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t emc_einput_duration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t emc_puterm_extra; + /* Specifies the value for EMC_CDB_CNTL_1 */ + uint32_t emc_cdb_cntl1; + /* Specifies the value for EMC_CDB_CNTL_2 */ + uint32_t emc_cdb_cntl2; + /* Specifies the value for EMC_QRST */ + uint32_t emc_qrst; + /* Specifies the value for EMC_QSAFE */ + uint32_t emc_qsafe; + /* Specifies the value for EMC_RDV */ + uint32_t emc_rdv; + /* Specifies the value for EMC_RDV_MASK */ + uint32_t emc_rdv_mask; + /* Specifies the value for EMC_CTT */ + uint32_t emc_ctt; + /* Specifies the value for EMC_CTT_DURATION */ + uint32_t emc_ctt_duration; + /* Specifies the value for EMC_REFRESH */ + uint32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t emc_prerefresh_req_cnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t emc_rw2pden; + /* Specifies the value for EMC_TXSR */ + uint32_t emc_txsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t emc_txsr_dll; + /* Specifies the value for EMC_TCKE */ + uint32_t emc_tcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t emc_tckesr; + /* Specifies the value for EMC_TPD */ + uint32_t emc_tpd; + /* Specifies the value for EMC_TFAW */ + uint32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + uint32_t emc_trefbw; + /* Specifies the value for EMC_QUSE_EXTRA */ + uint32_t emc_quse_extra; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + uint32_t emc_fbio_cfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t emc_fbio_spare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t emc_cfg_rsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t emc_mrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t emc_emrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t emc_emrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t emc_emrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t emc_mrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t emc_mrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t emc_mrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t emc_mrw4; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t emc_mrw_extra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t emc_warm_boot_mrw_extra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t emc_warm_boot_extramode_reg_write_enable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t emc_extramode_reg_write_enable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t emc_mrw_reset_ninit_wait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t emc_mrs_wait_cnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t emc_mrs_wait_cnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t emc_cfg2; + /* Specifies the value for EMC_DBG */ + uint32_t emc_dbg; + /* Specifies the value for EMC_CMDQ */ + uint32_t emc_cmd_q; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t emc_mc2emc_q; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t emc_dyn_self_ref_control; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t ahb_arbitration_xbar_ctrl_meminit_done; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t emc_cfg_dig_dll; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t emc_cfg_dig_dll_period; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t emc_dev_select; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t emc_sel_dpd_ctrl; + + /* Pads trimmer delays */ + + /* Specifies the value for EMC_DLL_XFORM_DQS0 */ + uint32_t emc_dll_xform_dqs0; + /* Specifies the value for EMC_DLL_XFORM_DQS1 */ + uint32_t emc_dll_xform_dqs1; + /* Specifies the value for EMC_DLL_XFORM_DQS2 */ + uint32_t emc_dll_xform_dqs2; + /* Specifies the value for EMC_DLL_XFORM_DQS3 */ + uint32_t emc_dll_xform_dqs3; + /* Specifies the value for EMC_DLL_XFORM_DQS4 */ + uint32_t emc_dll_xform_dqs4; + /* Specifies the value for EMC_DLL_XFORM_DQS5 */ + uint32_t emc_dll_xform_dqs5; + /* Specifies the value for EMC_DLL_XFORM_DQS6 */ + uint32_t emc_dll_xform_dqs6; + /* Specifies the value for EMC_DLL_XFORM_DQS7 */ + uint32_t emc_dll_xform_dqs7; + /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ + uint32_t emc_dll_xform_quse0; + /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ + uint32_t emc_dll_xform_quse1; + /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ + uint32_t emc_dll_xform_quse2; + /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ + uint32_t emc_dll_xform_quse3; + /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ + uint32_t emc_dll_xform_quse4; + /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ + uint32_t emc_dll_xform_quse5; + /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ + uint32_t emc_dll_xform_quse6; + /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ + uint32_t emc_dll_xform_quse7; + /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ + uint32_t emc_dll_xform_addr0; + /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ + uint32_t emc_dll_xform_addr1; + /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ + uint32_t emc_dll_xform_addr2; + /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ + uint32_t emc_dli_trim_tx_dqs0; + /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ + uint32_t emc_dli_trim_tx_dqs1; + /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ + uint32_t emc_dli_trim_tx_dqs2; + /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ + uint32_t emc_dli_trim_tx_dqs3; + /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ + uint32_t emc_dli_trim_tx_dqs4; + /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ + uint32_t emc_dli_trim_tx_dqs5; + /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ + uint32_t emc_dli_trim_tx_dqs6; + /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ + uint32_t emc_dli_trim_tx_dqs7; + /* Specifies the value for EMC_DLL_XFORM_DQ0 */ + uint32_t emc_dll_xform_dq0; + /* Specifies the value for EMC_DLL_XFORM_DQ1 */ + uint32_t emc_dll_xform_dq1; + /* Specifies the value for EMC_DLL_XFORM_DQ2 */ + uint32_t emc_dll_xform_dq2; + /* Specifies the value for EMC_DLL_XFORM_DQ3 */ + uint32_t emc_dll_xform_dq3; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t warm_boot_wait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + uint32_t emc_ctt_term_ctrl; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_write; + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_read; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t emc_zcal_interval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t emc_zcal_wait_cnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t emc_zcal_mrw_cmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t emc_mrs_reset_dll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t emc_zcal_init_dev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t emc_zcal_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t emc_zcal_init_wait; + /* Specifies the enable for ZQ calibration at cold boot */ + uint32_t emc_zcal_warm_cold_boot_enables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t emc_mrw_lpddr2zcal_warm_boot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t emc_zqcal_ddr3_warm_boot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t emc_zcal_warm_boot_wait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t emc_mrs_warm_boot_enable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t emc_mrs_reset_dll_wait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t emc_mrs_extra; + /* Specifies the extra MRS command at warm boot */ + uint32_t emc_warm_boot_mrs_extra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t emc_ddr2_wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t emc_clken_override; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t emc_extra_refresh_num; + /* Specifies the master override for all EMC clocks */ + uint32_t emc_clken_override_allwarm_boot; + /* Specifies the master override for all MC clocks */ + uint32_t mc_clken_override_allwarm_boot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t emc_cfg_dig_dll_period_warm_boot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t pmc_ddr_pwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t pmc_ddr_cfg; + /* Specifies the value for PMC_IO_DPD_REQ */ + uint32_t pmc_io_dpd_req; + /* Specifies the value for PMC_IO_DPD2_REQ */ + uint32_t pmc_io_dpd2_req; + /* Specifies the value for PMC_REG_SHORT */ + uint32_t pmc_reg_short; + /* Specifies the value for PMC_E_NO_VTTGEN */ + uint32_t pmc_eno_vtt_gen; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t pmc_no_io_power; + /* Specifies the value for EMC_XM2CMDPADCTRL */ + uint32_t emc_xm2cmd_pad_ctrl; + /* Specifies the value for EMC_XM2CMDPADCTRL2 */ + uint32_t emc_xm2cmd_pad_ctrl2; + /* Specifies the value for EMC_XM2CMDPADCTRL3 */ + uint32_t emc_xm2cmd_pad_ctrl3; + /* Specifies the value for EMC_XM2CMDPADCTRL4 */ + uint32_t emc_xm2cmd_pad_ctrl4; + /* Specifies the value for EMC_XM2DQSPADCTRL */ + uint32_t emc_xm2dqs_pad_ctrl; + /* Specifies the value for EMC_XM2DQSPADCTRL2 */ + uint32_t emc_xm2dqs_pad_ctrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL3 */ + uint32_t emc_xm2dqs_pad_ctrl3; + /* Specifies the value for EMC_XM2DQSPADCTRL4 */ + uint32_t emc_xm2dqs_pad_ctrl4; + /* Specifies the value for EMC_XM2DQPADCTRL */ + uint32_t emc_xm2dq_pad_ctrl; + /* Specifies the value for EMC_XM2DQPADCTRL2 */ + uint32_t emc_xm2dq_pad_ctrl2; + /* Specifies the value for EMC_XM2CLKPADCTRL */ + uint32_t emc_xm2clk_pad_ctrl; + /* Specifies the value for EMC_XM2CLKPADCTRL2 */ + uint32_t emc_xm2clk_pad_ctrl2; + /* Specifies the value for EMC_XM2COMPPADCTRL */ + uint32_t emc_xm2comp_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL */ + uint32_t emc_xm2vttgen_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ + uint32_t emc_xm2vttgen_pad_ctrl2; + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t emc_acpd_control; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ + uint32_t emc_swizzle_rank0_byte_cfg; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t emc_swizzle_rank0_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t emc_swizzle_rank0_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t emc_swizzle_rank0_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t emc_swizzle_rank0_byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ + uint32_t emc_swizzle_rank1_byte_cfg; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t emc_swizzle_rank1_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t emc_swizzle_rank1_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t emc_swizzle_rank1_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t emc_swizzle_rank1_byte3; + /* Specifies the value for EMC_ADDR_SWIZZLE_STACK1A */ + uint32_t emc_addr_swizzle_stack1a; + /* Specifies the value for EMC_ADDR_SWIZZLE_STACK1B */ + uint32_t emc_addr_swizzle_stack1b; + /* Specifies the value for EMC_ADDR_SWIZZLE_STACK2A */ + uint32_t emc_addr_swizzle_stack2a; + /* Specifies the value for EMC_ADDR_SWIZZLE_STACK2B */ + uint32_t emc_addr_swizzle_stack2b; + /* Specifies the value for EMC_ADDR_SWIZZLE_STACK3 */ + uint32_t emc_addr_swizzle_stack3; + + /* Specifies the value for EMC_DSR_VTTGEN_DRV */ + uint32_t emc_dsr_vttgen_drv; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t emc_txdsrvttgen; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t mc_emem_adr_cfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t mc_emem_adr_cfg_dev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t mc_emem_adr_cfg_dev1; + /* Specifies the value for MC_EMEM_ADR_CFG_CHANNEL_MASK */ + uint32_t mc_emem_adr_cfg_channel_mask; + /* Specifies the value for MC_EMEM_ADR_CFG_CHANNEL_MASK_PROPAGATION_COUNT */ + uint32_t mc_emem_adr_cfg_channel_mask_propagation_count; + /* Specifies the value for MC_EMEM_ADR_CFG_BANK_MASK_0 */ + uint32_t mc_emem_adr_cfg_bank_mask0; + /* Specifies the value for MC_EMEM_ADR_CFG_BANK_MASK_1 */ + uint32_t mc_emem_adr_cfg_bank_mask1; + /* Specifies the value for MC_EMEM_ADR_CFG_BANK_MASK_2 */ + uint32_t mc_emem_adr_cfg_bank_mask2; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t mc_emem_cfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t mc_emem_arb_cfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t mc_emem_arb_outstanding_req; + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t mc_emem_arb_timing_rcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t mc_emem_arb_timing_rp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t mc_emem_arb_timing_rc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t mc_emem_arb_timing_ras; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t mc_emem_arb_timing_faw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t mc_emem_arb_timing_rrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t mc_emem_arb_timing_rap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t mc_emem_arb_timing_wap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t mc_emem_arb_timing_r2r; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t mc_emem_arb_timing_w2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t mc_emem_arb_timing_r2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t mc_emem_arb_timing_w2r; + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t mc_emem_arb_da_turns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t mc_emem_arb_da_covers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t mc_emem_arb_misc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t mc_emem_arb_misc1; + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t mc_emem_arb_ring1_throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t mc_emem_arb_override; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t mc_emem_arb_rsv; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t mc_clken_override; + + /* Specifies the MC/EMC register address aperture */ + uint32_t mc_emc_reg_mode; + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t mc_video_protect_bom; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t mc_video_protect_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t mc_video_protect_vpr_override; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t mc_sec_carveout_bom; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t mc_sec_carveout_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ + uint32_t mc_video_protect_write_access; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ + uint32_t mc_sec_carveout_protect_write_access; + + /* Specifies enable for CA training */ + uint32_t emc_ca_training_enable; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ + uint32_t emc_ca_training_timing_cntl1; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ + uint32_t emc_ca_training_timing_cntl2; + /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t swizzle_rank_byte_encode; + /* Specifies enable and offset for patched boot rom write */ + uint32_t boot_rom_patch_control; + /* Specifies data for patched boot rom write */ + uint32_t boot_rom_patch_data; + + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQS0 */ + uint32_t ch1_emc_dll_xform_dqs0; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQS1 */ + uint32_t ch1_emc_dll_xform_dqs1; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQS2 */ + uint32_t ch1_emc_dll_xform_dqs2; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQS3 */ + uint32_t ch1_emc_dll_xform_dqs3; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQS4 */ + uint32_t ch1_emc_dll_xform_dqs4; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQS5 */ + uint32_t ch1_emc_dll_xform_dqs5; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQS6 */ + uint32_t ch1_emc_dll_xform_dqs6; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQS7 */ + uint32_t ch1_emc_dll_xform_dqs7; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_QUSE0 */ + uint32_t ch1_emc_dll_xform_quse0; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_QUSE1 */ + uint32_t ch1_emc_dll_xform_quse1; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_QUSE2 */ + uint32_t ch1_emc_dll_xform_quse2; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_QUSE3 */ + uint32_t ch1_emc_dll_xform_quse3; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_QUSE4 */ + uint32_t ch1_emc_dll_xform_quse4; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_QUSE5 */ + uint32_t ch1_emc_dll_xform_quse5; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_QUSE6 */ + uint32_t ch1_emc_dll_xform_quse6; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_QUSE7 */ + uint32_t ch1_emc_dll_xform_quse7; + /* (Channel 1) Specifies the value for EMC_DLI_TRIM_TXDQS0 */ + uint32_t ch1_emc_dli_trim_tx_dqs0; + /* (Channel 1) Specifies the value for EMC_DLI_TRIM_TXDQS1 */ + uint32_t ch1_emc_dli_trim_tx_dqs1; + /* (Channel 1) Specifies the value for EMC_DLI_TRIM_TXDQS2 */ + uint32_t ch1_emc_dli_trim_tx_dqs2; + /* (Channel 1) Specifies the value for EMC_DLI_TRIM_TXDQS3 */ + uint32_t ch1_emc_dli_trim_tx_dqs3; + /* (Channel 1) Specifies the value for EMC_DLI_TRIM_TXDQS4 */ + uint32_t ch1_emc_dli_trim_tx_dqs4; + /* (Channel 1) Specifies the value for EMC_DLI_TRIM_TXDQS5 */ + uint32_t ch1_emc_dli_trim_tx_dqs5; + /* (Channel 1) Specifies the value for EMC_DLI_TRIM_TXDQS6 */ + uint32_t ch1_emc_dli_trim_tx_dqs6; + /* (Channel 1) Specifies the value for EMC_DLI_TRIM_TXDQS7 */ + uint32_t ch1_emc_dli_trim_tx_dqs7; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQ0 */ + uint32_t ch1_emc_dll_xform_dq0; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQ1 */ + uint32_t ch1_emc_dll_xform_dq1; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQ2 */ + uint32_t ch1_emc_dll_xform_dq2; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_DQ3 */ + uint32_t ch1_emc_dll_xform_dq3; + + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ + uint32_t ch1_emc_swizzle_rank0_byte_cfg; + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t ch1_emc_swizzle_rank0_byte0; + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t ch1_emc_swizzle_rank0_byte1; + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t ch1_emc_swizzle_rank0_byte2; + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t ch1_emc_swizzle_rank0_byte3; + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ + uint32_t ch1_emc_swizzle_rank1_byte_cfg; + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t ch1_emc_swizzle_rank1_byte0; + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t ch1_emc_swizzle_rank1_byte1; + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t ch1_emc_swizzle_rank1_byte2; + /* (Channel 1) Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t ch1_emc_swizzle_rank1_byte3; + /* (Channel 1) Specifies the value for EMC_ADDR_SWIZZLE_STACK1A */ + uint32_t ch1_emc_addr_swizzle_stack1a; + /* (Channel 1) Specifies the value for EMC_ADDR_SWIZZLE_STACK1B */ + uint32_t ch1_emc_addr_swizzle_stack1b; + /* (Channel 1) Specifies the value for EMC_ADDR_SWIZZLE_STACK2A */ + uint32_t ch1_emc_addr_swizzle_stack2a; + /* (Channel 1) Specifies the value for EMC_ADDR_SWIZZLE_STACK2B */ + uint32_t ch1_emc_addr_swizzle_stack2b; + /* (Channel 1) Specifies the value for EMC_ADDR_SWIZZLE_STACK3 */ + uint32_t ch1_emc_addr_swizzle_stack3; + + /* (Channel 1) Specifies the value for EMC_AUTO_CAL_CONFIG */ + /* Note: Trigger bits are set by the SDRAM code. */ + uint32_t ch1_emc_auto_cal_config; + /* (Channel 1) Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t ch1_emc_auto_cal_config2; + /* (Channel 1) Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t ch1_emc_auto_cal_config3; + /* (Channel 1) Specifies the value for EMC_CDB_CNTL_1 */ + uint32_t ch1_emc_cdb_cntl1; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_ADDR0 */ + uint32_t ch1_emc_dll_xform_addr0; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_ADDR1 */ + uint32_t ch1_emc_dll_xform_addr1; + /* (Channel 1) Specifies the value for EMC_DLL_XFORM_ADDR2 */ + uint32_t ch1_emc_dll_xform_addr2; + /* (Channel 1) Specifies the value for EMC_FBIO_SPARE */ + uint32_t ch1_emc_fbio_spare; + /* (Channel 1) Specifies the value for EMC_XM2CLKPADCTRL */ + uint32_t ch1_emc_xm2_clk_pad_ctrl; + /* (Channel 1) Specifies the value for EMC_XM2CLKPADCTRL2 */ + uint32_t ch1_emc_xm2_clk_pad_ctrl2; + /* (Channel 1) Specifies the value for EMC_XM2CMDPADCTRL2 */ + uint32_t ch1_emc_xm2_cmd_pad_ctrl2; + /* (Channel 1) Specifies the value for EMC_XM2CMDPADCTRL3 */ + uint32_t ch1_emc_xm2_cmd_pad_ctrl3; + /* (Channel 1) Specifies the value for EMC_XM2CMDPADCTRL4 */ + uint32_t ch1_emc_xm2_cmd_pad_ctrl4; + /* (Channel 1) Specifies the value for EMC_XM2DQPADCTRL */ + uint32_t ch1_emc_xm2_dq_pad_ctrl; + /* (Channel 1) Specifies the value for EMC_XM2DQPADCTRL2 */ + uint32_t ch1_emc_xm2_dq_pad_ctrl2; + /* (Channel 1) Specifies the value for EMC_XM2DQSPADCTRL */ + uint32_t ch1_emc_xm2_dqs_pad_ctrl; + /* (Channel 1) Specifies the value for EMC_XM2DQSPADCTRL3 */ + uint32_t ch1_emc_xm2_dqs_pad_ctrl3; + /* (Channel 1) Specifies the value for EMC_XM2DQSPADCTRL4 */ + uint32_t ch1_emc_xm2_dqs_pad_ctrl4; + + /* End of generated code by warmboot_code_gen */ +} nvboot_sdram_params; +#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T114_H */ + diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t114/parse_t114.c b/firmware/coreboot/util/nvidia/cbootimage/src/t114/parse_t114.c new file mode 100644 index 0000000000..17f612e8c8 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t114/parse_t114.c @@ -0,0 +1,430 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * parse_t114.h - Definitions for the dev/sdram parameters + */ + +#include "../parse.h" +#include "nvboot_bct_t114.h" + +enum_item s_devtype_table_t114[] = { + { "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc }, + { "NvBootDevType_Spi", nvboot_dev_type_spi }, + { "Sdmmc", nvboot_dev_type_sdmmc }, + { "Spi", nvboot_dev_type_spi }, + { NULL, 0 } +}; + +enum_item s_sdmmc_data_width_table_t114[] = { + { + "NvBootSdmmcDataWidth_4Bit", + nvboot_sdmmc_data_width_4bit + }, + { + "NvBootSdmmcDataWidth_8Bit", + nvboot_sdmmc_data_width_8bit + }, + { "4Bit", nvboot_sdmmc_data_width_4bit }, + { "8Bit", nvboot_sdmmc_data_width_8bit }, + { NULL, 0 } +}; + +enum_item s_spi_clock_source_table_t114[] = { + { "NvBootSpiClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "NvBootSpiClockSource_ClockM", nvboot_spi_clock_source_clockm }, + { "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockSource_ClockM", nvboot_spi_clock_source_clockm }, + { "PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockM", nvboot_spi_clock_source_clockm }, + { NULL, 0 } +}; + +enum_item s_nvboot_memory_type_table_t114[] = { + { "NvBootMemoryType_None", nvboot_memory_type_none }, + { "NvBootMemoryType_Ddr3", nvboot_memory_type_ddr3 }, + { "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 }, + { "NvBootMemoryType_Ddr", nvboot_memory_type_ddr }, + { "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 }, + { "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr }, + + { "None", nvboot_memory_type_none }, + { "Ddr3", nvboot_memory_type_ddr3 }, + { "Ddr2", nvboot_memory_type_ddr2 }, + { "Ddr", nvboot_memory_type_ddr }, + { "LpDdr2", nvboot_memory_type_lpddr2 }, + { "LpDdr", nvboot_memory_type_lpddr }, + + { NULL, 0 } +}; + +#define TOKEN(name) \ + token_##name, field_type_u32, NULL + +field_item s_sdram_field_table_t114[] = { + { "MemoryType", token_memory_type, + field_type_enum, s_nvboot_memory_type_table_t114 }, + + { "PllMInputDivider", TOKEN(pllm_input_divider) }, + { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, + { "PllMStableTime", TOKEN(pllm_stable_time) }, + { "PllMSetupControl", TOKEN(pllm_setup_control) }, + { "PllMSelectDiv2", TOKEN(pllm_select_div2) }, + { "PllMPDLshiftPh45", TOKEN(pllm_pdlshift_ph45) }, + { "PllMPDLshiftPh90", TOKEN(pllm_pdlshift_ph90) }, + { "PllMPDLshiftPh135", TOKEN(pllm_pdlshift_ph135) }, + { "PllMKCP", TOKEN(pllm_kcp) }, + { "PllMKVCO", TOKEN(pllm_kvco) }, + { "EmcBctSpare0", TOKEN(emc_bct_spare0) }, + { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, + { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, + { "EmcAutoCalConfig2", TOKEN(emc_auto_cal_config2) }, + { "EmcAutoCalConfig3", TOKEN(emc_auto_cal_config3) }, + { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, + { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, + { "EmcRc", TOKEN(emc_rc) }, + { "EmcRfc", TOKEN(emc_rfc) }, + { "EmcRfcSlr", TOKEN(emc_rfc_slr) }, + { "EmcRas", TOKEN(emc_ras) }, + { "EmcRp", TOKEN(emc_rp) }, + { "EmcR2r", TOKEN(emc_r2r) }, + { "EmcW2w", TOKEN(emc_w2w) }, + { "EmcR2w", TOKEN(emc_r2w) }, + { "EmcW2r", TOKEN(emc_w2r) }, + { "EmcR2p", TOKEN(emc_r2p) }, + { "EmcW2p", TOKEN(emc_w2p) }, + { "EmcRrd", TOKEN(emc_rrd) }, + { "EmcRdRcd", TOKEN(emc_rd_rcd) }, + { "EmcWrRcd", TOKEN(emc_wr_rcd) }, + { "EmcRext", TOKEN(emc_rext) }, + { "EmcWdv", TOKEN(emc_wdv) }, + { "EmcWdvMask", TOKEN(emc_wdv_mask) }, + { "EmcQUseExtra", TOKEN(emc_quse_extra) }, + { "EmcQUse", TOKEN(emc_quse) }, + { "EmcIbdly", TOKEN(emc_ibdly) }, + { "EmcEInput", TOKEN(emc_einput) }, + { "EmcEInputDuration", TOKEN(emc_einput_duration) }, + { "EmcPutermExtra", TOKEN(emc_puterm_extra) }, + { "EmcCdbCntl1", TOKEN(emc_cdb_cntl1) }, + { "EmcCdbCntl2", TOKEN(emc_cdb_cntl2) }, + { "EmcQRst", TOKEN(emc_qrst) }, + { "EmcQSafe", TOKEN(emc_qsafe) }, + { "EmcRdv", TOKEN(emc_rdv) }, + { "EmcRdvMask", TOKEN(emc_rdv_mask) }, + { "EmcRefresh", TOKEN(emc_refresh) }, + { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, + { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, + { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, + { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, + { "EmcAct2Pden", TOKEN(emc_act2pden) }, + { "EmcAr2Pden", TOKEN(emc_ar2pden) }, + { "EmcRw2Pden", TOKEN(emc_rw2pden) }, + { "EmcTxsr", TOKEN(emc_txsr) }, + { "EmcTcke", TOKEN(emc_tcke) }, + { "EmcTckesr", TOKEN(emc_tckesr) }, + { "EmcTpd", TOKEN(emc_tpd) }, + { "EmcTfaw", TOKEN(emc_tfaw) }, + { "EmcTrpab", TOKEN(emc_trpab) }, + { "EmcTClkStable", TOKEN(emc_tclkstable) }, + { "EmcTClkStop", TOKEN(emc_tclkstop) }, + { "EmcTRefBw", TOKEN(emc_trefbw) }, + { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, + { "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) }, + { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, + { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, + { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, + { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, + { "EmcMrs", TOKEN(emc_mrs) }, + { "EmcEmrs2", TOKEN(emc_emrs2) }, + { "EmcEmrs3", TOKEN(emc_emrs3) }, + { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, + { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, + { "EmcEmrs", TOKEN(emc_emrs) }, + { "EmcMrw1", TOKEN(emc_mrw1) }, + { "EmcMrw2", TOKEN(emc_mrw2) }, + { "EmcMrw3", TOKEN(emc_mrw3) }, + { "EmcMrw4", TOKEN(emc_mrw4) }, + { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, + { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, + { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, + { "McEmemCfg", TOKEN(mc_emem_cfg) }, + { "EmcCfg2", TOKEN(emc_cfg2) }, + { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, + { "EmcCfgDigDllPeriod", TOKEN(emc_cfg_dig_dll_period) }, + { "EmcCfg", TOKEN(emc_cfg) }, + { "EmcDbg", TOKEN(emc_dbg) }, + { "WarmBootWait", TOKEN(warm_boot_wait) }, + { "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) }, + { "EmcOdtWrite", TOKEN(emc_odt_write) }, + { "EmcOdtRead", TOKEN(emc_odt_read) }, + { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, + { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, + { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, + { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, + { "EmcClockSource", TOKEN(emc_clock_source) }, + { "EmcPinExtraWait", TOKEN(emc_pin_extra_wait) }, + { "EmcTimingControlWait", TOKEN(emc_timing_control_wait) }, + { "EmcWext", TOKEN(emc_wext) }, + { "EmcCtt", TOKEN(emc_ctt) }, + { "EmcCttDuration", TOKEN(emc_ctt_duration) }, + { "EmcPreRefreshReqCnt", TOKEN(emc_prerefresh_req_cnt) }, + { "EmcTxsrDll", TOKEN(emc_txsr_dll) }, + { "EmcCfgRsv", TOKEN(emc_cfg_rsv) }, + { "EmcMrwExtra", TOKEN(emc_mrw_extra) }, + { "EmcWarmBootMrwExtra", TOKEN(emc_warm_boot_mrw_extra) }, + { "EmcWarmBootExtraModeRegWriteEnable", + TOKEN(emc_warm_boot_extramode_reg_write_enable) }, + { "EmcExtraModeRegWriteEnable", TOKEN(emc_extramode_reg_write_enable) }, + { "EmcMrsWaitCnt", TOKEN(emc_mrs_wait_cnt) }, + { "EmcMrsWaitCnt2", TOKEN(emc_mrs_wait_cnt2) }, + { "EmcCmdQ", TOKEN(emc_cmd_q) }, + { "EmcMc2EmcQ", TOKEN(emc_mc2emc_q) }, + { "EmcDynSelfRefControl", TOKEN(emc_dyn_self_ref_control) }, + { "AhbArbitrationXbarCtrlMemInitDone", + TOKEN(ahb_arbitration_xbar_ctrl_meminit_done) }, + { "EmcDevSelect", TOKEN(emc_dev_select) }, + { "EmcSelDpdCtrl", TOKEN(emc_sel_dpd_ctrl) }, + { "EmcDllXformDqs0", TOKEN(emc_dll_xform_dqs0) }, + { "EmcDllXformDqs1", TOKEN(emc_dll_xform_dqs1) }, + { "EmcDllXformDqs2", TOKEN(emc_dll_xform_dqs2) }, + { "EmcDllXformDqs3", TOKEN(emc_dll_xform_dqs3) }, + { "EmcDllXformDqs4", TOKEN(emc_dll_xform_dqs4) }, + { "EmcDllXformDqs5", TOKEN(emc_dll_xform_dqs5) }, + { "EmcDllXformDqs6", TOKEN(emc_dll_xform_dqs6) }, + { "EmcDllXformDqs7", TOKEN(emc_dll_xform_dqs7) }, + { "EmcDllXformQUse0", TOKEN(emc_dll_xform_quse0) }, + { "EmcDllXformQUse1", TOKEN(emc_dll_xform_quse1) }, + { "EmcDllXformQUse2", TOKEN(emc_dll_xform_quse2) }, + { "EmcDllXformQUse3", TOKEN(emc_dll_xform_quse3) }, + { "EmcDllXformQUse4", TOKEN(emc_dll_xform_quse4) }, + { "EmcDllXformQUse5", TOKEN(emc_dll_xform_quse5) }, + { "EmcDllXformQUse6", TOKEN(emc_dll_xform_quse6) }, + { "EmcDllXformQUse7", TOKEN(emc_dll_xform_quse7) }, + { "EmcDllXformAddr0", TOKEN(emc_dll_xform_addr0) }, + { "EmcDllXformAddr1", TOKEN(emc_dll_xform_addr1) }, + { "EmcDllXformAddr2", TOKEN(emc_dll_xform_addr2) }, + { "EmcDliTrimTxDqs0", TOKEN(emc_dli_trim_tx_dqs0) }, + { "EmcDliTrimTxDqs1", TOKEN(emc_dli_trim_tx_dqs1) }, + { "EmcDliTrimTxDqs2", TOKEN(emc_dli_trim_tx_dqs2) }, + { "EmcDliTrimTxDqs3", TOKEN(emc_dli_trim_tx_dqs3) }, + { "EmcDliTrimTxDqs4", TOKEN(emc_dli_trim_tx_dqs4) }, + { "EmcDliTrimTxDqs5", TOKEN(emc_dli_trim_tx_dqs5) }, + { "EmcDliTrimTxDqs6", TOKEN(emc_dli_trim_tx_dqs6) }, + { "EmcDliTrimTxDqs7", TOKEN(emc_dli_trim_tx_dqs7) }, + { "EmcDllXformDq0", TOKEN(emc_dll_xform_dq0) }, + { "EmcDllXformDq1", TOKEN(emc_dll_xform_dq1) }, + { "EmcDllXformDq2", TOKEN(emc_dll_xform_dq2) }, + { "EmcDllXformDq3", TOKEN(emc_dll_xform_dq3) }, + { "EmcZcalInterval", TOKEN(emc_zcal_interval) }, + { "EmcZcalInitDev0", TOKEN(emc_zcal_init_dev0) }, + { "EmcZcalInitDev1", TOKEN(emc_zcal_init_dev1) }, + { "EmcZcalInitWait", TOKEN(emc_zcal_init_wait) }, + { "EmcZcalWarmColdBootEnables", TOKEN(emc_zcal_warm_cold_boot_enables) }, + { "EmcMrwLpddr2ZcalWarmBoot", TOKEN(emc_mrw_lpddr2zcal_warm_boot) }, + { "EmcZqCalDdr3WarmBoot", TOKEN(emc_zqcal_ddr3_warm_boot) }, + { "EmcZcalWarmBootWait", TOKEN(emc_zcal_warm_boot_wait) }, + { "EmcMrsWarmBootEnable", TOKEN(emc_mrs_warm_boot_enable) }, + { "EmcMrsExtra", TOKEN(emc_mrs_extra) }, + { "EmcWarmBootMrsExtra", TOKEN(emc_warm_boot_mrs_extra) }, + { "EmcClkenOverride", TOKEN(emc_clken_override) }, + { "EmcExtraRefreshNum", TOKEN(emc_extra_refresh_num) }, + { "EmcClkenOverrideAllWarmBoot", + TOKEN(emc_clken_override_allwarm_boot) }, + { "McClkenOverrideAllWarmBoot", TOKEN(mc_clken_override_allwarm_boot) }, + { "EmcCfgDigDllPeriodWarmBoot", + TOKEN(emc_cfg_dig_dll_period_warm_boot) }, + { "PmcVddpSel", TOKEN(pmc_vddp_sel) }, + { "PmcDdrCfg", TOKEN(pmc_ddr_cfg) }, + { "PmcIoDpdReq", TOKEN(pmc_io_dpd_req) }, + { "PmcIoDpd2Req", TOKEN(pmc_io_dpd2_req) }, + { "PmcRegShort", TOKEN(pmc_reg_short) }, + { "PmcENoVttGen", TOKEN(pmc_eno_vtt_gen) }, + { "PmcNoIoPower", TOKEN(pmc_no_io_power) }, + { "EmcXm2CmdPadCtrl", TOKEN(emc_xm2cmd_pad_ctrl) }, + { "EmcXm2CmdPadCtrl2", TOKEN(emc_xm2cmd_pad_ctrl2) }, + { "EmcXm2CmdPadCtrl3", TOKEN(emc_xm2cmd_pad_ctrl3) }, + { "EmcXm2CmdPadCtrl4", TOKEN(emc_xm2cmd_pad_ctrl4) }, + { "EmcXm2DqsPadCtrl", TOKEN(emc_xm2dqs_pad_ctrl) }, + { "EmcXm2DqsPadCtrl2", TOKEN(emc_xm2dqs_pad_ctrl2) }, + { "EmcXm2DqsPadCtrl3", TOKEN(emc_xm2dqs_pad_ctrl3) }, + { "EmcXm2DqsPadCtrl4", TOKEN(emc_xm2dqs_pad_ctrl4) }, + { "EmcXm2DqPadCtrl", TOKEN(emc_xm2dq_pad_ctrl) }, + { "EmcXm2DqPadCtrl2", TOKEN(emc_xm2dq_pad_ctrl2) }, + { "EmcXm2ClkPadCtrl", TOKEN(emc_xm2clk_pad_ctrl) }, + { "EmcXm2ClkPadCtrl2", TOKEN(emc_xm2clk_pad_ctrl2) }, + { "EmcXm2CompPadCtrl", TOKEN(emc_xm2comp_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl", TOKEN(emc_xm2vttgen_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl2", TOKEN(emc_xm2vttgen_pad_ctrl2) }, + { "EmcAcpdControl", TOKEN(emc_acpd_control) }, + { "EmcSwizzleRank0ByteCfg", TOKEN(emc_swizzle_rank0_byte_cfg) }, + { "EmcSwizzleRank0Byte0", TOKEN(emc_swizzle_rank0_byte0) }, + { "EmcSwizzleRank0Byte1", TOKEN(emc_swizzle_rank0_byte1) }, + { "EmcSwizzleRank0Byte2", TOKEN(emc_swizzle_rank0_byte2) }, + { "EmcSwizzleRank0Byte3", TOKEN(emc_swizzle_rank0_byte3) }, + { "EmcSwizzleRank1ByteCfg", TOKEN(emc_swizzle_rank1_byte_cfg) }, + { "EmcSwizzleRank1Byte0", TOKEN(emc_swizzle_rank1_byte0) }, + { "EmcSwizzleRank1Byte1", TOKEN(emc_swizzle_rank1_byte1) }, + { "EmcSwizzleRank1Byte2", TOKEN(emc_swizzle_rank1_byte2) }, + { "EmcSwizzleRank1Byte3", TOKEN(emc_swizzle_rank1_byte3) }, + { "EmcAddrSwizzleStack1a", TOKEN(emc_addr_swizzle_stack1a) }, + { "EmcAddrSwizzleStack1b", TOKEN(emc_addr_swizzle_stack1b) }, + { "EmcAddrSwizzleStack2a", TOKEN(emc_addr_swizzle_stack2a) }, + { "EmcAddrSwizzleStack2b", TOKEN(emc_addr_swizzle_stack2b) }, + { "EmcAddrSwizzleStack3", TOKEN(emc_addr_swizzle_stack3) }, + { "EmcDsrVttgenDrv", TOKEN(emc_dsr_vttgen_drv) }, + { "EmcTxdsrvttgen", TOKEN(emc_txdsrvttgen) }, + { "McEmemAdrCfg", TOKEN(mc_emem_adr_cfg) }, + { "McEmemAdrCfgDev0", TOKEN(mc_emem_adr_cfg_dev0) }, + { "McEmemAdrCfgDev1", TOKEN(mc_emem_adr_cfg_dev1) }, + { "McEmemAdrCfgChannelMask", TOKEN(mc_emem_adr_cfg_channel_mask) }, + { "McEmemAdrCfgChannelMaskPropagationCount", + TOKEN(mc_emem_adr_cfg_channel_mask_propagation_count) }, + { "McEmemAdrCfgBankMask0", TOKEN(mc_emem_adr_cfg_bank_mask0) }, + { "McEmemAdrCfgBankMask1", TOKEN(mc_emem_adr_cfg_bank_mask1) }, + { "McEmemAdrCfgBankMask2", TOKEN(mc_emem_adr_cfg_bank_mask2) }, + { "McEmemArbCfg", TOKEN(mc_emem_arb_cfg) }, + { "McEmemArbOutstandingReq", TOKEN(mc_emem_arb_outstanding_req) }, + { "McEmemArbTimingRcd", TOKEN(mc_emem_arb_timing_rcd) }, + { "McEmemArbTimingRp", TOKEN(mc_emem_arb_timing_rp) }, + { "McEmemArbTimingRc", TOKEN(mc_emem_arb_timing_rc) }, + { "McEmemArbTimingRas", TOKEN(mc_emem_arb_timing_ras) }, + { "McEmemArbTimingFaw", TOKEN(mc_emem_arb_timing_faw) }, + { "McEmemArbTimingRrd", TOKEN(mc_emem_arb_timing_rrd) }, + { "McEmemArbTimingRap2Pre", TOKEN(mc_emem_arb_timing_rap2pre) }, + { "McEmemArbTimingWap2Pre", TOKEN(mc_emem_arb_timing_wap2pre) }, + { "McEmemArbTimingR2R", TOKEN(mc_emem_arb_timing_r2r) }, + { "McEmemArbTimingW2W", TOKEN(mc_emem_arb_timing_w2w) }, + { "McEmemArbTimingR2W", TOKEN(mc_emem_arb_timing_r2w) }, + { "McEmemArbTimingW2R", TOKEN(mc_emem_arb_timing_w2r) }, + { "McEmemArbDaTurns", TOKEN(mc_emem_arb_da_turns) }, + { "McEmemArbDaCovers", TOKEN(mc_emem_arb_da_covers) }, + { "McEmemArbMisc0", TOKEN(mc_emem_arb_misc0) }, + { "McEmemArbMisc1", TOKEN(mc_emem_arb_misc1) }, + { "McEmemArbRing1Throttle", TOKEN(mc_emem_arb_ring1_throttle) }, + { "McEmemArbOverride", TOKEN(mc_emem_arb_override) }, + { "McEmemArbRsv", TOKEN(mc_emem_arb_rsv) }, + { "McClkenOverride", TOKEN(mc_clken_override) }, + { "McEmcRegMode", TOKEN(mc_emc_reg_mode) }, + { "McVideoProtectBom", TOKEN(mc_video_protect_bom) }, + { "McVideoProtectSizeMb", TOKEN(mc_video_protect_size_mb) }, + { "McVideoProtectVprOverride", TOKEN(mc_video_protect_vpr_override) }, + { "McSecCarveoutBom", TOKEN(mc_sec_carveout_bom) }, + { "McSecCarveoutSizeMb", TOKEN(mc_sec_carveout_size_mb) }, + { "McVideoProtectWriteAccess", TOKEN(mc_video_protect_write_access) }, + { "McSecCarveoutProtectWriteAccess", + TOKEN(mc_sec_carveout_protect_write_access) }, + { "EmcCaTrainingEnable", TOKEN(emc_ca_training_enable) }, + { "EmcCaTrainingTimingCntl1", TOKEN(emc_ca_training_timing_cntl1) }, + { "EmcCaTrainingTimingCntl2", TOKEN(emc_ca_training_timing_cntl2) }, + { "SwizzleRankByteEncode", TOKEN(swizzle_rank_byte_encode) }, + { "BootRomPatchControl", TOKEN(boot_rom_patch_control) }, + { "BootRomPatchData", TOKEN(boot_rom_patch_data) }, + { "Ch1EmcDllXformDqs0", TOKEN(ch1_emc_dll_xform_dqs0) }, + { "Ch1EmcDllXformDqs1", TOKEN(ch1_emc_dll_xform_dqs1) }, + { "Ch1EmcDllXformDqs2", TOKEN(ch1_emc_dll_xform_dqs2) }, + { "Ch1EmcDllXformDqs3", TOKEN(ch1_emc_dll_xform_dqs3) }, + { "Ch1EmcDllXformDqs4", TOKEN(ch1_emc_dll_xform_dqs4) }, + { "Ch1EmcDllXformDqs5", TOKEN(ch1_emc_dll_xform_dqs5) }, + { "Ch1EmcDllXformDqs6", TOKEN(ch1_emc_dll_xform_dqs6) }, + { "Ch1EmcDllXformDqs7", TOKEN(ch1_emc_dll_xform_dqs7) }, + { "Ch1EmcDllXformQUse0", TOKEN(ch1_emc_dll_xform_quse0) }, + { "Ch1EmcDllXformQUse1", TOKEN(ch1_emc_dll_xform_quse1) }, + { "Ch1EmcDllXformQUse2", TOKEN(ch1_emc_dll_xform_quse2) }, + { "Ch1EmcDllXformQUse3", TOKEN(ch1_emc_dll_xform_quse3) }, + { "Ch1EmcDllXformQUse4", TOKEN(ch1_emc_dll_xform_quse4) }, + { "Ch1EmcDllXformQUse5", TOKEN(ch1_emc_dll_xform_quse5) }, + { "Ch1EmcDllXformQUse6", TOKEN(ch1_emc_dll_xform_quse6) }, + { "Ch1EmcDllXformQUse7", TOKEN(ch1_emc_dll_xform_quse7) }, + { "Ch1EmcDliTrimTxDqs0", TOKEN(ch1_emc_dli_trim_tx_dqs0) }, + { "Ch1EmcDliTrimTxDqs1", TOKEN(ch1_emc_dli_trim_tx_dqs1) }, + { "Ch1EmcDliTrimTxDqs2", TOKEN(ch1_emc_dli_trim_tx_dqs2) }, + { "Ch1EmcDliTrimTxDqs3", TOKEN(ch1_emc_dli_trim_tx_dqs3) }, + { "Ch1EmcDliTrimTxDqs4", TOKEN(ch1_emc_dli_trim_tx_dqs4) }, + { "Ch1EmcDliTrimTxDqs5", TOKEN(ch1_emc_dli_trim_tx_dqs5) }, + { "Ch1EmcDliTrimTxDqs6", TOKEN(ch1_emc_dli_trim_tx_dqs6) }, + { "Ch1EmcDliTrimTxDqs7", TOKEN(ch1_emc_dli_trim_tx_dqs7) }, + { "Ch1EmcDllXformDq0", TOKEN(ch1_emc_dll_xform_dq0) }, + { "Ch1EmcDllXformDq1", TOKEN(ch1_emc_dll_xform_dq1) }, + { "Ch1EmcDllXformDq2", TOKEN(ch1_emc_dll_xform_dq2) }, + { "Ch1EmcDllXformDq3", TOKEN(ch1_emc_dll_xform_dq3) }, + { "Ch1EmcSwizzleRank0ByteCfg", TOKEN(ch1_emc_swizzle_rank0_byte_cfg) }, + { "Ch1EmcSwizzleRank0Byte0", TOKEN(ch1_emc_swizzle_rank0_byte0) }, + { "Ch1EmcSwizzleRank0Byte1", TOKEN(ch1_emc_swizzle_rank0_byte1) }, + { "Ch1EmcSwizzleRank0Byte2", TOKEN(ch1_emc_swizzle_rank0_byte2) }, + { "Ch1EmcSwizzleRank0Byte3", TOKEN(ch1_emc_swizzle_rank0_byte3) }, + { "Ch1EmcSwizzleRank1ByteCfg", TOKEN(ch1_emc_swizzle_rank1_byte_cfg) }, + { "Ch1EmcSwizzleRank1Byte0", TOKEN(ch1_emc_swizzle_rank1_byte0) }, + { "Ch1EmcSwizzleRank1Byte1", TOKEN(ch1_emc_swizzle_rank1_byte1) }, + { "Ch1EmcSwizzleRank1Byte2", TOKEN(ch1_emc_swizzle_rank1_byte2) }, + { "Ch1EmcSwizzleRank1Byte3", TOKEN(ch1_emc_swizzle_rank1_byte3) }, + { "Ch1EmcAddrSwizzleStack1a", TOKEN(ch1_emc_addr_swizzle_stack1a) }, + { "Ch1EmcAddrSwizzleStack1b", TOKEN(ch1_emc_addr_swizzle_stack1b) }, + { "Ch1EmcAddrSwizzleStack2a", TOKEN(ch1_emc_addr_swizzle_stack2a) }, + { "Ch1EmcAddrSwizzleStack2b", TOKEN(ch1_emc_addr_swizzle_stack2b) }, + { "Ch1EmcAddrSwizzleStack3", TOKEN(ch1_emc_addr_swizzle_stack3) }, + { "Ch1EmcAutoCalConfig", TOKEN(ch1_emc_auto_cal_config) }, + { "Ch1EmcAutoCalConfig2", TOKEN(ch1_emc_auto_cal_config2) }, + { "Ch1EmcAutoCalConfig3", TOKEN(ch1_emc_auto_cal_config3) }, + { "Ch1EmcCdbCntl1", TOKEN(ch1_emc_cdb_cntl1) }, + { "Ch1EmcDllXformAddr0", TOKEN(ch1_emc_dll_xform_addr0) }, + { "Ch1EmcDllXformAddr1", TOKEN(ch1_emc_dll_xform_addr1) }, + { "Ch1EmcDllXformAddr2", TOKEN(ch1_emc_dll_xform_addr2) }, + { "Ch1EmcFbioSpare", TOKEN(ch1_emc_fbio_spare) }, + { "Ch1EmcXm2ClkPadCtrl", TOKEN(ch1_emc_xm2_clk_pad_ctrl) }, + { "Ch1EmcXm2ClkPadCtrl2", TOKEN(ch1_emc_xm2_clk_pad_ctrl2) }, + { "Ch1EmcXm2CmdPadCtrl2", TOKEN(ch1_emc_xm2_cmd_pad_ctrl2) }, + { "Ch1EmcXm2CmdPadCtrl3", TOKEN(ch1_emc_xm2_cmd_pad_ctrl3) }, + { "Ch1EmcXm2CmdPadCtrl4", TOKEN(ch1_emc_xm2_cmd_pad_ctrl4) }, + { "Ch1EmcXm2DqPadCtrl", TOKEN(ch1_emc_xm2_dq_pad_ctrl) }, + { "Ch1EmcXm2DqPadCtrl2", TOKEN(ch1_emc_xm2_dq_pad_ctrl2) }, + { "Ch1EmcXm2DqsPadCtrl", TOKEN(ch1_emc_xm2_dqs_pad_ctrl) }, + { "Ch1EmcXm2DqsPadCtrl3", TOKEN(ch1_emc_xm2_dqs_pad_ctrl3) }, + { "Ch1EmcXm2DqsPadCtrl4", TOKEN(ch1_emc_xm2_dqs_pad_ctrl4) }, + { NULL, 0, 0, NULL } +}; + +field_item s_sdmmc_table_t114[] = { + { "ClockDivider", TOKEN(sdmmc_clock_divider) }, + { "DataWidth", + token_sdmmc_data_width, + field_type_enum, + s_sdmmc_data_width_table_t114 }, + { "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) }, + { "MultiPageSupport", TOKEN(sdmmc_multi_page_support) }, + { NULL, 0, 0, NULL } +}; + +field_item s_spiflash_table_t114[] = { + { "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) }, + { "PageSize2kor16k", TOKEN(spiflash_page_size_2k_or_16k) }, + { "ClockDivider", TOKEN(spiflash_clock_divider) }, + { "ClockSource", + token_spiflash_clock_source, + field_type_enum, + s_spi_clock_source_table_t114 }, + { NULL, 0, 0, NULL } +}; + +parse_subfield_item s_device_type_table_t114[] = { + { "SdmmcParams.", token_sdmmc_params, + s_sdmmc_table_t114, t114_set_dev_param }, + { "SpiFlashParams.", token_spiflash_params, + s_spiflash_table_t114, t114_set_dev_param }, + { NULL, 0, NULL } +}; diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t124/nvbctlib_t124.c b/firmware/coreboot/util/nvidia/cbootimage/src/t124/nvbctlib_t124.c new file mode 100644 index 0000000000..577a909c0b --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t124/nvbctlib_t124.c @@ -0,0 +1,1223 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include "../cbootimage.h" +#include "../parse.h" +#include "../crypto.h" +#include "nvboot_bct_t124.h" +#include "string.h" + +/* nvbctlib_t124.c: The implementation of the nvbctlib API for t124. */ + +/* Definitions that simplify the code which follows. */ +#define CASE_GET_SDRAM_PARAM(x) \ +case token_##x:\ + *value = params->x; \ + break + +#define CASE_SET_SDRAM_PARAM(x) \ +case token_##x:\ + params->x = value; \ + break + +#define CASE_GET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + *value = bct->dev_params[index].dev##_params.x; \ + break + +#define CASE_SET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + bct->dev_params[index].dev##_params.x = value; \ + break + +#define CASE_GET_BL_PARAM(x) \ +case token_bl_##x:\ + *data = bct_ptr->bootloader[set].x; \ + break + +#define CASE_SET_BL_PARAM(x) \ +case token_bl_##x:\ + bct_ptr->bootloader[set].x = *data; \ + break + +#define CASE_GET_NVU32(id) \ +case token_##id:\ + if (bct == NULL) \ + return -ENODATA; \ + *((uint32_t *)data) = bct_ptr->id; \ + break + +#define CASE_GET_CONST(id, val) \ +case token_##id:\ + *((uint32_t *)data) = val; \ + break + +#define CASE_GET_CONST_PREFIX(id, val_prefix) \ +case token_##id:\ + *((uint32_t *)data) = val_prefix##_##id; \ + break + +#define CASE_SET_NVU32(id) \ +case token_##id:\ + bct_ptr->id = *((uint32_t *)data); \ + break + +#define CASE_GET_DATA(id, size) \ +case token_##id:\ + if (*length < size) \ + return -ENODATA;\ + memcpy(data, &(bct_ptr->id), size); \ + *length = size;\ + break + +#define CASE_SET_DATA(id, size) \ +case token_##id:\ + if (length < size) \ + return -ENODATA;\ + memcpy(&(bct_ptr->id), data, size); \ + break + +#define DEFAULT() \ +default : \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +parse_token t124_root_token_list[] = { + token_boot_data_version, + token_block_size, + token_page_size, + token_partition_size, + token_odm_data, + token_bootloader_used, + token_bootloaders_max, + token_bct_size, + token_hash_size, + token_crypto_offset, + token_crypto_length, + token_max_bct_search_blks, + token_unique_chip_id, + token_secure_jtag_control, + token_rsa_key_modulus, + token_rsa_pss_sig_bl, + token_rsa_pss_sig_bct +}; + +int +t124_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1); + + switch (token) { + CASE_SET_DEV_PARAM(sdmmc, clock_divider); + CASE_SET_DEV_PARAM(sdmmc, data_width); + CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_SET_DEV_PARAM(sdmmc, multi_page_support); + + CASE_SET_DEV_PARAM(spiflash, clock_source); + CASE_SET_DEV_PARAM(spiflash, clock_divider); + CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + CASE_SET_DEV_PARAM(spiflash, page_size_2k_or_16k); + + case token_dev_type: + bct->dev_type[index] = value; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t124_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + switch (token) { + CASE_GET_DEV_PARAM(sdmmc, clock_divider); + CASE_GET_DEV_PARAM(sdmmc, data_width); + CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_GET_DEV_PARAM(sdmmc, multi_page_support); + + CASE_GET_DEV_PARAM(spiflash, clock_source); + CASE_GET_DEV_PARAM(spiflash, clock_divider); + CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); + CASE_GET_DEV_PARAM(spiflash, page_size_2k_or_16k); + + case token_dev_type: + *value = bct->dev_type[index]; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t124_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + + switch (token) { + CASE_GET_SDRAM_PARAM(memory_type); + CASE_GET_SDRAM_PARAM(pllm_input_divider); + CASE_GET_SDRAM_PARAM(pllm_feedback_divider); + CASE_GET_SDRAM_PARAM(pllm_stable_time); + CASE_GET_SDRAM_PARAM(pllm_setup_control); + CASE_GET_SDRAM_PARAM(pllm_select_div2); + CASE_GET_SDRAM_PARAM(pllm_pdlshift_ph45); + CASE_GET_SDRAM_PARAM(pllm_pdlshift_ph90); + CASE_GET_SDRAM_PARAM(pllm_pdlshift_ph135); + CASE_GET_SDRAM_PARAM(pllm_kcp); + CASE_GET_SDRAM_PARAM(pllm_kvco); + CASE_GET_SDRAM_PARAM(emc_bct_spare0); + CASE_GET_SDRAM_PARAM(emc_bct_spare1); + CASE_GET_SDRAM_PARAM(emc_bct_spare2); + CASE_GET_SDRAM_PARAM(emc_bct_spare3); + CASE_GET_SDRAM_PARAM(emc_bct_spare4); + CASE_GET_SDRAM_PARAM(emc_bct_spare5); + CASE_GET_SDRAM_PARAM(emc_bct_spare6); + CASE_GET_SDRAM_PARAM(emc_bct_spare7); + CASE_GET_SDRAM_PARAM(emc_bct_spare8); + CASE_GET_SDRAM_PARAM(emc_bct_spare9); + CASE_GET_SDRAM_PARAM(emc_bct_spare10); + CASE_GET_SDRAM_PARAM(emc_bct_spare11); + CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config2); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config3); + CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_GET_SDRAM_PARAM(emc_pin_program_wait); + CASE_GET_SDRAM_PARAM(emc_rc); + CASE_GET_SDRAM_PARAM(emc_rfc); + CASE_GET_SDRAM_PARAM(emc_rfc_slr); + CASE_GET_SDRAM_PARAM(emc_ras); + CASE_GET_SDRAM_PARAM(emc_rp); + CASE_GET_SDRAM_PARAM(emc_r2r); + CASE_GET_SDRAM_PARAM(emc_w2w); + CASE_GET_SDRAM_PARAM(emc_r2w); + CASE_GET_SDRAM_PARAM(emc_w2r); + CASE_GET_SDRAM_PARAM(emc_r2p); + CASE_GET_SDRAM_PARAM(emc_w2p); + CASE_GET_SDRAM_PARAM(emc_rd_rcd); + CASE_GET_SDRAM_PARAM(emc_wr_rcd); + CASE_GET_SDRAM_PARAM(emc_rrd); + CASE_GET_SDRAM_PARAM(emc_rext); + CASE_GET_SDRAM_PARAM(emc_wdv); + CASE_GET_SDRAM_PARAM(emc_wdv_mask); + CASE_GET_SDRAM_PARAM(emc_quse); + CASE_GET_SDRAM_PARAM(emc_quse_width); + CASE_GET_SDRAM_PARAM(emc_ibdly); + CASE_GET_SDRAM_PARAM(emc_einput); + CASE_GET_SDRAM_PARAM(emc_einput_duration); + CASE_GET_SDRAM_PARAM(emc_puterm_extra); + CASE_GET_SDRAM_PARAM(emc_puterm_width); + CASE_GET_SDRAM_PARAM(emc_puterm_adj); + CASE_GET_SDRAM_PARAM(emc_cdb_cntl1); + CASE_GET_SDRAM_PARAM(emc_cdb_cntl2); + CASE_GET_SDRAM_PARAM(emc_cdb_cntl3); + CASE_GET_SDRAM_PARAM(emc_qrst); + CASE_GET_SDRAM_PARAM(emc_qsafe); + CASE_GET_SDRAM_PARAM(emc_rdv); + CASE_GET_SDRAM_PARAM(emc_rdv_mask); + CASE_GET_SDRAM_PARAM(emc_qpop); + CASE_GET_SDRAM_PARAM(emc_refresh); + CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_GET_SDRAM_PARAM(emc_pdex2wr); + CASE_GET_SDRAM_PARAM(emc_pdex2rd); + CASE_GET_SDRAM_PARAM(emc_pchg2pden); + CASE_GET_SDRAM_PARAM(emc_act2pden); + CASE_GET_SDRAM_PARAM(emc_ar2pden); + CASE_GET_SDRAM_PARAM(emc_rw2pden); + CASE_GET_SDRAM_PARAM(emc_txsr); + CASE_GET_SDRAM_PARAM(emc_tcke); + CASE_GET_SDRAM_PARAM(emc_tckesr); + CASE_GET_SDRAM_PARAM(emc_tpd); + CASE_GET_SDRAM_PARAM(emc_tfaw); + CASE_GET_SDRAM_PARAM(emc_trpab); + CASE_GET_SDRAM_PARAM(emc_tclkstable); + CASE_GET_SDRAM_PARAM(emc_tclkstop); + CASE_GET_SDRAM_PARAM(emc_trefbw); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_GET_SDRAM_PARAM(emc_fbio_spare); + CASE_GET_SDRAM_PARAM(emc_mrs); + CASE_GET_SDRAM_PARAM(emc_emrs); + CASE_GET_SDRAM_PARAM(emc_emrs2); + CASE_GET_SDRAM_PARAM(emc_emrs3); + CASE_GET_SDRAM_PARAM(emc_mrw1); + CASE_GET_SDRAM_PARAM(emc_mrw2); + CASE_GET_SDRAM_PARAM(emc_mrw3); + CASE_GET_SDRAM_PARAM(emc_mrw4); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_GET_SDRAM_PARAM(emc_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg2); + CASE_GET_SDRAM_PARAM(emc_cfg_pipe); + CASE_GET_SDRAM_PARAM(emc_dbg); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_GET_SDRAM_PARAM(warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_GET_SDRAM_PARAM(emc_odt_write); + CASE_GET_SDRAM_PARAM(emc_odt_read); + CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_GET_SDRAM_PARAM(emc_ddr2_wait); + CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_GET_SDRAM_PARAM(emc_clock_source); + CASE_GET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_GET_SDRAM_PARAM(emc_timing_control_wait); + CASE_GET_SDRAM_PARAM(emc_wext); + CASE_GET_SDRAM_PARAM(emc_ctt); + CASE_GET_SDRAM_PARAM(emc_ctt_duration); + CASE_GET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_GET_SDRAM_PARAM(emc_txsr_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_rsv); + CASE_GET_SDRAM_PARAM(emc_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt2); + CASE_GET_SDRAM_PARAM(emc_cmd_q); + CASE_GET_SDRAM_PARAM(emc_mc2emc_q); + CASE_GET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_GET_SDRAM_PARAM(emc_dev_select); + CASE_GET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs8); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs9); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs10); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs11); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs12); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs13); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs14); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs15); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse8); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse9); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse10); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse11); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse12); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse13); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse14); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse15); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs8); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs9); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs10); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs11); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs12); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs13); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs14); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs15); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq7); + CASE_GET_SDRAM_PARAM(emc_zcal_interval); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_GET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_cold_boot_enables); + CASE_GET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_clken_override); + CASE_GET_SDRAM_PARAM(mc_dis_extra_snap_levels); + CASE_GET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_GET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_GET_SDRAM_PARAM(pmc_vddp_sel); + CASE_GET_SDRAM_PARAM(pmc_vddp_sel_wait); + CASE_GET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_GET_SDRAM_PARAM(pmc_io_dpd3_req); + CASE_GET_SDRAM_PARAM(pmc_io_dpd3_req_wait); + CASE_GET_SDRAM_PARAM(pmc_reg_short); + CASE_GET_SDRAM_PARAM(pmc_no_io_power); + CASE_GET_SDRAM_PARAM(pmc_por_dpd_ctrl_wait); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl4); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl5); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl4); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl5); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl6); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2clk_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_acpd_control); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte_cfg); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte0); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte1); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte2); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte3); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte_cfg); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte0); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte1); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte2); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte3); + CASE_GET_SDRAM_PARAM(emc_dsr_vttgen_drv); + CASE_GET_SDRAM_PARAM(emc_txdsrvttgen); + CASE_GET_SDRAM_PARAM(emc_bgbias_ctl0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask1); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask2); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_swizzle3); + CASE_GET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_GET_SDRAM_PARAM(mc_emem_arb_override); + CASE_GET_SDRAM_PARAM(mc_emem_arb_override1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_GET_SDRAM_PARAM(mc_clken_override); + CASE_GET_SDRAM_PARAM(mc_stat_control); + CASE_GET_SDRAM_PARAM(mc_display_snap_ring); + CASE_GET_SDRAM_PARAM(mc_video_protect_bom); + CASE_GET_SDRAM_PARAM(mc_video_protect_bom_adr_hi); + CASE_GET_SDRAM_PARAM(mc_video_protect_size_mb); + CASE_GET_SDRAM_PARAM(mc_video_protect_vpr_override); + CASE_GET_SDRAM_PARAM(mc_video_protect_vpr_override1); + CASE_GET_SDRAM_PARAM(mc_video_protect_gpu_override0); + CASE_GET_SDRAM_PARAM(mc_video_protect_gpu_override1); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_bom); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_adr_hi); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_size_mb); + CASE_GET_SDRAM_PARAM(mc_video_protect_write_access); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_protect_write_access); + CASE_GET_SDRAM_PARAM(emc_ca_training_enable); + CASE_GET_SDRAM_PARAM(emc_ca_training_timing_cntl1); + CASE_GET_SDRAM_PARAM(emc_ca_training_timing_cntl2); + CASE_GET_SDRAM_PARAM(swizzle_rank_byte_encode); + CASE_GET_SDRAM_PARAM(boot_rom_patch_control); + CASE_GET_SDRAM_PARAM(boot_rom_patch_data); + CASE_GET_SDRAM_PARAM(mc_mts_carveout_bom); + CASE_GET_SDRAM_PARAM(mc_mts_carveout_adr_hi); + CASE_GET_SDRAM_PARAM(mc_mts_carveout_size_mb); + CASE_GET_SDRAM_PARAM(mc_mts_carveout_reg_ctrl); + + DEFAULT(); + } + return 0; +} + +int +t124_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + /* Update the number of SDRAM parameter sets. */ + bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1); + + switch (token) { + CASE_SET_SDRAM_PARAM(memory_type); + CASE_SET_SDRAM_PARAM(pllm_input_divider); + CASE_SET_SDRAM_PARAM(pllm_feedback_divider); + CASE_SET_SDRAM_PARAM(pllm_stable_time); + CASE_SET_SDRAM_PARAM(pllm_setup_control); + CASE_SET_SDRAM_PARAM(pllm_select_div2); + CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph45); + CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph90); + CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph135); + CASE_SET_SDRAM_PARAM(pllm_kcp); + CASE_SET_SDRAM_PARAM(pllm_kvco); + CASE_SET_SDRAM_PARAM(emc_bct_spare0); + CASE_SET_SDRAM_PARAM(emc_bct_spare1); + CASE_SET_SDRAM_PARAM(emc_bct_spare2); + CASE_SET_SDRAM_PARAM(emc_bct_spare3); + CASE_SET_SDRAM_PARAM(emc_bct_spare4); + CASE_SET_SDRAM_PARAM(emc_bct_spare5); + CASE_SET_SDRAM_PARAM(emc_bct_spare6); + CASE_SET_SDRAM_PARAM(emc_bct_spare7); + CASE_SET_SDRAM_PARAM(emc_bct_spare8); + CASE_SET_SDRAM_PARAM(emc_bct_spare9); + CASE_SET_SDRAM_PARAM(emc_bct_spare10); + CASE_SET_SDRAM_PARAM(emc_bct_spare11); + CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config2); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config3); + CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_SET_SDRAM_PARAM(emc_pin_program_wait); + CASE_SET_SDRAM_PARAM(emc_rc); + CASE_SET_SDRAM_PARAM(emc_rfc); + CASE_SET_SDRAM_PARAM(emc_rfc_slr); + CASE_SET_SDRAM_PARAM(emc_ras); + CASE_SET_SDRAM_PARAM(emc_rp); + CASE_SET_SDRAM_PARAM(emc_r2r); + CASE_SET_SDRAM_PARAM(emc_w2w); + CASE_SET_SDRAM_PARAM(emc_r2w); + CASE_SET_SDRAM_PARAM(emc_w2r); + CASE_SET_SDRAM_PARAM(emc_r2p); + CASE_SET_SDRAM_PARAM(emc_w2p); + CASE_SET_SDRAM_PARAM(emc_rd_rcd); + CASE_SET_SDRAM_PARAM(emc_wr_rcd); + CASE_SET_SDRAM_PARAM(emc_rrd); + CASE_SET_SDRAM_PARAM(emc_rext); + CASE_SET_SDRAM_PARAM(emc_wdv); + CASE_SET_SDRAM_PARAM(emc_wdv_mask); + CASE_SET_SDRAM_PARAM(emc_quse); + CASE_SET_SDRAM_PARAM(emc_quse_width); + CASE_SET_SDRAM_PARAM(emc_ibdly); + CASE_SET_SDRAM_PARAM(emc_einput); + CASE_SET_SDRAM_PARAM(emc_einput_duration); + CASE_SET_SDRAM_PARAM(emc_puterm_extra); + CASE_SET_SDRAM_PARAM(emc_puterm_width); + CASE_SET_SDRAM_PARAM(emc_puterm_adj); + CASE_SET_SDRAM_PARAM(emc_cdb_cntl1); + CASE_SET_SDRAM_PARAM(emc_cdb_cntl2); + CASE_SET_SDRAM_PARAM(emc_cdb_cntl3); + CASE_SET_SDRAM_PARAM(emc_qrst); + CASE_SET_SDRAM_PARAM(emc_qsafe); + CASE_SET_SDRAM_PARAM(emc_rdv); + CASE_SET_SDRAM_PARAM(emc_rdv_mask); + CASE_SET_SDRAM_PARAM(emc_qpop); + CASE_SET_SDRAM_PARAM(emc_refresh); + CASE_SET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_SET_SDRAM_PARAM(emc_pdex2wr); + CASE_SET_SDRAM_PARAM(emc_pdex2rd); + CASE_SET_SDRAM_PARAM(emc_pchg2pden); + CASE_SET_SDRAM_PARAM(emc_act2pden); + CASE_SET_SDRAM_PARAM(emc_ar2pden); + CASE_SET_SDRAM_PARAM(emc_rw2pden); + CASE_SET_SDRAM_PARAM(emc_txsr); + CASE_SET_SDRAM_PARAM(emc_tcke); + CASE_SET_SDRAM_PARAM(emc_tckesr); + CASE_SET_SDRAM_PARAM(emc_tpd); + CASE_SET_SDRAM_PARAM(emc_tfaw); + CASE_SET_SDRAM_PARAM(emc_trpab); + CASE_SET_SDRAM_PARAM(emc_tclkstable); + CASE_SET_SDRAM_PARAM(emc_tclkstop); + CASE_SET_SDRAM_PARAM(emc_trefbw); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_SET_SDRAM_PARAM(emc_fbio_spare); + CASE_SET_SDRAM_PARAM(emc_mrs); + CASE_SET_SDRAM_PARAM(emc_emrs); + CASE_SET_SDRAM_PARAM(emc_emrs2); + CASE_SET_SDRAM_PARAM(emc_emrs3); + CASE_SET_SDRAM_PARAM(emc_mrw1); + CASE_SET_SDRAM_PARAM(emc_mrw2); + CASE_SET_SDRAM_PARAM(emc_mrw3); + CASE_SET_SDRAM_PARAM(emc_mrw4); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_SET_SDRAM_PARAM(emc_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg2); + CASE_SET_SDRAM_PARAM(emc_cfg_pipe); + CASE_SET_SDRAM_PARAM(emc_dbg); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_SET_SDRAM_PARAM(warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_SET_SDRAM_PARAM(emc_odt_write); + CASE_SET_SDRAM_PARAM(emc_odt_read); + CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_SET_SDRAM_PARAM(emc_ddr2_wait); + CASE_SET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_SET_SDRAM_PARAM(emc_clock_source); + CASE_SET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_SET_SDRAM_PARAM(emc_timing_control_wait); + CASE_SET_SDRAM_PARAM(emc_wext); + CASE_SET_SDRAM_PARAM(emc_ctt); + CASE_SET_SDRAM_PARAM(emc_ctt_duration); + CASE_SET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_SET_SDRAM_PARAM(emc_txsr_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_rsv); + CASE_SET_SDRAM_PARAM(emc_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt2); + CASE_SET_SDRAM_PARAM(emc_cmd_q); + CASE_SET_SDRAM_PARAM(emc_mc2emc_q); + CASE_SET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_SET_SDRAM_PARAM(emc_dev_select); + CASE_SET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs8); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs9); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs10); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs11); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs12); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs13); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs14); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs15); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse8); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse9); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse10); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse11); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse12); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse13); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse14); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse15); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs8); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs9); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs10); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs11); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs12); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs13); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs14); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs15); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq7); + CASE_SET_SDRAM_PARAM(emc_zcal_interval); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_SET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_cold_boot_enables); + CASE_SET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_clken_override); + CASE_SET_SDRAM_PARAM(mc_dis_extra_snap_levels); + CASE_SET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_SET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_SET_SDRAM_PARAM(pmc_vddp_sel); + CASE_SET_SDRAM_PARAM(pmc_vddp_sel_wait); + CASE_SET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_SET_SDRAM_PARAM(pmc_io_dpd3_req); + CASE_SET_SDRAM_PARAM(pmc_io_dpd3_req_wait); + CASE_SET_SDRAM_PARAM(pmc_reg_short); + CASE_SET_SDRAM_PARAM(pmc_no_io_power); + CASE_SET_SDRAM_PARAM(pmc_por_dpd_ctrl_wait); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl4); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl5); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl4); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl5); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl6); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_acpd_control); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte_cfg); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte0); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte1); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte2); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte3); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte_cfg); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte0); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte1); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte2); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte3); + CASE_SET_SDRAM_PARAM(emc_dsr_vttgen_drv); + CASE_SET_SDRAM_PARAM(emc_txdsrvttgen); + CASE_SET_SDRAM_PARAM(emc_bgbias_ctl0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask1); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask2); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_swizzle3); + CASE_SET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_SET_SDRAM_PARAM(mc_emem_arb_override); + CASE_SET_SDRAM_PARAM(mc_emem_arb_override1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_SET_SDRAM_PARAM(mc_clken_override); + CASE_SET_SDRAM_PARAM(mc_stat_control); + CASE_SET_SDRAM_PARAM(mc_display_snap_ring); + CASE_SET_SDRAM_PARAM(mc_video_protect_bom); + CASE_SET_SDRAM_PARAM(mc_video_protect_bom_adr_hi); + CASE_SET_SDRAM_PARAM(mc_video_protect_size_mb); + CASE_SET_SDRAM_PARAM(mc_video_protect_vpr_override); + CASE_SET_SDRAM_PARAM(mc_video_protect_vpr_override1); + CASE_SET_SDRAM_PARAM(mc_video_protect_gpu_override0); + CASE_SET_SDRAM_PARAM(mc_video_protect_gpu_override1); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_bom); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_adr_hi); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_size_mb); + CASE_SET_SDRAM_PARAM(mc_video_protect_write_access); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_protect_write_access); + CASE_SET_SDRAM_PARAM(emc_ca_training_enable); + CASE_SET_SDRAM_PARAM(emc_ca_training_timing_cntl1); + CASE_SET_SDRAM_PARAM(emc_ca_training_timing_cntl2); + CASE_SET_SDRAM_PARAM(swizzle_rank_byte_encode); + CASE_SET_SDRAM_PARAM(boot_rom_patch_control); + CASE_SET_SDRAM_PARAM(boot_rom_patch_data); + CASE_SET_SDRAM_PARAM(mc_mts_carveout_bom); + CASE_SET_SDRAM_PARAM(mc_mts_carveout_adr_hi); + CASE_SET_SDRAM_PARAM(mc_mts_carveout_size_mb); + CASE_SET_SDRAM_PARAM(mc_mts_carveout_reg_ctrl); + + DEFAULT(); + } + return 0; +} + +int +t124_getbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_GET_BL_PARAM(version); + CASE_GET_BL_PARAM(start_blk); + CASE_GET_BL_PARAM(start_page); + CASE_GET_BL_PARAM(length); + CASE_GET_BL_PARAM(load_addr); + CASE_GET_BL_PARAM(entry_point); + CASE_GET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(data, + &(bct_ptr->bootloader[set].signature.crypto_hash), + sizeof(nvboot_hash)); + break; + + case token_rsa_pss_sig_bl: + reverse_byte_order((uint8_t *)data, + (const uint8_t *)&bct_ptr->bootloader[set].signature.rsa_pss_sig, + sizeof(nvboot_rsa_pss_sig)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t124_setbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_SET_BL_PARAM(version); + CASE_SET_BL_PARAM(start_blk); + CASE_SET_BL_PARAM(start_page); + CASE_SET_BL_PARAM(length); + CASE_SET_BL_PARAM(load_addr); + CASE_SET_BL_PARAM(entry_point); + CASE_SET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(&(bct_ptr->bootloader[set].signature.crypto_hash), + data, + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t124_bct_get_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + nvboot_config_table samplebct; /* Used for computing offsets. */ + + /* + * Note: Not all queries require use of the BCT, so testing for a + * valid BCT is distributed within the code. + */ + if (data == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_GET_NVU32(boot_data_version); + CASE_GET_NVU32(block_size_log2); + CASE_GET_NVU32(page_size_log2); + CASE_GET_NVU32(partition_size); + CASE_GET_NVU32(num_param_sets); + CASE_GET_NVU32(num_sdram_sets); + CASE_GET_NVU32(bootloader_used); + CASE_GET_NVU32(odm_data); + CASE_GET_NVU32(secure_jtag_control); + + case token_block_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->block_size_log2; + break; + + case token_page_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->page_size_log2; + break; + + /* + * Constants. + */ + + CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); + CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); + + case token_crypto_hash: + memcpy(data, + &(bct_ptr->signature.crypto_hash), + sizeof(nvboot_hash)); + break; + + case token_unique_chip_id: + memcpy(data, &(bct_ptr->unique_chip_id), sizeof(nvboot_ecid)); + break; + + case token_rsa_key_modulus: + reverse_byte_order(data, (const uint8_t *)&bct_ptr->key, + sizeof(nvboot_rsa_key_modulus)); + break; + + case token_rsa_pss_sig_bct: + reverse_byte_order(data, + (const uint8_t *)&bct_ptr->signature.rsa_pss_sig, + sizeof(nvboot_rsa_pss_sig)); + break; + + case token_reserved_offset: + *((uint32_t *)data) = (uint8_t *)&(samplebct.reserved) + - (uint8_t *)&samplebct; + break; + + case token_bct_size: + *((uint32_t *)data) = sizeof(nvboot_config_table); + break; + + CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); + + case token_crypto_offset: + /* Offset to region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)&(samplebct.random_aes_blk) + - (uint8_t *)&samplebct; + break; + + case token_crypto_length: + /* size of region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)bct_ptr + sizeof(nvboot_config_table) + - (uint8_t *)&(bct_ptr->random_aes_blk); + break; + + CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); + + CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); + CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); + + CASE_GET_CONST_PREFIX(memory_type_none, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr3, nvboot); + + default: + return -ENODATA; + } + return 0; +} + +int +t124_bct_get_value_size(parse_token id) +{ + switch (id) { + case token_rsa_key_modulus: + return sizeof(nvboot_rsa_key_modulus); + + case token_rsa_pss_sig_bl: + return sizeof(nvboot_rsa_pss_sig); + + case token_rsa_pss_sig_bct: + return sizeof(nvboot_rsa_pss_sig); + + /* + * Other bct fields can be added in when needed + */ + default: + return -ENODATA; + } + return 0; +} + +int +t124_bct_set_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_SET_NVU32(boot_data_version); + CASE_SET_NVU32(block_size_log2); + CASE_SET_NVU32(page_size_log2); + CASE_SET_NVU32(partition_size); + CASE_SET_NVU32(num_param_sets); + CASE_SET_NVU32(num_sdram_sets); + CASE_SET_NVU32(bootloader_used); + CASE_SET_NVU32(odm_data); + CASE_SET_NVU32(secure_jtag_control); + case token_unique_chip_id: + memcpy(&bct_ptr->unique_chip_id, data, sizeof(nvboot_ecid)); + break; + + case token_rsa_key_modulus: + reverse_byte_order((uint8_t *)&bct_ptr->key, data, + sizeof(nvboot_rsa_key_modulus)); + break; + + case token_rsa_pss_sig_bl: + /* + * Update bootloader 0 since there is only one copy + * of bootloader being built in. + */ + reverse_byte_order( + (uint8_t *)&bct_ptr->bootloader[0].signature.rsa_pss_sig, + data, sizeof(nvboot_rsa_pss_sig)); + break; + + case token_rsa_pss_sig_bct: + reverse_byte_order((uint8_t *)&bct_ptr->signature.rsa_pss_sig, + data, sizeof(nvboot_rsa_pss_sig)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t124_bct_set_data(parse_token id, + uint8_t *data, + uint32_t length, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + + case token_crypto_hash: + if (length < sizeof(nvboot_hash)) + return -ENODATA; + memcpy(&bct_ptr->signature.crypto_hash, data, sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int t124_get_bct_size() +{ + return sizeof(nvboot_config_table); +} + +int t124_bct_token_supported(parse_token token) +{ + int index; + + for (index = 0; index < ARRAY_SIZE(t124_root_token_list); index++) + if (t124_root_token_list[index] == token) + return 1; + + return 0; +} + +void t124_init_bad_block_table(build_image_context *context) +{ + uint32_t bytes_per_entry; + nvboot_badblock_table *table; + nvboot_config_table *bct; + + bct = (nvboot_config_table *)(context->bct); + + assert(context != NULL); + assert(bct != NULL); + + table = &bct->badblock_table; + + bytes_per_entry = ICEIL(context->partition_size, + NVBOOT_BAD_BLOCK_TABLE_SIZE); + table->block_size_log2 = context->block_size_log2; + table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), + table->block_size_log2); + table->entries_used = iceil_log2(context->partition_size, + table->virtual_blk_size_log2); +} + +cbootimage_soc_config tegra124_config = { + .init_bad_block_table = t124_init_bad_block_table, + .set_dev_param = t124_set_dev_param, + .get_dev_param = t124_get_dev_param, + .set_sdram_param = t124_set_sdram_param, + .get_sdram_param = t124_get_sdram_param, + .setbl_param = t124_setbl_param, + .getbl_param = t124_getbl_param, + .set_value = t124_bct_set_value, + .get_value = t124_bct_get_value, + .get_value_size = t124_bct_get_value_size, + .set_data = t124_bct_set_data, + .get_bct_size = t124_get_bct_size, + .token_supported = t124_bct_token_supported, + + .devtype_table = s_devtype_table_t124, + .sdmmc_data_width_table = s_sdmmc_data_width_table_t124, + .spi_clock_source_table = s_spi_clock_source_table_t124, + .nvboot_memory_type_table = s_nvboot_memory_type_table_t124, + .sdram_field_table = s_sdram_field_table_t124, + .nand_table = 0, + .sdmmc_table = s_sdmmc_table_t124, + .spiflash_table = s_spiflash_table_t124, + .device_type_table = s_device_type_table_t124, +}; + +void t124_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + context->boot_data_version = BOOTDATA_VERSION_T124; + *soc_config = &tegra124_config; +} + +int if_bct_is_t124_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + nvboot_config_table *bct = (nvboot_config_table *) context->bct; + + if (bct->boot_data_version == BOOTDATA_VERSION_T124) { + t124_get_soc_config(context, soc_config); + return 1; + } + return 0; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t124/nvboot_bct_t124.h b/firmware/coreboot/util/nvidia/cbootimage/src/t124/nvboot_bct_t124.h new file mode 100644 index 0000000000..ca46b54f14 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t124/nvboot_bct_t124.h @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#ifndef INCLUDED_NVBOOT_BCT_T124_H +#define INCLUDED_NVBOOT_BCT_T124_H + +#include +#include "nvboot_sdram_param_t124.h" + +/** + * Defines the number of 32-bit words in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_WORDS 162 + +/** + * Defines the number of bytes in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_SIZE \ + (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) + +/** + * Defines the number of bytes in the reserved area of the BCT. + */ +#define NVBOOT_BCT_RESERVED_SIZE 2 + +/** + * Defines the maximum number of bootloader descriptions in the BCT. + */ +#define NVBOOT_MAX_BOOTLOADERS 4 + +/** + * Defines the maximum number of device parameter sets in the BCT. + * The value must be equal to (1 << # of device straps) + */ +#define NVBOOT_BCT_MAX_PARAM_SETS 4 + +/** + * Defines the maximum number of SDRAM parameter sets in the BCT. + * The value must be equal to (1 << # of SDRAM straps) + */ +#define NVBOOT_BCT_MAX_SDRAM_SETS 4 + +/** + * Defines the number of entries (bits) in the bad block table. + * The consequences of changing its value are as follows. Using P as the + * # of physical blocks in the boot loader and B as the value of this + * constant: + * B > P: There will be unused storage in the bad block table. + * B < P: The virtual block size will be greater than the physical block + * size, so the granularity of the bad block table will be less than + * one bit per physical block. + * + * 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one + * bit per block (1 virtual block = 1 physical block). This occupies 512 bytes + * of storage. + */ +#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096 + +/** + * Defines the amount of padding needed to pad the bad block table to a + * multiple of AES block size. + */ +#define NVBOOT_BAD_BLOCK_TABLE_PADDING 10 + +/** + * Defines the maximum number of blocks to search for BCTs. + * + * This value covers the initial block and a set of journal blocks. + * + * Ideally, this number will span several erase units for reliable updates + * and tolerance for blocks to become bad with use. Safe updates require + * a minimum of 2 erase units in which BCTs can appear. + * + * To ensure that the BCT search spans a sufficient range of configurations, + * the search block count has been set to 64. This allows for redundancy with + * a wide range of parts and provides room for greater problems in this + * region of the device. + */ +#define NVBOOT_MAX_BCT_SEARCH_BLOCKS 64 + +#define ARSE_RSA_MAX_MODULUS_SIZE 2048 + +/** + * Defines the RSA modulus length in bits and bytes used for PKC secure boot. + */ +enum {NVBOOT_SE_RSA_MODULUS_LENGTH_BITS = ARSE_RSA_MAX_MODULUS_SIZE}; + +/* + * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) + */ +enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; + +/** + * Defines the storage for a hash value (128 bits). + */ +typedef struct nvboot_hash_rec { + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; +} nvboot_hash; + +/* + * Defines the storage for the RSA public key's modulus + * in the BCT + */ +typedef struct nvboot_rsa_key_modulus_rec { + /* The modulus size is 2048-bits. */ + uint32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; +} nvboot_rsa_key_modulus; + +typedef struct nvboot_rsa_pss_sig_rec { + /* + * The RSA-PSS signature length is equal to the + * length in octets of the RSA modulus. + * In our case, it's 2048-bits. + */ + uint32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; +} nvboot_rsa_pss_sig; + +typedef struct nvboot_object_signature_rec { + /* + * Specifies the AES-CMAC signature for the rest of the BCT structure if symmetric key + * encryption secure boot scheme is used. + */ + nvboot_hash crypto_hash; + + /* + * Specifies the RSASSA-PSS signature for the rest of the BCT structure if public + * key cryptography secure boot scheme is used. + */ + nvboot_rsa_pss_sig rsa_pss_sig; +} nvboot_object_signature; + +typedef struct nvboot_ecid_rec { + uint32_t ecid_0; + uint32_t ecid_1; + uint32_t ecid_2; + uint32_t ecid_3; +} nvboot_ecid; + +/* Defines various data widths supported. */ +typedef enum { + /** + * Specifies a 1 bit interface to eMMC. + * Note that 1-bit data width is only for the driver's internal use. + * Fuses doesn't provide option to select 1-bit data width. + * The driver selects 1-bit internally based on need. + * It is used for reading Extended CSD and when the power class + * requirements of a card for 4-bit or 8-bit transfers are not + * supported by the target board. + */ + nvboot_sdmmc_data_width_1bit = 0, + + /* Specifies a 4 bit interface to eMMC. */ + nvboot_sdmmc_data_width_4bit = 1, + + /* Specifies a 8 bit interface to eMMC. */ + nvboot_sdmmc_data_width_8bit = 2, + /* Specifies a 4 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_4bit = 5, + /* Specifies a 8 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_8bit = 6, + + nvboot_sdmmc_data_width_num, + nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF +} nvboot_sdmmc_data_width; + +/* Defines the parameters that can be changed after BCT is read. */ +typedef struct nvboot_sdmmc_params_rec { + /** + * Specifies the clock divider for the SDMMC controller's clock source, + * which is PLLP running at 216MHz. If it is set to 9, then the SDMMC + * controller runs at 216/9 = 24MHz. + */ + uint8_t clock_divider; + + /* Specifies the data bus width. Supported data widths are 4/8 bits. */ + nvboot_sdmmc_data_width data_width; + + /** + * Max Power class supported by the target board. + * The driver determines the best data width and clock frequency + * supported within the power class range (0 to Max) if the selected + * data width cannot be used at the chosen clock frequency. + */ + uint8_t max_power_class_supported; + + /* Specifies the max page size supported by driver */ + uint8_t multi_page_support; +} nvboot_sdmmc_params; + +typedef enum { + /* Specifies SPI clock source to be PLLP. */ + nvboot_spi_clock_source_pllp_out0 = 0, + + /* Specifies SPI clock source to be ClockM. */ + nvboot_spi_clock_source_clockm = 6, + + nvboot_spi_clock_source_num, + nvboot_spi_clock_source_force32 = 0x7FFFFFF +} nvboot_spi_clock_source; + +/** + * Defines the parameters SPI FLASH devices. + */ +typedef struct nvboot_spiflash_params_rec { + /** + * Specifies the clock source to use. + */ + uint32_t clock_source; + + /** + * Specifes the clock divider to use. + * The value is a 7-bit value based on an input clock of 432Mhz. + * Divider = (432+ DesiredFrequency-1)/DesiredFrequency; + * Typical values: + * NORMAL_READ at 20MHz: 22 + * FAST_READ at 33MHz: 14 + * FAST_READ at 40MHz: 11 + * FAST_READ at 50MHz: 9 + */ + uint8_t clock_divider; + + /** + * Specifies the type of command for read operations. + * NV_FALSE specifies a NORMAL_READ Command + * NV_TRUE specifies a FAST_READ Command + */ + uint8_t read_command_type_fast; + + /* 0 = 2k page size, 1 = 16K page size */ + uint8_t page_size_2k_or_16k; +} nvboot_spiflash_params; + +/** +* Defines the union of the parameters required by each device. +*/ +typedef union { + uint8_t size[64]; + /* Specifies optimized parameters for eMMC and eSD */ + nvboot_sdmmc_params sdmmc_params; + /* Specifies optimized parameters for SPI NOR */ + nvboot_spiflash_params spiflash_params; +} nvboot_dev_params; + +/** + * Identifies the types of devices from which the system booted. + * Used to identify primary and secondary boot devices. + * @note These no longer match the fuse API device values (for + * backward compatibility with AP15). + */ +typedef enum { + /* Specifies a default (unset) value. */ + nvboot_dev_type_none = 0, + + /* Specifies SPI NOR. */ + nvboot_dev_type_spi = 3, + + /* Specifies SDMMC (either eMMC or eSD). */ + nvboot_dev_type_sdmmc = 4, + + nvboot_dev_type_max, + + /* Ignore -- Forces compilers to make 32-bit enums. */ + nvboot_dev_type_force32 = 0x7FFFFFFF +} nvboot_dev_type; + +/** + * Stores information needed to locate and verify a boot loader. + * + * There is one \c nv_bootloader_info structure for each copy of a BL stored on + * the device. + */ +typedef struct nv_bootloader_info_rec { + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; + + /* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */ + nvboot_object_signature signature; +} nv_bootloader_info; + +/** + * Defines the bad block table structure stored in the BCT. + */ +typedef struct nvboot_badblock_table_rec { + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; + /* + * Add a reserved field as padding to make the bad block table structure + * a multiple of 16 bytes (AES block size). + */ + uint8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; +} nvboot_badblock_table; + +/** + * Contains the information needed to load BLs from the secondary boot device. + * + * - Supplying NumParamSets = 0 indicates not to load any of them. + * - Supplying NumDramSets = 0 indicates not to load any of them. + * - The \c random_aes_blk member exists to increase the difficulty of + * key attacks based on knowledge of this structure. + */ +typedef struct nvboot_config_table_rec { + nvboot_badblock_table badblock_table; + nvboot_rsa_key_modulus key; + nvboot_object_signature signature; + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + uint32_t odm_data; + uint32_t reserved1; + + /* START OF SIGNED SECTION OF THE BCT */ + nvboot_hash random_aes_blk; + nvboot_ecid unique_chip_id; + uint32_t boot_data_version; + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; + nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; + nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; + uint32_t num_sdram_sets; + nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; + + uint32_t bootloader_used; + nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; + + uint8_t enable_fail_back; + + /* + * Specify whether or not to enable JTAG access when the JTAG disable fuse + * has not been burned. + * SecureJtagControl = NV_FALSE (0) = Disable JTAG access. + * SecureJtagControl = NV_TRUE (1) = Enable JTAG access. + */ + uint8_t secure_jtag_control; + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; +} nvboot_config_table; +#endif /* #ifndef INCLUDED_NVBOOT_BCT_T124_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t124/nvboot_sdram_param_t124.h b/firmware/coreboot/util/nvidia/cbootimage/src/t124/nvboot_sdram_param_t124.h new file mode 100644 index 0000000000..feb09f8187 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t124/nvboot_sdram_param_t124.h @@ -0,0 +1,803 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T124_H +#define INCLUDED_NVBOOT_SDRAM_PARAM_T124_H + +#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 + +typedef enum { + /* Specifies the memory type to be undefined */ + nvboot_memory_type_none = 0, + + /* Specifies the memory type to be DDR SDRAM */ + nvboot_memory_type_ddr = 0, + + /* Specifies the memory type to be LPDDR SDRAM */ + nvboot_memory_type_lpddr = 0, + + /* Specifies the memory type to be DDR2 SDRAM */ + nvboot_memory_type_ddr2 = 0, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + nvboot_memory_type_lpddr2, + + /* Specifies the memory type to be DDR3 SDRAM */ + nvboot_memory_type_ddr3, + + nvboot_memory_type_num, + nvboot_memory_type_force32 = 0x7FFFFFF +} nvboot_memory_type; + +/** + * Defines the SDRAM parameter structure + */ +typedef struct nvboot_sdram_params_rec { + /* sdram data structure generated by tool warmboot_code_gen */ + + /* Specifies the type of memory device */ + nvboot_memory_type memory_type; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t pllm_input_divider; + /* Specifies the N value for PllM */ + uint32_t pllm_feedback_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t pllm_stable_time; + /* Specifies misc. control bits */ + uint32_t pllm_setup_control; + /* Enables the Div by 2 */ + uint32_t pllm_select_div2; + /* Powers down VCO output Level shifter */ + uint32_t pllm_pdlshift_ph45; + /* Powers down VCO output Level shifter */ + uint32_t pllm_pdlshift_ph90; + /* Powers down VCO output Level shifter */ + uint32_t pllm_pdlshift_ph135; + /* Specifies value for Charge Pump Gain Control */ + uint32_t pllm_kcp; + /* Specifies VCO gain */ + uint32_t pllm_kvco; + /* Spare BCT param */ + uint32_t emc_bct_spare0; + /* Spare BCT param */ + uint32_t emc_bct_spare1; + /* Spare BCT param */ + uint32_t emc_bct_spare2; + /* Spare BCT param */ + uint32_t emc_bct_spare3; + /* Spare BCT param */ + uint32_t emc_bct_spare4; + /* Spare BCT param */ + uint32_t emc_bct_spare5; + /* Spare BCT param */ + uint32_t emc_bct_spare6; + /* Spare BCT param */ + uint32_t emc_bct_spare7; + /* Spare BCT param */ + uint32_t emc_bct_spare8; + /* Spare BCT param */ + uint32_t emc_bct_spare9; + /* Spare BCT param */ + uint32_t emc_bct_spare10; + /* Spare BCT param */ + uint32_t emc_bct_spare11; + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t emc_clock_source; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t emc_auto_cal_interval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t emc_auto_cal_config; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t emc_auto_cal_config2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t emc_auto_cal_config3; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t emc_auto_cal_wait; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t emc_adr_cfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t emc_pin_program_wait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t emc_pin_extra_wait; + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t emc_timing_control_wait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t emc_rc; + /* Specifies the value for EMC_RFC */ + uint32_t emc_rfc; + /* Specifies the value for EMC_RFC_SLR */ + uint32_t emc_rfc_slr; + /* Specifies the value for EMC_RAS */ + uint32_t emc_ras; + /* Specifies the value for EMC_RP */ + uint32_t emc_rp; + /* Specifies the value for EMC_R2R */ + uint32_t emc_r2r; + /* Specifies the value for EMC_W2W */ + uint32_t emc_w2w; + /* Specifies the value for EMC_R2W */ + uint32_t emc_r2w; + /* Specifies the value for EMC_W2R */ + uint32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + uint32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + uint32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + uint32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + uint32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + uint32_t emc_rext; + /* Specifies the value for EMC_WEXT */ + uint32_t emc_wext; + /* Specifies the value for EMC_WDV */ + uint32_t emc_wdv; + /* Specifies the value for EMC_WDV_MASK */ + uint32_t emc_wdv_mask; + /* Specifies the value for EMC_QUSE */ + uint32_t emc_quse; + /* Specifies the value for EMC_QUSE_WIDTH */ + uint32_t emc_quse_width; + /* Specifies the value for EMC_IBDLY */ + uint32_t emc_ibdly; + /* Specifies the value for EMC_EINPUT */ + uint32_t emc_einput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t emc_einput_duration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t emc_puterm_extra; + /* Specifies the value for EMC_PUTERM_WIDTH */ + uint32_t emc_puterm_width; + /* Specifies the value for EMC_PUTERM_ADJ */ + uint32_t emc_puterm_adj; + /* Specifies the value for EMC_CDB_CNTL_1 */ + uint32_t emc_cdb_cntl1; + /* Specifies the value for EMC_CDB_CNTL_2 */ + uint32_t emc_cdb_cntl2; + /* Specifies the value for EMC_CDB_CNTL_3 */ + uint32_t emc_cdb_cntl3; + /* Specifies the value for EMC_QRST */ + uint32_t emc_qrst; + /* Specifies the value for EMC_QSAFE */ + uint32_t emc_qsafe; + /* Specifies the value for EMC_RDV */ + uint32_t emc_rdv; + /* Specifies the value for EMC_RDV_MASK */ + uint32_t emc_rdv_mask; + /* Specifies the value for EMC_QPOP */ + uint32_t emc_qpop; + /* Specifies the value for EMC_CTT */ + uint32_t emc_ctt; + /* Specifies the value for EMC_CTT_DURATION */ + uint32_t emc_ctt_duration; + /* Specifies the value for EMC_REFRESH */ + uint32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t emc_prerefresh_req_cnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t emc_rw2pden; + /* Specifies the value for EMC_TXSR */ + uint32_t emc_txsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t emc_txsr_dll; + /* Specifies the value for EMC_TCKE */ + uint32_t emc_tcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t emc_tckesr; + /* Specifies the value for EMC_TPD */ + uint32_t emc_tpd; + /* Specifies the value for EMC_TFAW */ + uint32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + uint32_t emc_trefbw; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + uint32_t emc_fbio_cfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t emc_fbio_spare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t emc_cfg_rsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t emc_mrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t emc_emrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t emc_emrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t emc_emrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t emc_mrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t emc_mrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t emc_mrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t emc_mrw4; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t emc_mrw_extra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t emc_warm_boot_mrw_extra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t emc_warm_boot_extramode_reg_write_enable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t emc_extramode_reg_write_enable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t emc_mrw_reset_ninit_wait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t emc_mrs_wait_cnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t emc_mrs_wait_cnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t emc_cfg2; + /* Specifies the pipe bypass controls */ + uint32_t emc_cfg_pipe; + /* Specifies the value for EMC_DBG */ + uint32_t emc_dbg; + /* Specifies the value for EMC_CMDQ */ + uint32_t emc_cmd_q; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t emc_mc2emc_q; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t emc_dyn_self_ref_control; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t ahb_arbitration_xbar_ctrl_meminit_done; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t emc_cfg_dig_dll; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t emc_cfg_dig_dll_period; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t emc_dev_select; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t emc_sel_dpd_ctrl; + + /* Pads trimmer delays */ + + /* Specifies the value for EMC_DLL_XFORM_DQS0 */ + uint32_t emc_dll_xform_dqs0; + /* Specifies the value for EMC_DLL_XFORM_DQS1 */ + uint32_t emc_dll_xform_dqs1; + /* Specifies the value for EMC_DLL_XFORM_DQS2 */ + uint32_t emc_dll_xform_dqs2; + /* Specifies the value for EMC_DLL_XFORM_DQS3 */ + uint32_t emc_dll_xform_dqs3; + /* Specifies the value for EMC_DLL_XFORM_DQS4 */ + uint32_t emc_dll_xform_dqs4; + /* Specifies the value for EMC_DLL_XFORM_DQS5 */ + uint32_t emc_dll_xform_dqs5; + /* Specifies the value for EMC_DLL_XFORM_DQS6 */ + uint32_t emc_dll_xform_dqs6; + /* Specifies the value for EMC_DLL_XFORM_DQS7 */ + uint32_t emc_dll_xform_dqs7; + /* Specifies the value for EMC_DLL_XFORM_DQS8 */ + uint32_t emc_dll_xform_dqs8; + /* Specifies the value for EMC_DLL_XFORM_DQS9 */ + uint32_t emc_dll_xform_dqs9; + /* Specifies the value for EMC_DLL_XFORM_DQS10 */ + uint32_t emc_dll_xform_dqs10; + /* Specifies the value for EMC_DLL_XFORM_DQS11 */ + uint32_t emc_dll_xform_dqs11; + /* Specifies the value for EMC_DLL_XFORM_DQS12 */ + uint32_t emc_dll_xform_dqs12; + /* Specifies the value for EMC_DLL_XFORM_DQS13 */ + uint32_t emc_dll_xform_dqs13; + /* Specifies the value for EMC_DLL_XFORM_DQS14 */ + uint32_t emc_dll_xform_dqs14; + /* Specifies the value for EMC_DLL_XFORM_DQS15 */ + uint32_t emc_dll_xform_dqs15; + /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ + uint32_t emc_dll_xform_quse0; + /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ + uint32_t emc_dll_xform_quse1; + /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ + uint32_t emc_dll_xform_quse2; + /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ + uint32_t emc_dll_xform_quse3; + /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ + uint32_t emc_dll_xform_quse4; + /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ + uint32_t emc_dll_xform_quse5; + /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ + uint32_t emc_dll_xform_quse6; + /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ + uint32_t emc_dll_xform_quse7; + /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ + uint32_t emc_dll_xform_addr0; + /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ + uint32_t emc_dll_xform_addr1; + /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ + uint32_t emc_dll_xform_addr2; + /* Specifies the value for EMC_DLL_XFORM_ADDR3 */ + uint32_t emc_dll_xform_addr3; + /* Specifies the value for EMC_DLL_XFORM_ADDR4 */ + uint32_t emc_dll_xform_addr4; + /* Specifies the value for EMC_DLL_XFORM_ADDR5 */ + uint32_t emc_dll_xform_addr5; + /* Specifies the value for EMC_DLL_XFORM_QUSE8 */ + uint32_t emc_dll_xform_quse8; + /* Specifies the value for EMC_DLL_XFORM_QUSE9 */ + uint32_t emc_dll_xform_quse9; + /* Specifies the value for EMC_DLL_XFORM_QUSE10 */ + uint32_t emc_dll_xform_quse10; + /* Specifies the value for EMC_DLL_XFORM_QUSE11 */ + uint32_t emc_dll_xform_quse11; + /* Specifies the value for EMC_DLL_XFORM_QUSE12 */ + uint32_t emc_dll_xform_quse12; + /* Specifies the value for EMC_DLL_XFORM_QUSE13 */ + uint32_t emc_dll_xform_quse13; + /* Specifies the value for EMC_DLL_XFORM_QUSE14 */ + uint32_t emc_dll_xform_quse14; + /* Specifies the value for EMC_DLL_XFORM_QUSE15 */ + uint32_t emc_dll_xform_quse15; + /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ + uint32_t emc_dli_trim_tx_dqs0; + /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ + uint32_t emc_dli_trim_tx_dqs1; + /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ + uint32_t emc_dli_trim_tx_dqs2; + /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ + uint32_t emc_dli_trim_tx_dqs3; + /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ + uint32_t emc_dli_trim_tx_dqs4; + /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ + uint32_t emc_dli_trim_tx_dqs5; + /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ + uint32_t emc_dli_trim_tx_dqs6; + /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ + uint32_t emc_dli_trim_tx_dqs7; + /* Specifies the value for EMC_DLI_TRIM_TXDQS8 */ + uint32_t emc_dli_trim_tx_dqs8; + /* Specifies the value for EMC_DLI_TRIM_TXDQS9 */ + uint32_t emc_dli_trim_tx_dqs9; + /* Specifies the value for EMC_DLI_TRIM_TXDQS10 */ + uint32_t emc_dli_trim_tx_dqs10; + /* Specifies the value for EMC_DLI_TRIM_TXDQS11 */ + uint32_t emc_dli_trim_tx_dqs11; + /* Specifies the value for EMC_DLI_TRIM_TXDQS12 */ + uint32_t emc_dli_trim_tx_dqs12; + /* Specifies the value for EMC_DLI_TRIM_TXDQS13 */ + uint32_t emc_dli_trim_tx_dqs13; + /* Specifies the value for EMC_DLI_TRIM_TXDQS14 */ + uint32_t emc_dli_trim_tx_dqs14; + /* Specifies the value for EMC_DLI_TRIM_TXDQS15 */ + uint32_t emc_dli_trim_tx_dqs15; + /* Specifies the value for EMC_DLL_XFORM_DQ0 */ + uint32_t emc_dll_xform_dq0; + /* Specifies the value for EMC_DLL_XFORM_DQ1 */ + uint32_t emc_dll_xform_dq1; + /* Specifies the value for EMC_DLL_XFORM_DQ2 */ + uint32_t emc_dll_xform_dq2; + /* Specifies the value for EMC_DLL_XFORM_DQ3 */ + uint32_t emc_dll_xform_dq3; + /* Specifies the value for EMC_DLL_XFORM_DQ4 */ + uint32_t emc_dll_xform_dq4; + /* Specifies the value for EMC_DLL_XFORM_DQ5 */ + uint32_t emc_dll_xform_dq5; + /* Specifies the value for EMC_DLL_XFORM_DQ6 */ + uint32_t emc_dll_xform_dq6; + /* Specifies the value for EMC_DLL_XFORM_DQ7 */ + uint32_t emc_dll_xform_dq7; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t warm_boot_wait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + uint32_t emc_ctt_term_ctrl; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_write; + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_read; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t emc_zcal_interval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t emc_zcal_wait_cnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t emc_zcal_mrw_cmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t emc_mrs_reset_dll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t emc_zcal_init_dev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t emc_zcal_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t emc_zcal_init_wait; + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + uint32_t emc_zcal_warm_cold_boot_enables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t emc_mrw_lpddr2zcal_warm_boot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t emc_zqcal_ddr3_warm_boot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t emc_zcal_warm_boot_wait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t emc_mrs_warm_boot_enable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t emc_mrs_reset_dll_wait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t emc_mrs_extra; + /* Specifies the extra MRS command at warm boot */ + uint32_t emc_warm_boot_mrs_extra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t emc_ddr2_wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t emc_clken_override; + /* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */ + uint32_t mc_dis_extra_snap_levels; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t emc_extra_refresh_num; + /* Specifies the master override for all EMC clocks */ + uint32_t emc_clken_override_allwarm_boot; + /* Specifies the master override for all MC clocks */ + uint32_t mc_clken_override_allwarm_boot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t emc_cfg_dig_dll_period_warm_boot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel; + /* Specifies the wait time after programming PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel_wait; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t pmc_ddr_pwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t pmc_ddr_cfg; + /* Specifies the value for PMC_IO_DPD3_REQ */ + uint32_t pmc_io_dpd3_req; + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + uint32_t pmc_io_dpd3_req_wait; + /* Specifies the value for PMC_REG_SHORT */ + uint32_t pmc_reg_short; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t pmc_no_io_power; + /* Specifies the wait time after programming PMC_POR_DPD_CTRL */ + uint32_t pmc_por_dpd_ctrl_wait; + /* Specifies the value for EMC_XM2CMDPADCTRL */ + uint32_t emc_xm2cmd_pad_ctrl; + /* Specifies the value for EMC_XM2CMDPADCTRL2 */ + uint32_t emc_xm2cmd_pad_ctrl2; + /* Specifies the value for EMC_XM2CMDPADCTRL3 */ + uint32_t emc_xm2cmd_pad_ctrl3; + /* Specifies the value for EMC_XM2CMDPADCTRL4 */ + uint32_t emc_xm2cmd_pad_ctrl4; + /* Specifies the value for EMC_XM2CMDPADCTRL5 */ + uint32_t emc_xm2cmd_pad_ctrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL */ + uint32_t emc_xm2dqs_pad_ctrl; + /* Specifies the value for EMC_XM2DQSPADCTRL2 */ + uint32_t emc_xm2dqs_pad_ctrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL3 */ + uint32_t emc_xm2dqs_pad_ctrl3; + /* Specifies the value for EMC_XM2DQSPADCTRL4 */ + uint32_t emc_xm2dqs_pad_ctrl4; + /* Specifies the value for EMC_XM2DQSPADCTRL5 */ + uint32_t emc_xm2dqs_pad_ctrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL6 */ + uint32_t emc_xm2dqs_pad_ctrl6; + /* Specifies the value for EMC_XM2DQPADCTRL */ + uint32_t emc_xm2dq_pad_ctrl; + /* Specifies the value for EMC_XM2DQPADCTRL2 */ + uint32_t emc_xm2dq_pad_ctrl2; + /* Specifies the value for EMC_XM2DQPADCTRL3 */ + uint32_t emc_xm2dq_pad_ctrl3; + /* Specifies the value for EMC_XM2CLKPADCTRL */ + uint32_t emc_xm2clk_pad_ctrl; + /* Specifies the value for EMC_XM2CLKPADCTRL2 */ + uint32_t emc_xm2clk_pad_ctrl2; + /* Specifies the value for EMC_XM2COMPPADCTRL */ + uint32_t emc_xm2comp_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL */ + uint32_t emc_xm2vttgen_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ + uint32_t emc_xm2vttgen_pad_ctrl2; + /* Specifies the value for EMC_XM2VTTGENPADCTRL3 */ + uint32_t emc_xm2vttgen_pad_ctrl3; + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t emc_acpd_control; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ + uint32_t emc_swizzle_rank0_byte_cfg; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t emc_swizzle_rank0_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t emc_swizzle_rank0_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t emc_swizzle_rank0_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t emc_swizzle_rank0_byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ + uint32_t emc_swizzle_rank1_byte_cfg; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t emc_swizzle_rank1_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t emc_swizzle_rank1_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t emc_swizzle_rank1_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t emc_swizzle_rank1_byte3; + + /* Specifies the value for EMC_DSR_VTTGEN_DRV */ + uint32_t emc_dsr_vttgen_drv; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t emc_txdsrvttgen; + /* Specifies the value for EMC_BGBIAS_CTL */ + uint32_t emc_bgbias_ctl0; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t mc_emem_adr_cfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t mc_emem_adr_cfg_dev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t mc_emem_adr_cfg_dev1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ + uint32_t mc_emem_adr_cfg_bank_mask0; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + uint32_t mc_emem_adr_cfg_bank_mask1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + uint32_t mc_emem_adr_cfg_bank_mask2; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */ + uint32_t mc_emem_adr_cfg_bank_swizzle3; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t mc_emem_cfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t mc_emem_arb_cfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t mc_emem_arb_outstanding_req; + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t mc_emem_arb_timing_rcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t mc_emem_arb_timing_rp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t mc_emem_arb_timing_rc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t mc_emem_arb_timing_ras; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t mc_emem_arb_timing_faw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t mc_emem_arb_timing_rrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t mc_emem_arb_timing_rap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t mc_emem_arb_timing_wap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t mc_emem_arb_timing_r2r; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t mc_emem_arb_timing_w2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t mc_emem_arb_timing_r2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t mc_emem_arb_timing_w2r; + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t mc_emem_arb_da_turns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t mc_emem_arb_da_covers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t mc_emem_arb_misc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t mc_emem_arb_misc1; + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t mc_emem_arb_ring1_throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t mc_emem_arb_override; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + uint32_t mc_emem_arb_override1; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t mc_emem_arb_rsv; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t mc_clken_override; + + /* Specifies the value for MC_STAT_CONTROL */ + uint32_t mc_stat_control; + /* Specifies the value for MC_DISPLAY_SNAP_RING */ + uint32_t mc_display_snap_ring; + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t mc_video_protect_bom; + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + uint32_t mc_video_protect_bom_adr_hi; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t mc_video_protect_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t mc_video_protect_vpr_override; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + uint32_t mc_video_protect_vpr_override1; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + uint32_t mc_video_protect_gpu_override0; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + uint32_t mc_video_protect_gpu_override1; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t mc_sec_carveout_bom; + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + uint32_t mc_sec_carveout_adr_hi; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t mc_sec_carveout_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ + uint32_t mc_video_protect_write_access; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ + uint32_t mc_sec_carveout_protect_write_access; + + /* Specifies enable for CA training */ + uint32_t emc_ca_training_enable; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ + uint32_t emc_ca_training_timing_cntl1; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ + uint32_t emc_ca_training_timing_cntl2; + /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t swizzle_rank_byte_encode; + /* Specifies enable and offset for patched boot rom write */ + uint32_t boot_rom_patch_control; + /* Specifies data for patched boot rom write */ + uint32_t boot_rom_patch_data; + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + uint32_t mc_mts_carveout_bom; + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + uint32_t mc_mts_carveout_adr_hi; + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + uint32_t mc_mts_carveout_size_mb; + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + uint32_t mc_mts_carveout_reg_ctrl; + + /* End of generated code by warmboot_code_gen */ +} nvboot_sdram_params; +#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T124_H */ + diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t124/parse_t124.c b/firmware/coreboot/util/nvidia/cbootimage/src/t124/parse_t124.c new file mode 100644 index 0000000000..0d80867eea --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t124/parse_t124.c @@ -0,0 +1,429 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * parse_t124.c - The implementation for parsing dev/sdram parameters + */ + +#include "../parse.h" +#include "nvboot_bct_t124.h" + +enum_item s_devtype_table_t124[] = { + { "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc }, + { "NvBootDevType_Spi", nvboot_dev_type_spi }, + { "Sdmmc", nvboot_dev_type_sdmmc }, + { "Spi", nvboot_dev_type_spi }, + { NULL, 0 } +}; + +enum_item s_sdmmc_data_width_table_t124[] = { + { + "NvBootSdmmcDataWidth_4Bit", + nvboot_sdmmc_data_width_4bit + }, + { + "NvBootSdmmcDataWidth_8Bit", + nvboot_sdmmc_data_width_8bit + }, + { "4Bit", nvboot_sdmmc_data_width_4bit }, + { "8Bit", nvboot_sdmmc_data_width_8bit }, + { NULL, 0 } +}; + +enum_item s_spi_clock_source_table_t124[] = { + { "NvBootSpiClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "NvBootSpiClockSource_ClockM", nvboot_spi_clock_source_clockm }, + { "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockSource_ClockM", nvboot_spi_clock_source_clockm }, + { "PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockM", nvboot_spi_clock_source_clockm }, + { NULL, 0 } +}; + +enum_item s_nvboot_memory_type_table_t124[] = { + { "NvBootMemoryType_None", nvboot_memory_type_none }, + { "NvBootMemoryType_Ddr3", nvboot_memory_type_ddr3 }, + { "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 }, + { "NvBootMemoryType_Ddr", nvboot_memory_type_ddr }, + { "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 }, + { "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr }, + + { "None", nvboot_memory_type_none }, + { "Ddr3", nvboot_memory_type_ddr3 }, + { "Ddr2", nvboot_memory_type_ddr2 }, + { "Ddr", nvboot_memory_type_ddr }, + { "LpDdr2", nvboot_memory_type_lpddr2 }, + { "LpDdr", nvboot_memory_type_lpddr }, + + { NULL, 0 } +}; + +#define TOKEN(name) \ + token_##name, field_type_u32, NULL + +field_item s_sdram_field_table_t124[] = { + { "MemoryType", token_memory_type, + field_type_enum, s_nvboot_memory_type_table_t124 }, + + { "PllMInputDivider", TOKEN(pllm_input_divider) }, + { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, + { "PllMStableTime", TOKEN(pllm_stable_time) }, + { "PllMSetupControl", TOKEN(pllm_setup_control) }, + { "PllMSelectDiv2", TOKEN(pllm_select_div2) }, + { "PllMPDLshiftPh45", TOKEN(pllm_pdlshift_ph45) }, + { "PllMPDLshiftPh90", TOKEN(pllm_pdlshift_ph90) }, + { "PllMPDLshiftPh135", TOKEN(pllm_pdlshift_ph135) }, + { "PllMKCP", TOKEN(pllm_kcp) }, + { "PllMKVCO", TOKEN(pllm_kvco) }, + { "EmcBctSpare0", TOKEN(emc_bct_spare0) }, + { "EmcBctSpare1", TOKEN(emc_bct_spare1) }, + { "EmcBctSpare2", TOKEN(emc_bct_spare2) }, + { "EmcBctSpare3", TOKEN(emc_bct_spare3) }, + { "EmcBctSpare4", TOKEN(emc_bct_spare4) }, + { "EmcBctSpare5", TOKEN(emc_bct_spare5) }, + { "EmcBctSpare6", TOKEN(emc_bct_spare6) }, + { "EmcBctSpare7", TOKEN(emc_bct_spare7) }, + { "EmcBctSpare8", TOKEN(emc_bct_spare8) }, + { "EmcBctSpare9", TOKEN(emc_bct_spare9) }, + { "EmcBctSpare10", TOKEN(emc_bct_spare10) }, + { "EmcBctSpare11", TOKEN(emc_bct_spare11) }, + { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, + { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, + { "EmcAutoCalConfig2", TOKEN(emc_auto_cal_config2) }, + { "EmcAutoCalConfig3", TOKEN(emc_auto_cal_config3) }, + { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, + { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, + { "EmcRc", TOKEN(emc_rc) }, + { "EmcRfc", TOKEN(emc_rfc) }, + { "EmcRfcSlr", TOKEN(emc_rfc_slr) }, + { "EmcRas", TOKEN(emc_ras) }, + { "EmcRp", TOKEN(emc_rp) }, + { "EmcR2r", TOKEN(emc_r2r) }, + { "EmcW2w", TOKEN(emc_w2w) }, + { "EmcR2w", TOKEN(emc_r2w) }, + { "EmcW2r", TOKEN(emc_w2r) }, + { "EmcR2p", TOKEN(emc_r2p) }, + { "EmcW2p", TOKEN(emc_w2p) }, + { "EmcRrd", TOKEN(emc_rrd) }, + { "EmcRdRcd", TOKEN(emc_rd_rcd) }, + { "EmcWrRcd", TOKEN(emc_wr_rcd) }, + { "EmcRext", TOKEN(emc_rext) }, + { "EmcWdv", TOKEN(emc_wdv) }, + { "EmcWdvMask", TOKEN(emc_wdv_mask) }, + { "EmcQUse", TOKEN(emc_quse) }, + { "EmcQuseWidth", TOKEN(emc_quse_width) }, + { "EmcIbdly", TOKEN(emc_ibdly) }, + { "EmcEInput", TOKEN(emc_einput) }, + { "EmcEInputDuration", TOKEN(emc_einput_duration) }, + { "EmcPutermExtra", TOKEN(emc_puterm_extra) }, + { "EmcPutermWidth", TOKEN(emc_puterm_width) }, + { "EmcPutermAdj", TOKEN(emc_puterm_adj) }, + { "EmcCdbCntl1", TOKEN(emc_cdb_cntl1) }, + { "EmcCdbCntl2", TOKEN(emc_cdb_cntl2) }, + { "EmcCdbCntl3", TOKEN(emc_cdb_cntl3) }, + { "EmcQRst", TOKEN(emc_qrst) }, + { "EmcQSafe", TOKEN(emc_qsafe) }, + { "EmcRdv", TOKEN(emc_rdv) }, + { "EmcRdvMask", TOKEN(emc_rdv_mask) }, + { "EmcQpop", TOKEN(emc_qpop) }, + { "EmcRefresh", TOKEN(emc_refresh) }, + { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, + { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, + { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, + { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, + { "EmcAct2Pden", TOKEN(emc_act2pden) }, + { "EmcAr2Pden", TOKEN(emc_ar2pden) }, + { "EmcRw2Pden", TOKEN(emc_rw2pden) }, + { "EmcTxsr", TOKEN(emc_txsr) }, + { "EmcTcke", TOKEN(emc_tcke) }, + { "EmcTckesr", TOKEN(emc_tckesr) }, + { "EmcTpd", TOKEN(emc_tpd) }, + { "EmcTfaw", TOKEN(emc_tfaw) }, + { "EmcTrpab", TOKEN(emc_trpab) }, + { "EmcTClkStable", TOKEN(emc_tclkstable) }, + { "EmcTClkStop", TOKEN(emc_tclkstop) }, + { "EmcTRefBw", TOKEN(emc_trefbw) }, + { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, + { "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) }, + { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, + { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, + { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, + { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, + { "EmcMrs", TOKEN(emc_mrs) }, + { "EmcEmrs2", TOKEN(emc_emrs2) }, + { "EmcEmrs3", TOKEN(emc_emrs3) }, + { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, + { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, + { "EmcEmrs", TOKEN(emc_emrs) }, + { "EmcMrw1", TOKEN(emc_mrw1) }, + { "EmcMrw2", TOKEN(emc_mrw2) }, + { "EmcMrw3", TOKEN(emc_mrw3) }, + { "EmcMrw4", TOKEN(emc_mrw4) }, + { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, + { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, + { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, + { "McEmemCfg", TOKEN(mc_emem_cfg) }, + { "EmcCfg2", TOKEN(emc_cfg2) }, + { "EmcCfgPipe", TOKEN(emc_cfg_pipe) }, + { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, + { "EmcCfgDigDllPeriod", TOKEN(emc_cfg_dig_dll_period) }, + { "EmcCfg", TOKEN(emc_cfg) }, + { "EmcDbg", TOKEN(emc_dbg) }, + { "WarmBootWait", TOKEN(warm_boot_wait) }, + { "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) }, + { "EmcOdtWrite", TOKEN(emc_odt_write) }, + { "EmcOdtRead", TOKEN(emc_odt_read) }, + { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, + { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, + { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, + { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, + { "EmcClockSource", TOKEN(emc_clock_source) }, + { "EmcPinExtraWait", TOKEN(emc_pin_extra_wait) }, + { "EmcTimingControlWait", TOKEN(emc_timing_control_wait) }, + { "EmcWext", TOKEN(emc_wext) }, + { "EmcCtt", TOKEN(emc_ctt) }, + { "EmcCttDuration", TOKEN(emc_ctt_duration) }, + { "EmcPreRefreshReqCnt", TOKEN(emc_prerefresh_req_cnt) }, + { "EmcTxsrDll", TOKEN(emc_txsr_dll) }, + { "EmcCfgRsv", TOKEN(emc_cfg_rsv) }, + { "EmcMrwExtra", TOKEN(emc_mrw_extra) }, + { "EmcWarmBootMrwExtra", TOKEN(emc_warm_boot_mrw_extra) }, + { "EmcWarmBootExtraModeRegWriteEnable", + TOKEN(emc_warm_boot_extramode_reg_write_enable) }, + { "EmcExtraModeRegWriteEnable", TOKEN(emc_extramode_reg_write_enable) }, + { "EmcMrsWaitCnt", TOKEN(emc_mrs_wait_cnt) }, + { "EmcMrsWaitCnt2", TOKEN(emc_mrs_wait_cnt2) }, + { "EmcCmdQ", TOKEN(emc_cmd_q) }, + { "EmcMc2EmcQ", TOKEN(emc_mc2emc_q) }, + { "EmcDynSelfRefControl", TOKEN(emc_dyn_self_ref_control) }, + { "AhbArbitrationXbarCtrlMemInitDone", + TOKEN(ahb_arbitration_xbar_ctrl_meminit_done) }, + { "EmcDevSelect", TOKEN(emc_dev_select) }, + { "EmcSelDpdCtrl", TOKEN(emc_sel_dpd_ctrl) }, + { "EmcDllXformDqs0", TOKEN(emc_dll_xform_dqs0) }, + { "EmcDllXformDqs1", TOKEN(emc_dll_xform_dqs1) }, + { "EmcDllXformDqs2", TOKEN(emc_dll_xform_dqs2) }, + { "EmcDllXformDqs3", TOKEN(emc_dll_xform_dqs3) }, + { "EmcDllXformDqs4", TOKEN(emc_dll_xform_dqs4) }, + { "EmcDllXformDqs5", TOKEN(emc_dll_xform_dqs5) }, + { "EmcDllXformDqs6", TOKEN(emc_dll_xform_dqs6) }, + { "EmcDllXformDqs7", TOKEN(emc_dll_xform_dqs7) }, + { "EmcDllXformDqs8", TOKEN(emc_dll_xform_dqs8) }, + { "EmcDllXformDqs9", TOKEN(emc_dll_xform_dqs9) }, + { "EmcDllXformDqs10", TOKEN(emc_dll_xform_dqs10) }, + { "EmcDllXformDqs11", TOKEN(emc_dll_xform_dqs11) }, + { "EmcDllXformDqs12", TOKEN(emc_dll_xform_dqs12) }, + { "EmcDllXformDqs13", TOKEN(emc_dll_xform_dqs13) }, + { "EmcDllXformDqs14", TOKEN(emc_dll_xform_dqs14) }, + { "EmcDllXformDqs15", TOKEN(emc_dll_xform_dqs15) }, + { "EmcDllXformQUse0", TOKEN(emc_dll_xform_quse0) }, + { "EmcDllXformQUse1", TOKEN(emc_dll_xform_quse1) }, + { "EmcDllXformQUse2", TOKEN(emc_dll_xform_quse2) }, + { "EmcDllXformQUse3", TOKEN(emc_dll_xform_quse3) }, + { "EmcDllXformQUse4", TOKEN(emc_dll_xform_quse4) }, + { "EmcDllXformQUse5", TOKEN(emc_dll_xform_quse5) }, + { "EmcDllXformQUse6", TOKEN(emc_dll_xform_quse6) }, + { "EmcDllXformQUse7", TOKEN(emc_dll_xform_quse7) }, + { "EmcDllXformAddr0", TOKEN(emc_dll_xform_addr0) }, + { "EmcDllXformAddr1", TOKEN(emc_dll_xform_addr1) }, + { "EmcDllXformAddr2", TOKEN(emc_dll_xform_addr2) }, + { "EmcDllXformAddr3", TOKEN(emc_dll_xform_addr3) }, + { "EmcDllXformAddr4", TOKEN(emc_dll_xform_addr4) }, + { "EmcDllXformAddr5", TOKEN(emc_dll_xform_addr5) }, + { "EmcDllXformQUse8", TOKEN(emc_dll_xform_quse8) }, + { "EmcDllXformQUse9", TOKEN(emc_dll_xform_quse9) }, + { "EmcDllXformQUse10", TOKEN(emc_dll_xform_quse10) }, + { "EmcDllXformQUse11", TOKEN(emc_dll_xform_quse11) }, + { "EmcDllXformQUse12", TOKEN(emc_dll_xform_quse12) }, + { "EmcDllXformQUse13", TOKEN(emc_dll_xform_quse13) }, + { "EmcDllXformQUse14", TOKEN(emc_dll_xform_quse14) }, + { "EmcDllXformQUse15", TOKEN(emc_dll_xform_quse15) }, + { "EmcDliTrimTxDqs0", TOKEN(emc_dli_trim_tx_dqs0) }, + { "EmcDliTrimTxDqs1", TOKEN(emc_dli_trim_tx_dqs1) }, + { "EmcDliTrimTxDqs2", TOKEN(emc_dli_trim_tx_dqs2) }, + { "EmcDliTrimTxDqs3", TOKEN(emc_dli_trim_tx_dqs3) }, + { "EmcDliTrimTxDqs4", TOKEN(emc_dli_trim_tx_dqs4) }, + { "EmcDliTrimTxDqs5", TOKEN(emc_dli_trim_tx_dqs5) }, + { "EmcDliTrimTxDqs6", TOKEN(emc_dli_trim_tx_dqs6) }, + { "EmcDliTrimTxDqs7", TOKEN(emc_dli_trim_tx_dqs7) }, + { "EmcDliTrimTxDqs8", TOKEN(emc_dli_trim_tx_dqs8) }, + { "EmcDliTrimTxDqs9", TOKEN(emc_dli_trim_tx_dqs9) }, + { "EmcDliTrimTxDqs10", TOKEN(emc_dli_trim_tx_dqs10) }, + { "EmcDliTrimTxDqs11", TOKEN(emc_dli_trim_tx_dqs11) }, + { "EmcDliTrimTxDqs12", TOKEN(emc_dli_trim_tx_dqs12) }, + { "EmcDliTrimTxDqs13", TOKEN(emc_dli_trim_tx_dqs13) }, + { "EmcDliTrimTxDqs14", TOKEN(emc_dli_trim_tx_dqs14) }, + { "EmcDliTrimTxDqs15", TOKEN(emc_dli_trim_tx_dqs15) }, + { "EmcDllXformDq0", TOKEN(emc_dll_xform_dq0) }, + { "EmcDllXformDq1", TOKEN(emc_dll_xform_dq1) }, + { "EmcDllXformDq2", TOKEN(emc_dll_xform_dq2) }, + { "EmcDllXformDq3", TOKEN(emc_dll_xform_dq3) }, + { "EmcDllXformDq4", TOKEN(emc_dll_xform_dq4) }, + { "EmcDllXformDq5", TOKEN(emc_dll_xform_dq5) }, + { "EmcDllXformDq6", TOKEN(emc_dll_xform_dq6) }, + { "EmcDllXformDq7", TOKEN(emc_dll_xform_dq7) }, + { "EmcZcalInterval", TOKEN(emc_zcal_interval) }, + { "EmcZcalInitDev0", TOKEN(emc_zcal_init_dev0) }, + { "EmcZcalInitDev1", TOKEN(emc_zcal_init_dev1) }, + { "EmcZcalInitWait", TOKEN(emc_zcal_init_wait) }, + { "EmcZcalWarmColdBootEnables", TOKEN(emc_zcal_warm_cold_boot_enables) }, + { "EmcMrwLpddr2ZcalWarmBoot", TOKEN(emc_mrw_lpddr2zcal_warm_boot) }, + { "EmcZqCalDdr3WarmBoot", TOKEN(emc_zqcal_ddr3_warm_boot) }, + { "EmcZcalWarmBootWait", TOKEN(emc_zcal_warm_boot_wait) }, + { "EmcMrsWarmBootEnable", TOKEN(emc_mrs_warm_boot_enable) }, + { "EmcMrsExtra", TOKEN(emc_mrs_extra) }, + { "EmcWarmBootMrsExtra", TOKEN(emc_warm_boot_mrs_extra) }, + { "EmcClkenOverride", TOKEN(emc_clken_override) }, + { "McDisExtraSnapLevels", TOKEN(mc_dis_extra_snap_levels) }, + { "EmcExtraRefreshNum", TOKEN(emc_extra_refresh_num) }, + { "EmcClkenOverrideAllWarmBoot", + TOKEN(emc_clken_override_allwarm_boot) }, + { "McClkenOverrideAllWarmBoot", TOKEN(mc_clken_override_allwarm_boot) }, + { "EmcCfgDigDllPeriodWarmBoot", + TOKEN(emc_cfg_dig_dll_period_warm_boot) }, + { "PmcVddpSel", TOKEN(pmc_vddp_sel) }, + { "PmcVddpSelWait", TOKEN(pmc_vddp_sel_wait) }, + { "PmcDdrCfg", TOKEN(pmc_ddr_cfg) }, + { "PmcIoDpd3Req", TOKEN(pmc_io_dpd3_req) }, + { "PmcIoDpd3ReqWait", TOKEN(pmc_io_dpd3_req_wait) }, + { "PmcRegShort", TOKEN(pmc_reg_short) }, + { "PmcNoIoPower", TOKEN(pmc_no_io_power) }, + { "PmcPorDpdCtrlWait", TOKEN(pmc_por_dpd_ctrl_wait) }, + { "EmcXm2CmdPadCtrl", TOKEN(emc_xm2cmd_pad_ctrl) }, + { "EmcXm2CmdPadCtrl2", TOKEN(emc_xm2cmd_pad_ctrl2) }, + { "EmcXm2CmdPadCtrl3", TOKEN(emc_xm2cmd_pad_ctrl3) }, + { "EmcXm2CmdPadCtrl4", TOKEN(emc_xm2cmd_pad_ctrl4) }, + { "EmcXm2CmdPadCtrl5", TOKEN(emc_xm2cmd_pad_ctrl5) }, + { "EmcXm2DqsPadCtrl", TOKEN(emc_xm2dqs_pad_ctrl) }, + { "EmcXm2DqsPadCtrl2", TOKEN(emc_xm2dqs_pad_ctrl2) }, + { "EmcXm2DqsPadCtrl3", TOKEN(emc_xm2dqs_pad_ctrl3) }, + { "EmcXm2DqsPadCtrl4", TOKEN(emc_xm2dqs_pad_ctrl4) }, + { "EmcXm2DqsPadCtrl5", TOKEN(emc_xm2dqs_pad_ctrl5) }, + { "EmcXm2DqsPadCtrl6", TOKEN(emc_xm2dqs_pad_ctrl6) }, + { "EmcXm2DqPadCtrl", TOKEN(emc_xm2dq_pad_ctrl) }, + { "EmcXm2DqPadCtrl2", TOKEN(emc_xm2dq_pad_ctrl2) }, + { "EmcXm2DqPadCtrl3", TOKEN(emc_xm2dq_pad_ctrl3) }, + { "EmcXm2ClkPadCtrl", TOKEN(emc_xm2clk_pad_ctrl) }, + { "EmcXm2ClkPadCtrl2", TOKEN(emc_xm2clk_pad_ctrl2) }, + { "EmcXm2CompPadCtrl", TOKEN(emc_xm2comp_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl", TOKEN(emc_xm2vttgen_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl2", TOKEN(emc_xm2vttgen_pad_ctrl2) }, + { "EmcXm2VttGenPadCtrl3", TOKEN(emc_xm2vttgen_pad_ctrl3) }, + { "EmcAcpdControl", TOKEN(emc_acpd_control) }, + { "EmcSwizzleRank0ByteCfg", TOKEN(emc_swizzle_rank0_byte_cfg) }, + { "EmcSwizzleRank0Byte0", TOKEN(emc_swizzle_rank0_byte0) }, + { "EmcSwizzleRank0Byte1", TOKEN(emc_swizzle_rank0_byte1) }, + { "EmcSwizzleRank0Byte2", TOKEN(emc_swizzle_rank0_byte2) }, + { "EmcSwizzleRank0Byte3", TOKEN(emc_swizzle_rank0_byte3) }, + { "EmcSwizzleRank1ByteCfg", TOKEN(emc_swizzle_rank1_byte_cfg) }, + { "EmcSwizzleRank1Byte0", TOKEN(emc_swizzle_rank1_byte0) }, + { "EmcSwizzleRank1Byte1", TOKEN(emc_swizzle_rank1_byte1) }, + { "EmcSwizzleRank1Byte2", TOKEN(emc_swizzle_rank1_byte2) }, + { "EmcSwizzleRank1Byte3", TOKEN(emc_swizzle_rank1_byte3) }, + { "EmcDsrVttgenDrv", TOKEN(emc_dsr_vttgen_drv) }, + { "EmcTxdsrvttgen", TOKEN(emc_txdsrvttgen) }, + { "EmcBgbiasCtl0", TOKEN(emc_bgbias_ctl0) }, + { "McEmemAdrCfg", TOKEN(mc_emem_adr_cfg) }, + { "McEmemAdrCfgDev0", TOKEN(mc_emem_adr_cfg_dev0) }, + { "McEmemAdrCfgDev1", TOKEN(mc_emem_adr_cfg_dev1) }, + { "McEmemAdrCfgBankMask0", TOKEN(mc_emem_adr_cfg_bank_mask0) }, + { "McEmemAdrCfgBankMask1", TOKEN(mc_emem_adr_cfg_bank_mask1) }, + { "McEmemAdrCfgBankMask2", TOKEN(mc_emem_adr_cfg_bank_mask2) }, + { "McEmemAdrCfgBankSwizzle3", TOKEN(mc_emem_adr_cfg_bank_swizzle3) }, + { "McEmemArbCfg", TOKEN(mc_emem_arb_cfg) }, + { "McEmemArbOutstandingReq", TOKEN(mc_emem_arb_outstanding_req) }, + { "McEmemArbTimingRcd", TOKEN(mc_emem_arb_timing_rcd) }, + { "McEmemArbTimingRp", TOKEN(mc_emem_arb_timing_rp) }, + { "McEmemArbTimingRc", TOKEN(mc_emem_arb_timing_rc) }, + { "McEmemArbTimingRas", TOKEN(mc_emem_arb_timing_ras) }, + { "McEmemArbTimingFaw", TOKEN(mc_emem_arb_timing_faw) }, + { "McEmemArbTimingRrd", TOKEN(mc_emem_arb_timing_rrd) }, + { "McEmemArbTimingRap2Pre", TOKEN(mc_emem_arb_timing_rap2pre) }, + { "McEmemArbTimingWap2Pre", TOKEN(mc_emem_arb_timing_wap2pre) }, + { "McEmemArbTimingR2R", TOKEN(mc_emem_arb_timing_r2r) }, + { "McEmemArbTimingW2W", TOKEN(mc_emem_arb_timing_w2w) }, + { "McEmemArbTimingR2W", TOKEN(mc_emem_arb_timing_r2w) }, + { "McEmemArbTimingW2R", TOKEN(mc_emem_arb_timing_w2r) }, + { "McEmemArbDaTurns", TOKEN(mc_emem_arb_da_turns) }, + { "McEmemArbDaCovers", TOKEN(mc_emem_arb_da_covers) }, + { "McEmemArbMisc0", TOKEN(mc_emem_arb_misc0) }, + { "McEmemArbMisc1", TOKEN(mc_emem_arb_misc1) }, + { "McEmemArbRing1Throttle", TOKEN(mc_emem_arb_ring1_throttle) }, + { "McEmemArbOverride", TOKEN(mc_emem_arb_override) }, + { "McEmemArbOverride1", TOKEN(mc_emem_arb_override1) }, + { "McEmemArbRsv", TOKEN(mc_emem_arb_rsv) }, + { "McClkenOverride", TOKEN(mc_clken_override) }, + { "McStatControl", TOKEN(mc_stat_control) }, + { "McDisplaySnapRing", TOKEN(mc_display_snap_ring) }, + { "McVideoProtectBom", TOKEN(mc_video_protect_bom) }, + { "McVideoProtectBomAdrHi", + TOKEN(mc_video_protect_bom_adr_hi) }, + { "McVideoProtectSizeMb", TOKEN(mc_video_protect_size_mb) }, + { "McVideoProtectVprOverride", TOKEN(mc_video_protect_vpr_override) }, + { "McVideoProtectVprOverride1", TOKEN(mc_video_protect_vpr_override1) }, + { "McVideoProtectGpuOverride0", TOKEN(mc_video_protect_gpu_override0) }, + { "McVideoProtectGpuOverride1", TOKEN(mc_video_protect_gpu_override1) }, + { "McSecCarveoutBom", TOKEN(mc_sec_carveout_bom) }, + { "McSecCarveoutAdrHi", TOKEN(mc_sec_carveout_adr_hi) }, + { "McSecCarveoutSizeMb", TOKEN(mc_sec_carveout_size_mb) }, + { "McVideoProtectWriteAccess", TOKEN(mc_video_protect_write_access) }, + { "McSecCarveoutProtectWriteAccess", + TOKEN(mc_sec_carveout_protect_write_access) }, + { "EmcCaTrainingEnable", TOKEN(emc_ca_training_enable) }, + { "EmcCaTrainingTimingCntl1", TOKEN(emc_ca_training_timing_cntl1) }, + { "EmcCaTrainingTimingCntl2", TOKEN(emc_ca_training_timing_cntl2) }, + { "SwizzleRankByteEncode", TOKEN(swizzle_rank_byte_encode) }, + { "BootRomPatchControl", TOKEN(boot_rom_patch_control) }, + { "BootRomPatchData", TOKEN(boot_rom_patch_data) }, + { "McMtsCarveoutBom", TOKEN(mc_mts_carveout_bom) }, + { "McMtsCarveoutAdrHi", TOKEN(mc_mts_carveout_adr_hi) }, + { "McMtsCarveoutSizeMb", TOKEN(mc_mts_carveout_size_mb) }, + { "McMtsCarveoutRegCtrl", TOKEN(mc_mts_carveout_reg_ctrl) }, + { NULL, 0, 0, NULL } +}; + +field_item s_sdmmc_table_t124[] = { + { "ClockDivider", TOKEN(sdmmc_clock_divider) }, + { "DataWidth", + token_sdmmc_data_width, + field_type_enum, + s_sdmmc_data_width_table_t124 }, + { "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) }, + { "MultiPageSupport", TOKEN(sdmmc_multi_page_support) }, + { NULL, 0, 0, NULL } +}; + +field_item s_spiflash_table_t124[] = { + { "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) }, + { "PageSize2kor16k", TOKEN(spiflash_page_size_2k_or_16k) }, + { "ClockDivider", TOKEN(spiflash_clock_divider) }, + { "ClockSource", + token_spiflash_clock_source, + field_type_enum, + s_spi_clock_source_table_t124 }, + { NULL, 0, 0, NULL } +}; + +parse_subfield_item s_device_type_table_t124[] = { + { "SdmmcParams.", token_sdmmc_params, + s_sdmmc_table_t124, t124_set_dev_param }, + { "SpiFlashParams.", token_spiflash_params, + s_spiflash_table_t124, t124_set_dev_param }, + { NULL, 0, NULL } +}; diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t132/nvbctlib_t132.c b/firmware/coreboot/util/nvidia/cbootimage/src/t132/nvbctlib_t132.c new file mode 100644 index 0000000000..5f3af0f440 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t132/nvbctlib_t132.c @@ -0,0 +1,1241 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include "../cbootimage.h" +#include "../parse.h" +#include "../crypto.h" +#include "nvboot_bct_t132.h" +#include "string.h" + +/* nvbctlib_t132.c: The implementation of the nvbctlib API for t132. */ + +/* Definitions that simplify the code which follows. */ +#define CASE_GET_SDRAM_PARAM(x) \ +case token_##x:\ + *value = params->x; \ + break + +#define CASE_SET_SDRAM_PARAM(x) \ +case token_##x:\ + params->x = value; \ + break + +#define CASE_GET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + *value = bct->dev_params[index].dev##_params.x; \ + break + +#define CASE_SET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + bct->dev_params[index].dev##_params.x = value; \ + break + +#define CASE_GET_BL_PARAM(x) \ +case token_bl_##x:\ + *data = bct_ptr->bootloader[set].x; \ + break + +#define CASE_SET_BL_PARAM(x) \ +case token_bl_##x:\ + bct_ptr->bootloader[set].x = *data; \ + break + +#define CASE_GET_NVU32(id) \ +case token_##id:\ + if (bct == NULL) \ + return -ENODATA; \ + *((uint32_t *)data) = bct_ptr->id; \ + break + +#define CASE_GET_CONST(id, val) \ +case token_##id:\ + *((uint32_t *)data) = val; \ + break + +#define CASE_GET_CONST_PREFIX(id, val_prefix) \ +case token_##id:\ + *((uint32_t *)data) = val_prefix##_##id; \ + break + +#define CASE_SET_NVU32(id) \ +case token_##id:\ + bct_ptr->id = *((uint32_t *)data); \ + break + +#define CASE_GET_DATA(id, size) \ +case token_##id:\ + if (*length < size) \ + return -ENODATA;\ + memcpy(data, &(bct_ptr->id), size); \ + *length = size;\ + break + +#define CASE_SET_DATA(id, size) \ +case token_##id:\ + if (length < size) \ + return -ENODATA;\ + memcpy(&(bct_ptr->id), data, size); \ + break + +#define CASE_GET_MTS_INFO(x) \ +case token_mts_info_##x:\ + *value = mts_info->x; \ + break + +#define CASE_SET_MTS_INFO(x) \ +case token_mts_info_##x:\ + mts_info->x = value; \ + break + +#define DEFAULT() \ +default : \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +parse_token t132_root_token_list[] = { + token_boot_data_version, + token_block_size, + token_page_size, + token_partition_size, + token_odm_data, + token_bootloader_used, + token_bootloaders_max, + token_bct_size, + token_hash_size, + token_crypto_offset, + token_crypto_length, + token_max_bct_search_blks, + token_unique_chip_id, + token_secure_jtag_control, + token_mts_used, + token_mts_max +}; + +int +t132_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1); + + switch (token) { + CASE_SET_DEV_PARAM(sdmmc, clock_divider); + CASE_SET_DEV_PARAM(sdmmc, data_width); + CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_SET_DEV_PARAM(sdmmc, multi_page_support); + + CASE_SET_DEV_PARAM(spiflash, clock_source); + CASE_SET_DEV_PARAM(spiflash, clock_divider); + CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + CASE_SET_DEV_PARAM(spiflash, page_size_2k_or_16k); + + case token_dev_type: + bct->dev_type[index] = value; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t132_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + switch (token) { + CASE_GET_DEV_PARAM(sdmmc, clock_divider); + CASE_GET_DEV_PARAM(sdmmc, data_width); + CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_GET_DEV_PARAM(sdmmc, multi_page_support); + + CASE_GET_DEV_PARAM(spiflash, clock_source); + CASE_GET_DEV_PARAM(spiflash, clock_divider); + CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); + CASE_GET_DEV_PARAM(spiflash, page_size_2k_or_16k); + + case token_dev_type: + *value = bct->dev_type[index]; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t132_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + + switch (token) { + CASE_GET_SDRAM_PARAM(memory_type); + CASE_GET_SDRAM_PARAM(pllm_input_divider); + CASE_GET_SDRAM_PARAM(pllm_feedback_divider); + CASE_GET_SDRAM_PARAM(pllm_stable_time); + CASE_GET_SDRAM_PARAM(pllm_setup_control); + CASE_GET_SDRAM_PARAM(pllm_select_div2); + CASE_GET_SDRAM_PARAM(pllm_pdlshift_ph45); + CASE_GET_SDRAM_PARAM(pllm_pdlshift_ph90); + CASE_GET_SDRAM_PARAM(pllm_pdlshift_ph135); + CASE_GET_SDRAM_PARAM(pllm_kcp); + CASE_GET_SDRAM_PARAM(pllm_kvco); + CASE_GET_SDRAM_PARAM(emc_bct_spare0); + CASE_GET_SDRAM_PARAM(emc_bct_spare1); + CASE_GET_SDRAM_PARAM(emc_bct_spare2); + CASE_GET_SDRAM_PARAM(emc_bct_spare3); + CASE_GET_SDRAM_PARAM(emc_bct_spare4); + CASE_GET_SDRAM_PARAM(emc_bct_spare5); + CASE_GET_SDRAM_PARAM(emc_bct_spare6); + CASE_GET_SDRAM_PARAM(emc_bct_spare7); + CASE_GET_SDRAM_PARAM(emc_bct_spare8); + CASE_GET_SDRAM_PARAM(emc_bct_spare9); + CASE_GET_SDRAM_PARAM(emc_bct_spare10); + CASE_GET_SDRAM_PARAM(emc_bct_spare11); + CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config2); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config3); + CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_GET_SDRAM_PARAM(emc_pin_program_wait); + CASE_GET_SDRAM_PARAM(emc_rc); + CASE_GET_SDRAM_PARAM(emc_rfc); + CASE_GET_SDRAM_PARAM(emc_rfc_slr); + CASE_GET_SDRAM_PARAM(emc_ras); + CASE_GET_SDRAM_PARAM(emc_rp); + CASE_GET_SDRAM_PARAM(emc_r2r); + CASE_GET_SDRAM_PARAM(emc_w2w); + CASE_GET_SDRAM_PARAM(emc_r2w); + CASE_GET_SDRAM_PARAM(emc_w2r); + CASE_GET_SDRAM_PARAM(emc_r2p); + CASE_GET_SDRAM_PARAM(emc_w2p); + CASE_GET_SDRAM_PARAM(emc_rd_rcd); + CASE_GET_SDRAM_PARAM(emc_wr_rcd); + CASE_GET_SDRAM_PARAM(emc_rrd); + CASE_GET_SDRAM_PARAM(emc_rext); + CASE_GET_SDRAM_PARAM(emc_wdv); + CASE_GET_SDRAM_PARAM(emc_wdv_mask); + CASE_GET_SDRAM_PARAM(emc_quse); + CASE_GET_SDRAM_PARAM(emc_quse_width); + CASE_GET_SDRAM_PARAM(emc_ibdly); + CASE_GET_SDRAM_PARAM(emc_einput); + CASE_GET_SDRAM_PARAM(emc_einput_duration); + CASE_GET_SDRAM_PARAM(emc_puterm_extra); + CASE_GET_SDRAM_PARAM(emc_puterm_width); + CASE_GET_SDRAM_PARAM(emc_puterm_adj); + CASE_GET_SDRAM_PARAM(emc_cdb_cntl1); + CASE_GET_SDRAM_PARAM(emc_cdb_cntl2); + CASE_GET_SDRAM_PARAM(emc_cdb_cntl3); + CASE_GET_SDRAM_PARAM(emc_qrst); + CASE_GET_SDRAM_PARAM(emc_qsafe); + CASE_GET_SDRAM_PARAM(emc_rdv); + CASE_GET_SDRAM_PARAM(emc_rdv_mask); + CASE_GET_SDRAM_PARAM(emc_qpop); + CASE_GET_SDRAM_PARAM(emc_refresh); + CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_GET_SDRAM_PARAM(emc_pdex2wr); + CASE_GET_SDRAM_PARAM(emc_pdex2rd); + CASE_GET_SDRAM_PARAM(emc_pchg2pden); + CASE_GET_SDRAM_PARAM(emc_act2pden); + CASE_GET_SDRAM_PARAM(emc_ar2pden); + CASE_GET_SDRAM_PARAM(emc_rw2pden); + CASE_GET_SDRAM_PARAM(emc_txsr); + CASE_GET_SDRAM_PARAM(emc_tcke); + CASE_GET_SDRAM_PARAM(emc_tckesr); + CASE_GET_SDRAM_PARAM(emc_tpd); + CASE_GET_SDRAM_PARAM(emc_tfaw); + CASE_GET_SDRAM_PARAM(emc_trpab); + CASE_GET_SDRAM_PARAM(emc_tclkstable); + CASE_GET_SDRAM_PARAM(emc_tclkstop); + CASE_GET_SDRAM_PARAM(emc_trefbw); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_GET_SDRAM_PARAM(emc_fbio_spare); + CASE_GET_SDRAM_PARAM(emc_mrs); + CASE_GET_SDRAM_PARAM(emc_emrs); + CASE_GET_SDRAM_PARAM(emc_emrs2); + CASE_GET_SDRAM_PARAM(emc_emrs3); + CASE_GET_SDRAM_PARAM(emc_mrw1); + CASE_GET_SDRAM_PARAM(emc_mrw2); + CASE_GET_SDRAM_PARAM(emc_mrw3); + CASE_GET_SDRAM_PARAM(emc_mrw4); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_GET_SDRAM_PARAM(emc_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg2); + CASE_GET_SDRAM_PARAM(emc_cfg_pipe); + CASE_GET_SDRAM_PARAM(emc_dbg); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_GET_SDRAM_PARAM(warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_GET_SDRAM_PARAM(emc_odt_write); + CASE_GET_SDRAM_PARAM(emc_odt_read); + CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_GET_SDRAM_PARAM(emc_ddr2_wait); + CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_GET_SDRAM_PARAM(emc_clock_source); + CASE_GET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_GET_SDRAM_PARAM(emc_timing_control_wait); + CASE_GET_SDRAM_PARAM(emc_wext); + CASE_GET_SDRAM_PARAM(emc_ctt); + CASE_GET_SDRAM_PARAM(emc_ctt_duration); + CASE_GET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_GET_SDRAM_PARAM(emc_txsr_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_rsv); + CASE_GET_SDRAM_PARAM(emc_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt2); + CASE_GET_SDRAM_PARAM(emc_cmd_q); + CASE_GET_SDRAM_PARAM(emc_mc2emc_q); + CASE_GET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_GET_SDRAM_PARAM(emc_dev_select); + CASE_GET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs8); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs9); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs10); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs11); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs12); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs13); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs14); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs15); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_addr5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse8); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse9); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse10); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse11); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse12); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse13); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse14); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse15); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs8); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs9); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs10); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs11); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs12); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs13); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs14); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs15); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq7); + CASE_GET_SDRAM_PARAM(emc_zcal_interval); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_GET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_cold_boot_enables); + CASE_GET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_clken_override); + CASE_GET_SDRAM_PARAM(mc_dis_extra_snap_levels); + CASE_GET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_GET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_GET_SDRAM_PARAM(pmc_vddp_sel); + CASE_GET_SDRAM_PARAM(pmc_vddp_sel_wait); + CASE_GET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_GET_SDRAM_PARAM(pmc_io_dpd3_req); + CASE_GET_SDRAM_PARAM(pmc_io_dpd3_req_wait); + CASE_GET_SDRAM_PARAM(pmc_reg_short); + CASE_GET_SDRAM_PARAM(pmc_no_io_power); + CASE_GET_SDRAM_PARAM(pmc_por_dpd_ctrl_wait); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl4); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl5); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl4); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl5); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl6); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2clk_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_acpd_control); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte_cfg); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte0); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte1); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte2); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte3); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte_cfg); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte0); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte1); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte2); + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte3); + CASE_GET_SDRAM_PARAM(emc_dsr_vttgen_drv); + CASE_GET_SDRAM_PARAM(emc_txdsrvttgen); + CASE_GET_SDRAM_PARAM(emc_bgbias_ctl0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask1); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask2); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_swizzle3); + CASE_GET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_GET_SDRAM_PARAM(mc_emem_arb_override); + CASE_GET_SDRAM_PARAM(mc_emem_arb_override1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_GET_SDRAM_PARAM(mc_clken_override); + CASE_GET_SDRAM_PARAM(mc_stat_control); + CASE_GET_SDRAM_PARAM(mc_display_snap_ring); + CASE_GET_SDRAM_PARAM(mc_video_protect_bom); + CASE_GET_SDRAM_PARAM(mc_video_protect_bom_adr_hi); + CASE_GET_SDRAM_PARAM(mc_video_protect_size_mb); + CASE_GET_SDRAM_PARAM(mc_video_protect_vpr_override); + CASE_GET_SDRAM_PARAM(mc_video_protect_vpr_override1); + CASE_GET_SDRAM_PARAM(mc_video_protect_gpu_override0); + CASE_GET_SDRAM_PARAM(mc_video_protect_gpu_override1); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_bom); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_adr_hi); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_size_mb); + CASE_GET_SDRAM_PARAM(mc_video_protect_write_access); + CASE_GET_SDRAM_PARAM(mc_sec_carveout_protect_write_access); + CASE_GET_SDRAM_PARAM(emc_ca_training_enable); + CASE_GET_SDRAM_PARAM(emc_ca_training_timing_cntl1); + CASE_GET_SDRAM_PARAM(emc_ca_training_timing_cntl2); + CASE_GET_SDRAM_PARAM(swizzle_rank_byte_encode); + CASE_GET_SDRAM_PARAM(boot_rom_patch_control); + CASE_GET_SDRAM_PARAM(boot_rom_patch_data); + CASE_GET_SDRAM_PARAM(mc_mts_carveout_bom); + CASE_GET_SDRAM_PARAM(mc_mts_carveout_adr_hi); + CASE_GET_SDRAM_PARAM(mc_mts_carveout_size_mb); + CASE_GET_SDRAM_PARAM(mc_mts_carveout_reg_ctrl); + + DEFAULT(); + } + return 0; +} + +int +t132_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + /* Update the number of SDRAM parameter sets. */ + bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1); + + switch (token) { + CASE_SET_SDRAM_PARAM(memory_type); + CASE_SET_SDRAM_PARAM(pllm_input_divider); + CASE_SET_SDRAM_PARAM(pllm_feedback_divider); + CASE_SET_SDRAM_PARAM(pllm_stable_time); + CASE_SET_SDRAM_PARAM(pllm_setup_control); + CASE_SET_SDRAM_PARAM(pllm_select_div2); + CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph45); + CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph90); + CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph135); + CASE_SET_SDRAM_PARAM(pllm_kcp); + CASE_SET_SDRAM_PARAM(pllm_kvco); + CASE_SET_SDRAM_PARAM(emc_bct_spare0); + CASE_SET_SDRAM_PARAM(emc_bct_spare1); + CASE_SET_SDRAM_PARAM(emc_bct_spare2); + CASE_SET_SDRAM_PARAM(emc_bct_spare3); + CASE_SET_SDRAM_PARAM(emc_bct_spare4); + CASE_SET_SDRAM_PARAM(emc_bct_spare5); + CASE_SET_SDRAM_PARAM(emc_bct_spare6); + CASE_SET_SDRAM_PARAM(emc_bct_spare7); + CASE_SET_SDRAM_PARAM(emc_bct_spare8); + CASE_SET_SDRAM_PARAM(emc_bct_spare9); + CASE_SET_SDRAM_PARAM(emc_bct_spare10); + CASE_SET_SDRAM_PARAM(emc_bct_spare11); + CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config2); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config3); + CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_SET_SDRAM_PARAM(emc_pin_program_wait); + CASE_SET_SDRAM_PARAM(emc_rc); + CASE_SET_SDRAM_PARAM(emc_rfc); + CASE_SET_SDRAM_PARAM(emc_rfc_slr); + CASE_SET_SDRAM_PARAM(emc_ras); + CASE_SET_SDRAM_PARAM(emc_rp); + CASE_SET_SDRAM_PARAM(emc_r2r); + CASE_SET_SDRAM_PARAM(emc_w2w); + CASE_SET_SDRAM_PARAM(emc_r2w); + CASE_SET_SDRAM_PARAM(emc_w2r); + CASE_SET_SDRAM_PARAM(emc_r2p); + CASE_SET_SDRAM_PARAM(emc_w2p); + CASE_SET_SDRAM_PARAM(emc_rd_rcd); + CASE_SET_SDRAM_PARAM(emc_wr_rcd); + CASE_SET_SDRAM_PARAM(emc_rrd); + CASE_SET_SDRAM_PARAM(emc_rext); + CASE_SET_SDRAM_PARAM(emc_wdv); + CASE_SET_SDRAM_PARAM(emc_wdv_mask); + CASE_SET_SDRAM_PARAM(emc_quse); + CASE_SET_SDRAM_PARAM(emc_quse_width); + CASE_SET_SDRAM_PARAM(emc_ibdly); + CASE_SET_SDRAM_PARAM(emc_einput); + CASE_SET_SDRAM_PARAM(emc_einput_duration); + CASE_SET_SDRAM_PARAM(emc_puterm_extra); + CASE_SET_SDRAM_PARAM(emc_puterm_width); + CASE_SET_SDRAM_PARAM(emc_puterm_adj); + CASE_SET_SDRAM_PARAM(emc_cdb_cntl1); + CASE_SET_SDRAM_PARAM(emc_cdb_cntl2); + CASE_SET_SDRAM_PARAM(emc_cdb_cntl3); + CASE_SET_SDRAM_PARAM(emc_qrst); + CASE_SET_SDRAM_PARAM(emc_qsafe); + CASE_SET_SDRAM_PARAM(emc_rdv); + CASE_SET_SDRAM_PARAM(emc_rdv_mask); + CASE_SET_SDRAM_PARAM(emc_qpop); + CASE_SET_SDRAM_PARAM(emc_refresh); + CASE_SET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_SET_SDRAM_PARAM(emc_pdex2wr); + CASE_SET_SDRAM_PARAM(emc_pdex2rd); + CASE_SET_SDRAM_PARAM(emc_pchg2pden); + CASE_SET_SDRAM_PARAM(emc_act2pden); + CASE_SET_SDRAM_PARAM(emc_ar2pden); + CASE_SET_SDRAM_PARAM(emc_rw2pden); + CASE_SET_SDRAM_PARAM(emc_txsr); + CASE_SET_SDRAM_PARAM(emc_tcke); + CASE_SET_SDRAM_PARAM(emc_tckesr); + CASE_SET_SDRAM_PARAM(emc_tpd); + CASE_SET_SDRAM_PARAM(emc_tfaw); + CASE_SET_SDRAM_PARAM(emc_trpab); + CASE_SET_SDRAM_PARAM(emc_tclkstable); + CASE_SET_SDRAM_PARAM(emc_tclkstop); + CASE_SET_SDRAM_PARAM(emc_trefbw); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_SET_SDRAM_PARAM(emc_fbio_spare); + CASE_SET_SDRAM_PARAM(emc_mrs); + CASE_SET_SDRAM_PARAM(emc_emrs); + CASE_SET_SDRAM_PARAM(emc_emrs2); + CASE_SET_SDRAM_PARAM(emc_emrs3); + CASE_SET_SDRAM_PARAM(emc_mrw1); + CASE_SET_SDRAM_PARAM(emc_mrw2); + CASE_SET_SDRAM_PARAM(emc_mrw3); + CASE_SET_SDRAM_PARAM(emc_mrw4); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_SET_SDRAM_PARAM(emc_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg2); + CASE_SET_SDRAM_PARAM(emc_cfg_pipe); + CASE_SET_SDRAM_PARAM(emc_dbg); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_SET_SDRAM_PARAM(warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_SET_SDRAM_PARAM(emc_odt_write); + CASE_SET_SDRAM_PARAM(emc_odt_read); + CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_SET_SDRAM_PARAM(emc_ddr2_wait); + CASE_SET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_SET_SDRAM_PARAM(emc_clock_source); + CASE_SET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_SET_SDRAM_PARAM(emc_timing_control_wait); + CASE_SET_SDRAM_PARAM(emc_wext); + CASE_SET_SDRAM_PARAM(emc_ctt); + CASE_SET_SDRAM_PARAM(emc_ctt_duration); + CASE_SET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_SET_SDRAM_PARAM(emc_txsr_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_rsv); + CASE_SET_SDRAM_PARAM(emc_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt2); + CASE_SET_SDRAM_PARAM(emc_cmd_q); + CASE_SET_SDRAM_PARAM(emc_mc2emc_q); + CASE_SET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_SET_SDRAM_PARAM(emc_dev_select); + CASE_SET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs8); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs9); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs10); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs11); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs12); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs13); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs14); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs15); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_addr5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse8); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse9); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse10); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse11); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse12); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse13); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse14); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse15); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs8); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs9); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs10); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs11); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs12); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs13); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs14); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs15); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq7); + CASE_SET_SDRAM_PARAM(emc_zcal_interval); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_SET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_cold_boot_enables); + CASE_SET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_clken_override); + CASE_SET_SDRAM_PARAM(mc_dis_extra_snap_levels); + CASE_SET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_SET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_SET_SDRAM_PARAM(pmc_vddp_sel); + CASE_SET_SDRAM_PARAM(pmc_vddp_sel_wait); + CASE_SET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_SET_SDRAM_PARAM(pmc_io_dpd3_req); + CASE_SET_SDRAM_PARAM(pmc_io_dpd3_req_wait); + CASE_SET_SDRAM_PARAM(pmc_reg_short); + CASE_SET_SDRAM_PARAM(pmc_no_io_power); + CASE_SET_SDRAM_PARAM(pmc_por_dpd_ctrl_wait); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl4); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl5); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl4); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl5); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl6); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_acpd_control); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte_cfg); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte0); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte1); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte2); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte3); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte_cfg); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte0); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte1); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte2); + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte3); + CASE_SET_SDRAM_PARAM(emc_dsr_vttgen_drv); + CASE_SET_SDRAM_PARAM(emc_txdsrvttgen); + CASE_SET_SDRAM_PARAM(emc_bgbias_ctl0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask1); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask2); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_swizzle3); + CASE_SET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_SET_SDRAM_PARAM(mc_emem_arb_override); + CASE_SET_SDRAM_PARAM(mc_emem_arb_override1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_SET_SDRAM_PARAM(mc_clken_override); + CASE_SET_SDRAM_PARAM(mc_stat_control); + CASE_SET_SDRAM_PARAM(mc_display_snap_ring); + CASE_SET_SDRAM_PARAM(mc_video_protect_bom); + CASE_SET_SDRAM_PARAM(mc_video_protect_bom_adr_hi); + CASE_SET_SDRAM_PARAM(mc_video_protect_size_mb); + CASE_SET_SDRAM_PARAM(mc_video_protect_vpr_override); + CASE_SET_SDRAM_PARAM(mc_video_protect_vpr_override1); + CASE_SET_SDRAM_PARAM(mc_video_protect_gpu_override0); + CASE_SET_SDRAM_PARAM(mc_video_protect_gpu_override1); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_bom); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_adr_hi); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_size_mb); + CASE_SET_SDRAM_PARAM(mc_video_protect_write_access); + CASE_SET_SDRAM_PARAM(mc_sec_carveout_protect_write_access); + CASE_SET_SDRAM_PARAM(emc_ca_training_enable); + CASE_SET_SDRAM_PARAM(emc_ca_training_timing_cntl1); + CASE_SET_SDRAM_PARAM(emc_ca_training_timing_cntl2); + CASE_SET_SDRAM_PARAM(swizzle_rank_byte_encode); + CASE_SET_SDRAM_PARAM(boot_rom_patch_control); + CASE_SET_SDRAM_PARAM(boot_rom_patch_data); + CASE_SET_SDRAM_PARAM(mc_mts_carveout_bom); + CASE_SET_SDRAM_PARAM(mc_mts_carveout_adr_hi); + CASE_SET_SDRAM_PARAM(mc_mts_carveout_size_mb); + CASE_SET_SDRAM_PARAM(mc_mts_carveout_reg_ctrl); + + DEFAULT(); + } + return 0; +} + +int +t132_getbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_GET_BL_PARAM(version); + CASE_GET_BL_PARAM(start_blk); + CASE_GET_BL_PARAM(start_page); + CASE_GET_BL_PARAM(length); + CASE_GET_BL_PARAM(load_addr); + CASE_GET_BL_PARAM(entry_point); + CASE_GET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(data, + &(bct_ptr->bootloader[set].signature.crypto_hash), + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t132_setbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_SET_BL_PARAM(version); + CASE_SET_BL_PARAM(start_blk); + CASE_SET_BL_PARAM(start_page); + CASE_SET_BL_PARAM(length); + CASE_SET_BL_PARAM(load_addr); + CASE_SET_BL_PARAM(entry_point); + CASE_SET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(&(bct_ptr->bootloader[set].signature.crypto_hash), + data, + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t132_bct_get_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + nvboot_config_table samplebct; /* Used for computing offsets. */ + + /* + * Note: Not all queries require use of the BCT, so testing for a + * valid BCT is distributed within the code. + */ + if (data == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_GET_NVU32(boot_data_version); + CASE_GET_NVU32(block_size_log2); + CASE_GET_NVU32(page_size_log2); + CASE_GET_NVU32(partition_size); + CASE_GET_NVU32(num_param_sets); + CASE_GET_NVU32(num_sdram_sets); + CASE_GET_NVU32(bootloader_used); + CASE_GET_NVU32(odm_data); + CASE_GET_NVU32(secure_jtag_control); + + case token_block_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->block_size_log2; + break; + + case token_page_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->page_size_log2; + break; + + case token_mts_used: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = bct_ptr->mts_boot_components_used; + break; + + /* + * Constants. + */ + + CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); + CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); + CASE_GET_CONST(mts_max, NVBOOT_MAX_MTS_COMPONENTS); + + case token_crypto_hash: + memcpy(data, + &(bct_ptr->signature.crypto_hash), + sizeof(nvboot_hash)); + break; + + case token_unique_chip_id: + memcpy(data, &(bct_ptr->unique_chip_id), sizeof(nvboot_ecid)); + break; + + case token_reserved_offset: + *((uint32_t *)data) = (uint8_t *)&(samplebct.reserved) + - (uint8_t *)&samplebct; + break; + + case token_bct_size: + *((uint32_t *)data) = sizeof(nvboot_config_table); + break; + + CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); + + case token_crypto_offset: + /* Offset to region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)&(samplebct.random_aes_blk) + - (uint8_t *)&samplebct; + break; + + case token_crypto_length: + /* size of region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)bct_ptr + sizeof(nvboot_config_table) + - (uint8_t *)&(bct_ptr->random_aes_blk); + break; + + CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); + + CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); + CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); + + CASE_GET_CONST_PREFIX(memory_type_none, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr3, nvboot); + + default: + return -ENODATA; + } + return 0; +} + +int +t132_bct_set_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_SET_NVU32(boot_data_version); + CASE_SET_NVU32(block_size_log2); + CASE_SET_NVU32(page_size_log2); + CASE_SET_NVU32(partition_size); + CASE_SET_NVU32(num_param_sets); + CASE_SET_NVU32(num_sdram_sets); + CASE_SET_NVU32(bootloader_used); + CASE_SET_NVU32(odm_data); + CASE_SET_NVU32(secure_jtag_control); + case token_unique_chip_id: + memcpy(&bct_ptr->unique_chip_id, data, sizeof(nvboot_ecid)); + break; + + case token_mts_used: + bct_ptr->mts_boot_components_used = *((uint32_t *)data); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t132_bct_set_data(parse_token id, + uint8_t *data, + uint32_t length, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + + case token_crypto_hash: + if (length < sizeof(nvboot_hash)) + return -ENODATA; + memcpy(&bct_ptr->signature.crypto_hash, data, sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int t132_get_bct_size() +{ + return sizeof(nvboot_config_table); +} + +int +t132_set_mts_info(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_mts_info *mts_info; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + mts_info = &(bct->mts_boot_components[index]); + + switch (token) { + CASE_SET_MTS_INFO(version); + CASE_SET_MTS_INFO(start_blk); + CASE_SET_MTS_INFO(start_page); + CASE_SET_MTS_INFO(length); + CASE_SET_MTS_INFO(load_addr); + CASE_SET_MTS_INFO(entry_point); + CASE_SET_MTS_INFO(attribute); + + DEFAULT(); + } + return 0; +} + +int +t132_get_mts_info(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_mts_info *mts_info; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + mts_info = &(bct->mts_boot_components[index]); + + switch (token) { + CASE_GET_MTS_INFO(version); + CASE_GET_MTS_INFO(start_blk); + CASE_GET_MTS_INFO(start_page); + CASE_GET_MTS_INFO(length); + CASE_GET_MTS_INFO(load_addr); + CASE_GET_MTS_INFO(entry_point); + CASE_GET_MTS_INFO(attribute); + + DEFAULT(); + } + return 0; +} + +int t132_bct_token_supported(parse_token token) +{ + int index; + + for (index = 0; index < ARRAY_SIZE(t132_root_token_list); index++) + if (t132_root_token_list[index] == token) + return 1; + + return 0; +} + +void t132_init_bad_block_table(build_image_context *context) +{ + uint32_t bytes_per_entry; + nvboot_badblock_table *table; + nvboot_config_table *bct; + + bct = (nvboot_config_table *)(context->bct); + + assert(context != NULL); + assert(bct != NULL); + + table = &bct->badblock_table; + + bytes_per_entry = ICEIL(context->partition_size, + NVBOOT_BAD_BLOCK_TABLE_SIZE); + table->block_size_log2 = context->block_size_log2; + table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), + table->block_size_log2); + table->entries_used = iceil_log2(context->partition_size, + table->virtual_blk_size_log2); +} + +cbootimage_soc_config tegra132_config = { + .init_bad_block_table = t132_init_bad_block_table, + .set_dev_param = t132_set_dev_param, + .get_dev_param = t132_get_dev_param, + .set_sdram_param = t132_set_sdram_param, + .get_sdram_param = t132_get_sdram_param, + .setbl_param = t132_setbl_param, + .getbl_param = t132_getbl_param, + .set_value = t132_bct_set_value, + .get_value = t132_bct_get_value, + .set_data = t132_bct_set_data, + .get_bct_size = t132_get_bct_size, + .set_mts_info = t132_set_mts_info, + .get_mts_info = t132_get_mts_info, + .token_supported = t132_bct_token_supported, + + .devtype_table = s_devtype_table_t132, + .sdmmc_data_width_table = s_sdmmc_data_width_table_t132, + .spi_clock_source_table = s_spi_clock_source_table_t132, + .nvboot_memory_type_table = s_nvboot_memory_type_table_t132, + .sdram_field_table = s_sdram_field_table_t132, + .nand_table = 0, + .sdmmc_table = s_sdmmc_table_t132, + .spiflash_table = s_spiflash_table_t132, + .device_type_table = s_device_type_table_t132, +}; + +void t132_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + context->boot_data_version = BOOTDATA_VERSION_T132; + *soc_config = &tegra132_config; +} + +int if_bct_is_t132_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + nvboot_config_table *bct = (nvboot_config_table *) context->bct; + + if (bct->boot_data_version == BOOTDATA_VERSION_T132) { + t132_get_soc_config(context, soc_config); + return 1; + } + return 0; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t132/nvboot_bct_t132.h b/firmware/coreboot/util/nvidia/cbootimage/src/t132/nvboot_bct_t132.h new file mode 100644 index 0000000000..7dc0bf2dba --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t132/nvboot_bct_t132.h @@ -0,0 +1,438 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#ifndef INCLUDED_NVBOOT_BCT_T132_H +#define INCLUDED_NVBOOT_BCT_T132_H + +#include +#include "nvboot_sdram_param_t132.h" + +/** + * Defines the number of 32-bit words in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_WORDS 162 + +/** + * Defines the number of bytes in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_SIZE \ + (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) + +/** + * Defines the number of bytes in the reserved area of the BCT. + */ +#define NVBOOT_BCT_RESERVED_SIZE 338 + +/** + * Defines the maximum number of bootloader descriptions in the BCT. + */ +#define NVBOOT_MAX_BOOTLOADERS 4 + +/** + * Defines the maximum number of device parameter sets in the BCT. + * The value must be equal to (1 << # of device straps) + */ +#define NVBOOT_BCT_MAX_PARAM_SETS 4 + +/** + * Defines the maximum number of SDRAM parameter sets in the BCT. + * The value must be equal to (1 << # of SDRAM straps) + */ +#define NVBOOT_BCT_MAX_SDRAM_SETS 4 + +/** + * Defines the number of entries (bits) in the bad block table. + * The consequences of changing its value are as follows. Using P as the + * # of physical blocks in the boot loader and B as the value of this + * constant: + * B > P: There will be unused storage in the bad block table. + * B < P: The virtual block size will be greater than the physical block + * size, so the granularity of the bad block table will be less than + * one bit per physical block. + * + * 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one + * bit per block (1 virtual block = 1 physical block). This occupies 512 bytes + * of storage. + */ +#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096 + +/** + * Defines the amount of padding needed to pad the bad block table to a + * multiple of AES block size. + */ +#define NVBOOT_BAD_BLOCK_TABLE_PADDING 10 + +/** + * Defines the maximum number of blocks to search for BCTs. + * + * This value covers the initial block and a set of journal blocks. + * + * Ideally, this number will span several erase units for reliable updates + * and tolerance for blocks to become bad with use. Safe updates require + * a minimum of 2 erase units in which BCTs can appear. + * + * To ensure that the BCT search spans a sufficient range of configurations, + * the search block count has been set to 64. This allows for redundancy with + * a wide range of parts and provides room for greater problems in this + * region of the device. + */ +#define NVBOOT_MAX_BCT_SEARCH_BLOCKS 64 + +/** + * Defines the maximum number of MTS boot components descriptions in the BCT. + */ +#define NVBOOT_MAX_MTS_COMPONENTS 6 + +#define ARSE_RSA_MAX_MODULUS_SIZE 2048 + +/** + * Defines the RSA modulus length in bits and bytes used for PKC secure boot. + */ +enum {NVBOOT_SE_RSA_MODULUS_LENGTH_BITS = ARSE_RSA_MAX_MODULUS_SIZE}; + +/* + * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) + */ +enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; + +/** + * Defines the storage for a hash value (128 bits). + */ +typedef struct nvboot_hash_rec { + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; +} nvboot_hash; + +/* + * Defines the storage for the RSA public key's modulus + * in the BCT + */ +typedef struct nvboot_rsa_key_modulus_rec { + /* The modulus size is 2048-bits. */ + uint32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; +} nvboot_rsa_key_modulus; + +typedef struct nvboot_rsa_pss_sig_rec { + /* + * The RSA-PSS signature length is equal to the + * length in octets of the RSA modulus. + * In our case, it's 2048-bits. + */ + uint32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; +} nvboot_rsa_pss_sig; + +typedef struct nvboot_object_signature_rec { + /* + * Specifies the AES-CMAC signature for the rest of the BCT structure if symmetric key + * encryption secure boot scheme is used. + */ + nvboot_hash crypto_hash; + + /* + * Specifies the RSASSA-PSS signature for the rest of the BCT structure if public + * key cryptography secure boot scheme is used. + */ + nvboot_rsa_pss_sig rsa_pss_sig; +} nvboot_object_signature; + +typedef struct nvboot_ecid_rec { + uint32_t ecid_0; + uint32_t ecid_1; + uint32_t ecid_2; + uint32_t ecid_3; +} nvboot_ecid; + +/* Defines various data widths supported. */ +typedef enum { + /** + * Specifies a 1 bit interface to eMMC. + * Note that 1-bit data width is only for the driver's internal use. + * Fuses doesn't provide option to select 1-bit data width. + * The driver selects 1-bit internally based on need. + * It is used for reading Extended CSD and when the power class + * requirements of a card for 4-bit or 8-bit transfers are not + * supported by the target board. + */ + nvboot_sdmmc_data_width_1bit = 0, + + /* Specifies a 4 bit interface to eMMC. */ + nvboot_sdmmc_data_width_4bit = 1, + + /* Specifies a 8 bit interface to eMMC. */ + nvboot_sdmmc_data_width_8bit = 2, + /* Specifies a 4 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_4bit = 5, + /* Specifies a 8 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_8bit = 6, + + nvboot_sdmmc_data_width_num, + nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF +} nvboot_sdmmc_data_width; + +/* Defines the parameters that can be changed after BCT is read. */ +typedef struct nvboot_sdmmc_params_rec { + /** + * Specifies the clock divider for the SDMMC controller's clock source, + * which is PLLP running at 216MHz. If it is set to 9, then the SDMMC + * controller runs at 216/9 = 24MHz. + */ + uint8_t clock_divider; + + /* Specifies the data bus width. Supported data widths are 4/8 bits. */ + nvboot_sdmmc_data_width data_width; + + /** + * Max Power class supported by the target board. + * The driver determines the best data width and clock frequency + * supported within the power class range (0 to Max) if the selected + * data width cannot be used at the chosen clock frequency. + */ + uint8_t max_power_class_supported; + + /* Specifies the max page size supported by driver */ + uint8_t multi_page_support; +} nvboot_sdmmc_params; + +typedef enum { + /* Specifies SPI clock source to be PLLP. */ + nvboot_spi_clock_source_pllp_out0 = 0, + + /* Specifies SPI clock source to be ClockM. */ + nvboot_spi_clock_source_clockm = 6, + + nvboot_spi_clock_source_num, + nvboot_spi_clock_source_force32 = 0x7FFFFFF +} nvboot_spi_clock_source; + +/** + * Defines the parameters SPI FLASH devices. + */ +typedef struct nvboot_spiflash_params_rec { + /** + * Specifies the clock source to use. + */ + uint32_t clock_source; + + /** + * Specifes the clock divider to use. + * The value is a 7-bit value based on an input clock of 432Mhz. + * Divider = (432+ DesiredFrequency-1)/DesiredFrequency; + * Typical values: + * NORMAL_READ at 20MHz: 22 + * FAST_READ at 33MHz: 14 + * FAST_READ at 40MHz: 11 + * FAST_READ at 50MHz: 9 + */ + uint8_t clock_divider; + + /** + * Specifies the type of command for read operations. + * NV_FALSE specifies a NORMAL_READ Command + * NV_TRUE specifies a FAST_READ Command + */ + uint8_t read_command_type_fast; + + /* 0 = 2k page size, 1 = 16K page size */ + uint8_t page_size_2k_or_16k; +} nvboot_spiflash_params; + +/** +* Defines the union of the parameters required by each device. +*/ +typedef union { + uint8_t size[64]; + /* Specifies optimized parameters for eMMC and eSD */ + nvboot_sdmmc_params sdmmc_params; + /* Specifies optimized parameters for SPI NOR */ + nvboot_spiflash_params spiflash_params; +} nvboot_dev_params; + +/** + * Identifies the types of devices from which the system booted. + * Used to identify primary and secondary boot devices. + * @note These no longer match the fuse API device values (for + * backward compatibility with AP15). + */ +typedef enum { + /* Specifies a default (unset) value. */ + nvboot_dev_type_none = 0, + + /* Specifies SPI NOR. */ + nvboot_dev_type_spi = 3, + + /* Specifies SDMMC (either eMMC or eSD). */ + nvboot_dev_type_sdmmc = 4, + + nvboot_dev_type_max, + + /* Ignore -- Forces compilers to make 32-bit enums. */ + nvboot_dev_type_force32 = 0x7FFFFFFF +} nvboot_dev_type; + +/** + * Stores information needed to locate MTS image on the boot media. + * + * There is one MTS boot structure for each of the Preboot, Bootcode and + * the package image. + */ +typedef struct nvboot_mts_info_rec +{ + /* + * Specifies a version number for the MTS image. The assignment of + * numbers is arbitrary; the numbers are only used to identify redundant. + */ + uint32_t version; + + /* + * Specifies the first physical block on the secondary boot device + * that contains the start of the MTS image. The first block can never be + * a known bad block. + */ + uint32_t start_blk; + + /* + * Specifies the page within the first block that contains the start + * of the MTS image. + */ + uint32_t start_page; + + /* + * Specifies the length of the MTS image in bytes. MTS image must be + * padded to an integral number of 16 bytes with the padding pattern. + * @note The end of the MTS image cannot fall within the last 16 bytes of + * a page. Add another 16 bytes to work around this restriction if + * needed. + */ + uint32_t length; + + /* + * Specifies the starting address of the memory region into which the + * MTS will be loaded. This is optional. + */ + uint32_t load_addr; + + /* Specifies the entry point address in the loaded MTS image. Optional */ + uint32_t entry_point; + + /* + * Specifies an attribute available for use by other code. + * Not interpreted by the Boot ROM. + */ + uint32_t attribute; + +} nvboot_mts_info; + +/** + * Stores information needed to locate and verify a boot loader. + * + * There is one \c nv_bootloader_info structure for each copy of a BL stored on + * the device. + */ +typedef struct nv_bootloader_info_rec { + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; + + /* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */ + nvboot_object_signature signature; +} nv_bootloader_info; + +/** + * Defines the bad block table structure stored in the BCT. + */ +typedef struct nvboot_badblock_table_rec { + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; + /* + * Add a reserved field as padding to make the bad block table structure + * a multiple of 16 bytes (AES block size). + */ + uint8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; +} nvboot_badblock_table; + +/** + * Contains the information needed to load BLs from the secondary boot device. + * + * - Supplying NumParamSets = 0 indicates not to load any of them. + * - Supplying NumDramSets = 0 indicates not to load any of them. + * - The \c random_aes_blk member exists to increase the difficulty of + * key attacks based on knowledge of this structure. + */ +typedef struct nvboot_config_table_rec { + nvboot_badblock_table badblock_table; + nvboot_rsa_key_modulus key; + nvboot_object_signature signature; + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + uint32_t odm_data; + uint32_t reserved1; + + /* START OF SIGNED SECTION OF THE BCT */ + nvboot_hash random_aes_blk; + nvboot_ecid unique_chip_id; + uint32_t boot_data_version; + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; + nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; + nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; + uint32_t num_sdram_sets; + nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; + + uint32_t bootloader_used; + nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; + + /* + * Specify the number of Mts boot components described in the mts boot + * table. + */ + uint32_t mts_boot_components_used; + + /* + * Specify the information needed to locate and validate Denver Boot. + * components. The BR interprets entries 0/1 for preboot, 2/3 + * for MTS bootcode and 4/5 for MTS package. + */ + nvboot_mts_info mts_boot_components[NVBOOT_MAX_MTS_COMPONENTS]; + + uint8_t enable_fail_back; + + /* + * Specify whether or not to enable JTAG access when the JTAG disable fuse + * has not been burned. + * secure_jtag_control = NV_FALSE (0) = Disable JTAG access. + * secure_jtag_control = NV_TRUE (1) = Enable JTAG access. + */ + uint8_t secure_jtag_control; + + /* + * Specify whether or not to enable denver dfd access + * cust_denver_dfd_en = NV_FALSE (0) = Disable Dfd access. + * cust_denver_dfd_en = NV_TRUE (1) = Enable Dfd access. + */ + uint8_t cust_denver_dfd_en; + + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; +} nvboot_config_table; +#endif /* #ifndef INCLUDED_NVBOOT_BCT_T132_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t132/nvboot_sdram_param_t132.h b/firmware/coreboot/util/nvidia/cbootimage/src/t132/nvboot_sdram_param_t132.h new file mode 100644 index 0000000000..166764a2fe --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t132/nvboot_sdram_param_t132.h @@ -0,0 +1,802 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T132_H +#define INCLUDED_NVBOOT_SDRAM_PARAM_T132_H + +#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 + +typedef enum { + /* Specifies the memory type to be undefined */ + nvboot_memory_type_none = 0, + + /* Specifies the memory type to be DDR SDRAM */ + nvboot_memory_type_ddr = 0, + + /* Specifies the memory type to be LPDDR SDRAM */ + nvboot_memory_type_lpddr = 0, + + /* Specifies the memory type to be DDR2 SDRAM */ + nvboot_memory_type_ddr2 = 0, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + nvboot_memory_type_lpddr2, + + /* Specifies the memory type to be DDR3 SDRAM */ + nvboot_memory_type_ddr3, + + nvboot_memory_type_num, + nvboot_memory_type_force32 = 0x7FFFFFF +} nvboot_memory_type; + +/** + * Defines the SDRAM parameter structure + */ +typedef struct nvboot_sdram_params_rec { + /* sdram data structure generated by tool warmboot_code_gen */ + + /* Specifies the type of memory device */ + nvboot_memory_type memory_type; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t pllm_input_divider; + /* Specifies the N value for PllM */ + uint32_t pllm_feedback_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t pllm_stable_time; + /* Specifies misc. control bits */ + uint32_t pllm_setup_control; + /* Enables the Div by 2 */ + uint32_t pllm_select_div2; + /* Powers down VCO output Level shifter */ + uint32_t pllm_pdlshift_ph45; + /* Powers down VCO output Level shifter */ + uint32_t pllm_pdlshift_ph90; + /* Powers down VCO output Level shifter */ + uint32_t pllm_pdlshift_ph135; + /* Specifies value for Charge Pump Gain Control */ + uint32_t pllm_kcp; + /* Specifies VCO gain */ + uint32_t pllm_kvco; + /* Spare BCT param */ + uint32_t emc_bct_spare0; + /* Spare BCT param */ + uint32_t emc_bct_spare1; + /* Spare BCT param */ + uint32_t emc_bct_spare2; + /* Spare BCT param */ + uint32_t emc_bct_spare3; + /* Spare BCT param */ + uint32_t emc_bct_spare4; + /* Spare BCT param */ + uint32_t emc_bct_spare5; + /* Spare BCT param */ + uint32_t emc_bct_spare6; + /* Spare BCT param */ + uint32_t emc_bct_spare7; + /* Spare BCT param */ + uint32_t emc_bct_spare8; + /* Spare BCT param */ + uint32_t emc_bct_spare9; + /* Spare BCT param */ + uint32_t emc_bct_spare10; + /* Spare BCT param */ + uint32_t emc_bct_spare11; + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t emc_clock_source; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t emc_auto_cal_interval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t emc_auto_cal_config; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t emc_auto_cal_config2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t emc_auto_cal_config3; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t emc_auto_cal_wait; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t emc_adr_cfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t emc_pin_program_wait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t emc_pin_extra_wait; + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t emc_timing_control_wait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t emc_rc; + /* Specifies the value for EMC_RFC */ + uint32_t emc_rfc; + /* Specifies the value for EMC_RFC_SLR */ + uint32_t emc_rfc_slr; + /* Specifies the value for EMC_RAS */ + uint32_t emc_ras; + /* Specifies the value for EMC_RP */ + uint32_t emc_rp; + /* Specifies the value for EMC_R2R */ + uint32_t emc_r2r; + /* Specifies the value for EMC_W2W */ + uint32_t emc_w2w; + /* Specifies the value for EMC_R2W */ + uint32_t emc_r2w; + /* Specifies the value for EMC_W2R */ + uint32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + uint32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + uint32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + uint32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + uint32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + uint32_t emc_rext; + /* Specifies the value for EMC_WEXT */ + uint32_t emc_wext; + /* Specifies the value for EMC_WDV */ + uint32_t emc_wdv; + /* Specifies the value for EMC_WDV_MASK */ + uint32_t emc_wdv_mask; + /* Specifies the value for EMC_QUSE */ + uint32_t emc_quse; + /* Specifies the value for EMC_QUSE_WIDTH */ + uint32_t emc_quse_width; + /* Specifies the value for EMC_IBDLY */ + uint32_t emc_ibdly; + /* Specifies the value for EMC_EINPUT */ + uint32_t emc_einput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t emc_einput_duration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t emc_puterm_extra; + /* Specifies the value for EMC_PUTERM_WIDTH */ + uint32_t emc_puterm_width; + /* Specifies the value for EMC_PUTERM_ADJ */ + uint32_t emc_puterm_adj; + /* Specifies the value for EMC_CDB_CNTL_1 */ + uint32_t emc_cdb_cntl1; + /* Specifies the value for EMC_CDB_CNTL_2 */ + uint32_t emc_cdb_cntl2; + /* Specifies the value for EMC_CDB_CNTL_3 */ + uint32_t emc_cdb_cntl3; + /* Specifies the value for EMC_QRST */ + uint32_t emc_qrst; + /* Specifies the value for EMC_QSAFE */ + uint32_t emc_qsafe; + /* Specifies the value for EMC_RDV */ + uint32_t emc_rdv; + /* Specifies the value for EMC_RDV_MASK */ + uint32_t emc_rdv_mask; + /* Specifies the value for EMC_QPOP */ + uint32_t emc_qpop; + /* Specifies the value for EMC_CTT */ + uint32_t emc_ctt; + /* Specifies the value for EMC_CTT_DURATION */ + uint32_t emc_ctt_duration; + /* Specifies the value for EMC_REFRESH */ + uint32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t emc_prerefresh_req_cnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t emc_rw2pden; + /* Specifies the value for EMC_TXSR */ + uint32_t emc_txsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t emc_txsr_dll; + /* Specifies the value for EMC_TCKE */ + uint32_t emc_tcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t emc_tckesr; + /* Specifies the value for EMC_TPD */ + uint32_t emc_tpd; + /* Specifies the value for EMC_TFAW */ + uint32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + uint32_t emc_trefbw; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + uint32_t emc_fbio_cfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t emc_fbio_spare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t emc_cfg_rsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t emc_mrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t emc_emrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t emc_emrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t emc_emrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t emc_mrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t emc_mrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t emc_mrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t emc_mrw4; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t emc_mrw_extra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t emc_warm_boot_mrw_extra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t emc_warm_boot_extramode_reg_write_enable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t emc_extramode_reg_write_enable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t emc_mrw_reset_ninit_wait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t emc_mrs_wait_cnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t emc_mrs_wait_cnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t emc_cfg2; + /* Specifies the pipe bypass controls */ + uint32_t emc_cfg_pipe; + /* Specifies the value for EMC_DBG */ + uint32_t emc_dbg; + /* Specifies the value for EMC_CMDQ */ + uint32_t emc_cmd_q; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t emc_mc2emc_q; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t emc_dyn_self_ref_control; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t ahb_arbitration_xbar_ctrl_meminit_done; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t emc_cfg_dig_dll; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t emc_cfg_dig_dll_period; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t emc_dev_select; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t emc_sel_dpd_ctrl; + + /* Pads trimmer delays */ + + /* Specifies the value for EMC_DLL_XFORM_DQS0 */ + uint32_t emc_dll_xform_dqs0; + /* Specifies the value for EMC_DLL_XFORM_DQS1 */ + uint32_t emc_dll_xform_dqs1; + /* Specifies the value for EMC_DLL_XFORM_DQS2 */ + uint32_t emc_dll_xform_dqs2; + /* Specifies the value for EMC_DLL_XFORM_DQS3 */ + uint32_t emc_dll_xform_dqs3; + /* Specifies the value for EMC_DLL_XFORM_DQS4 */ + uint32_t emc_dll_xform_dqs4; + /* Specifies the value for EMC_DLL_XFORM_DQS5 */ + uint32_t emc_dll_xform_dqs5; + /* Specifies the value for EMC_DLL_XFORM_DQS6 */ + uint32_t emc_dll_xform_dqs6; + /* Specifies the value for EMC_DLL_XFORM_DQS7 */ + uint32_t emc_dll_xform_dqs7; + /* Specifies the value for EMC_DLL_XFORM_DQS8 */ + uint32_t emc_dll_xform_dqs8; + /* Specifies the value for EMC_DLL_XFORM_DQS9 */ + uint32_t emc_dll_xform_dqs9; + /* Specifies the value for EMC_DLL_XFORM_DQS10 */ + uint32_t emc_dll_xform_dqs10; + /* Specifies the value for EMC_DLL_XFORM_DQS11 */ + uint32_t emc_dll_xform_dqs11; + /* Specifies the value for EMC_DLL_XFORM_DQS12 */ + uint32_t emc_dll_xform_dqs12; + /* Specifies the value for EMC_DLL_XFORM_DQS13 */ + uint32_t emc_dll_xform_dqs13; + /* Specifies the value for EMC_DLL_XFORM_DQS14 */ + uint32_t emc_dll_xform_dqs14; + /* Specifies the value for EMC_DLL_XFORM_DQS15 */ + uint32_t emc_dll_xform_dqs15; + /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ + uint32_t emc_dll_xform_quse0; + /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ + uint32_t emc_dll_xform_quse1; + /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ + uint32_t emc_dll_xform_quse2; + /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ + uint32_t emc_dll_xform_quse3; + /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ + uint32_t emc_dll_xform_quse4; + /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ + uint32_t emc_dll_xform_quse5; + /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ + uint32_t emc_dll_xform_quse6; + /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ + uint32_t emc_dll_xform_quse7; + /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ + uint32_t emc_dll_xform_addr0; + /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ + uint32_t emc_dll_xform_addr1; + /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ + uint32_t emc_dll_xform_addr2; + /* Specifies the value for EMC_DLL_XFORM_ADDR3 */ + uint32_t emc_dll_xform_addr3; + /* Specifies the value for EMC_DLL_XFORM_ADDR4 */ + uint32_t emc_dll_xform_addr4; + /* Specifies the value for EMC_DLL_XFORM_ADDR5 */ + uint32_t emc_dll_xform_addr5; + /* Specifies the value for EMC_DLL_XFORM_QUSE8 */ + uint32_t emc_dll_xform_quse8; + /* Specifies the value for EMC_DLL_XFORM_QUSE9 */ + uint32_t emc_dll_xform_quse9; + /* Specifies the value for EMC_DLL_XFORM_QUSE10 */ + uint32_t emc_dll_xform_quse10; + /* Specifies the value for EMC_DLL_XFORM_QUSE11 */ + uint32_t emc_dll_xform_quse11; + /* Specifies the value for EMC_DLL_XFORM_QUSE12 */ + uint32_t emc_dll_xform_quse12; + /* Specifies the value for EMC_DLL_XFORM_QUSE13 */ + uint32_t emc_dll_xform_quse13; + /* Specifies the value for EMC_DLL_XFORM_QUSE14 */ + uint32_t emc_dll_xform_quse14; + /* Specifies the value for EMC_DLL_XFORM_QUSE15 */ + uint32_t emc_dll_xform_quse15; + /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ + uint32_t emc_dli_trim_tx_dqs0; + /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ + uint32_t emc_dli_trim_tx_dqs1; + /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ + uint32_t emc_dli_trim_tx_dqs2; + /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ + uint32_t emc_dli_trim_tx_dqs3; + /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ + uint32_t emc_dli_trim_tx_dqs4; + /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ + uint32_t emc_dli_trim_tx_dqs5; + /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ + uint32_t emc_dli_trim_tx_dqs6; + /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ + uint32_t emc_dli_trim_tx_dqs7; + /* Specifies the value for EMC_DLI_TRIM_TXDQS8 */ + uint32_t emc_dli_trim_tx_dqs8; + /* Specifies the value for EMC_DLI_TRIM_TXDQS9 */ + uint32_t emc_dli_trim_tx_dqs9; + /* Specifies the value for EMC_DLI_TRIM_TXDQS10 */ + uint32_t emc_dli_trim_tx_dqs10; + /* Specifies the value for EMC_DLI_TRIM_TXDQS11 */ + uint32_t emc_dli_trim_tx_dqs11; + /* Specifies the value for EMC_DLI_TRIM_TXDQS12 */ + uint32_t emc_dli_trim_tx_dqs12; + /* Specifies the value for EMC_DLI_TRIM_TXDQS13 */ + uint32_t emc_dli_trim_tx_dqs13; + /* Specifies the value for EMC_DLI_TRIM_TXDQS14 */ + uint32_t emc_dli_trim_tx_dqs14; + /* Specifies the value for EMC_DLI_TRIM_TXDQS15 */ + uint32_t emc_dli_trim_tx_dqs15; + /* Specifies the value for EMC_DLL_XFORM_DQ0 */ + uint32_t emc_dll_xform_dq0; + /* Specifies the value for EMC_DLL_XFORM_DQ1 */ + uint32_t emc_dll_xform_dq1; + /* Specifies the value for EMC_DLL_XFORM_DQ2 */ + uint32_t emc_dll_xform_dq2; + /* Specifies the value for EMC_DLL_XFORM_DQ3 */ + uint32_t emc_dll_xform_dq3; + /* Specifies the value for EMC_DLL_XFORM_DQ4 */ + uint32_t emc_dll_xform_dq4; + /* Specifies the value for EMC_DLL_XFORM_DQ5 */ + uint32_t emc_dll_xform_dq5; + /* Specifies the value for EMC_DLL_XFORM_DQ6 */ + uint32_t emc_dll_xform_dq6; + /* Specifies the value for EMC_DLL_XFORM_DQ7 */ + uint32_t emc_dll_xform_dq7; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t warm_boot_wait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + uint32_t emc_ctt_term_ctrl; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_write; + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_read; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t emc_zcal_interval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t emc_zcal_wait_cnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t emc_zcal_mrw_cmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t emc_mrs_reset_dll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t emc_zcal_init_dev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t emc_zcal_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t emc_zcal_init_wait; + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + uint32_t emc_zcal_warm_cold_boot_enables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t emc_mrw_lpddr2zcal_warm_boot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t emc_zqcal_ddr3_warm_boot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t emc_zcal_warm_boot_wait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t emc_mrs_warm_boot_enable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t emc_mrs_reset_dll_wait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t emc_mrs_extra; + /* Specifies the extra MRS command at warm boot */ + uint32_t emc_warm_boot_mrs_extra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t emc_ddr2_wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t emc_clken_override; + /* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */ + uint32_t mc_dis_extra_snap_levels; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t emc_extra_refresh_num; + /* Specifies the master override for all EMC clocks */ + uint32_t emc_clken_override_allwarm_boot; + /* Specifies the master override for all MC clocks */ + uint32_t mc_clken_override_allwarm_boot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t emc_cfg_dig_dll_period_warm_boot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel; + /* Specifies the wait time after programming PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel_wait; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t pmc_ddr_pwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t pmc_ddr_cfg; + /* Specifies the value for PMC_IO_DPD3_REQ */ + uint32_t pmc_io_dpd3_req; + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + uint32_t pmc_io_dpd3_req_wait; + /* Specifies the value for PMC_REG_SHORT */ + uint32_t pmc_reg_short; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t pmc_no_io_power; + /* Specifies the wait time after programming PMC_POR_DPD_CTRL */ + uint32_t pmc_por_dpd_ctrl_wait; + /* Specifies the value for EMC_XM2CMDPADCTRL */ + uint32_t emc_xm2cmd_pad_ctrl; + /* Specifies the value for EMC_XM2CMDPADCTRL2 */ + uint32_t emc_xm2cmd_pad_ctrl2; + /* Specifies the value for EMC_XM2CMDPADCTRL3 */ + uint32_t emc_xm2cmd_pad_ctrl3; + /* Specifies the value for EMC_XM2CMDPADCTRL4 */ + uint32_t emc_xm2cmd_pad_ctrl4; + /* Specifies the value for EMC_XM2CMDPADCTRL5 */ + uint32_t emc_xm2cmd_pad_ctrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL */ + uint32_t emc_xm2dqs_pad_ctrl; + /* Specifies the value for EMC_XM2DQSPADCTRL2 */ + uint32_t emc_xm2dqs_pad_ctrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL3 */ + uint32_t emc_xm2dqs_pad_ctrl3; + /* Specifies the value for EMC_XM2DQSPADCTRL4 */ + uint32_t emc_xm2dqs_pad_ctrl4; + /* Specifies the value for EMC_XM2DQSPADCTRL5 */ + uint32_t emc_xm2dqs_pad_ctrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL6 */ + uint32_t emc_xm2dqs_pad_ctrl6; + /* Specifies the value for EMC_XM2DQPADCTRL */ + uint32_t emc_xm2dq_pad_ctrl; + /* Specifies the value for EMC_XM2DQPADCTRL2 */ + uint32_t emc_xm2dq_pad_ctrl2; + /* Specifies the value for EMC_XM2DQPADCTRL3 */ + uint32_t emc_xm2dq_pad_ctrl3; + /* Specifies the value for EMC_XM2CLKPADCTRL */ + uint32_t emc_xm2clk_pad_ctrl; + /* Specifies the value for EMC_XM2CLKPADCTRL2 */ + uint32_t emc_xm2clk_pad_ctrl2; + /* Specifies the value for EMC_XM2COMPPADCTRL */ + uint32_t emc_xm2comp_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL */ + uint32_t emc_xm2vttgen_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ + uint32_t emc_xm2vttgen_pad_ctrl2; + /* Specifies the value for EMC_XM2VTTGENPADCTRL3 */ + uint32_t emc_xm2vttgen_pad_ctrl3; + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t emc_acpd_control; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ + uint32_t emc_swizzle_rank0_byte_cfg; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t emc_swizzle_rank0_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t emc_swizzle_rank0_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t emc_swizzle_rank0_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t emc_swizzle_rank0_byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ + uint32_t emc_swizzle_rank1_byte_cfg; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t emc_swizzle_rank1_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t emc_swizzle_rank1_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t emc_swizzle_rank1_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t emc_swizzle_rank1_byte3; + + /* Specifies the value for EMC_DSR_VTTGEN_DRV */ + uint32_t emc_dsr_vttgen_drv; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t emc_txdsrvttgen; + /* Specifies the value for EMC_BGBIAS_CTL */ + uint32_t emc_bgbias_ctl0; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t mc_emem_adr_cfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t mc_emem_adr_cfg_dev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t mc_emem_adr_cfg_dev1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ + uint32_t mc_emem_adr_cfg_bank_mask0; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + uint32_t mc_emem_adr_cfg_bank_mask1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + uint32_t mc_emem_adr_cfg_bank_mask2; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */ + uint32_t mc_emem_adr_cfg_bank_swizzle3; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t mc_emem_cfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t mc_emem_arb_cfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t mc_emem_arb_outstanding_req; + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t mc_emem_arb_timing_rcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t mc_emem_arb_timing_rp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t mc_emem_arb_timing_rc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t mc_emem_arb_timing_ras; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t mc_emem_arb_timing_faw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t mc_emem_arb_timing_rrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t mc_emem_arb_timing_rap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t mc_emem_arb_timing_wap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t mc_emem_arb_timing_r2r; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t mc_emem_arb_timing_w2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t mc_emem_arb_timing_r2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t mc_emem_arb_timing_w2r; + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t mc_emem_arb_da_turns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t mc_emem_arb_da_covers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t mc_emem_arb_misc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t mc_emem_arb_misc1; + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t mc_emem_arb_ring1_throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t mc_emem_arb_override; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + uint32_t mc_emem_arb_override1; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t mc_emem_arb_rsv; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t mc_clken_override; + + /* Specifies the value for MC_STAT_CONTROL */ + uint32_t mc_stat_control; + /* Specifies the value for MC_DISPLAY_SNAP_RING */ + uint32_t mc_display_snap_ring; + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t mc_video_protect_bom; + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + uint32_t mc_video_protect_bom_adr_hi; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t mc_video_protect_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t mc_video_protect_vpr_override; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + uint32_t mc_video_protect_vpr_override1; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + uint32_t mc_video_protect_gpu_override0; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + uint32_t mc_video_protect_gpu_override1; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t mc_sec_carveout_bom; + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + uint32_t mc_sec_carveout_adr_hi; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t mc_sec_carveout_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ + uint32_t mc_video_protect_write_access; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ + uint32_t mc_sec_carveout_protect_write_access; + + /* Specifies enable for CA training */ + uint32_t emc_ca_training_enable; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ + uint32_t emc_ca_training_timing_cntl1; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ + uint32_t emc_ca_training_timing_cntl2; + /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t swizzle_rank_byte_encode; + /* Specifies enable and offset for patched boot rom write */ + uint32_t boot_rom_patch_control; + /* Specifies data for patched boot rom write */ + uint32_t boot_rom_patch_data; + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + uint32_t mc_mts_carveout_bom; + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + uint32_t mc_mts_carveout_adr_hi; + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + uint32_t mc_mts_carveout_size_mb; + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + uint32_t mc_mts_carveout_reg_ctrl; + + /* End of generated code by warmboot_code_gen */ +} nvboot_sdram_params; +#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T132_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t132/parse_t132.c b/firmware/coreboot/util/nvidia/cbootimage/src/t132/parse_t132.c new file mode 100644 index 0000000000..906a88b72c --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t132/parse_t132.c @@ -0,0 +1,429 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * parse_t132.c - The implementation for parsing dev/sdram parameters + */ + +#include "../parse.h" +#include "nvboot_bct_t132.h" + +enum_item s_devtype_table_t132[] = { + { "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc }, + { "NvBootDevType_Spi", nvboot_dev_type_spi }, + { "Sdmmc", nvboot_dev_type_sdmmc }, + { "Spi", nvboot_dev_type_spi }, + { NULL, 0 } +}; + +enum_item s_sdmmc_data_width_table_t132[] = { + { + "NvBootSdmmcDataWidth_4Bit", + nvboot_sdmmc_data_width_4bit + }, + { + "NvBootSdmmcDataWidth_8Bit", + nvboot_sdmmc_data_width_8bit + }, + { "4Bit", nvboot_sdmmc_data_width_4bit }, + { "8Bit", nvboot_sdmmc_data_width_8bit }, + { NULL, 0 } +}; + +enum_item s_spi_clock_source_table_t132[] = { + { "NvBootSpiClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "NvBootSpiClockSource_ClockM", nvboot_spi_clock_source_clockm }, + { "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockSource_ClockM", nvboot_spi_clock_source_clockm }, + { "PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockM", nvboot_spi_clock_source_clockm }, + { NULL, 0 } +}; + +enum_item s_nvboot_memory_type_table_t132[] = { + { "NvBootMemoryType_None", nvboot_memory_type_none }, + { "NvBootMemoryType_Ddr3", nvboot_memory_type_ddr3 }, + { "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 }, + { "NvBootMemoryType_Ddr", nvboot_memory_type_ddr }, + { "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 }, + { "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr }, + + { "None", nvboot_memory_type_none }, + { "Ddr3", nvboot_memory_type_ddr3 }, + { "Ddr2", nvboot_memory_type_ddr2 }, + { "Ddr", nvboot_memory_type_ddr }, + { "LpDdr2", nvboot_memory_type_lpddr2 }, + { "LpDdr", nvboot_memory_type_lpddr }, + + { NULL, 0 } +}; + +#define TOKEN(name) \ + token_##name, field_type_u32, NULL + +field_item s_sdram_field_table_t132[] = { + { "MemoryType", token_memory_type, + field_type_enum, s_nvboot_memory_type_table_t132 }, + + { "PllMInputDivider", TOKEN(pllm_input_divider) }, + { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, + { "PllMStableTime", TOKEN(pllm_stable_time) }, + { "PllMSetupControl", TOKEN(pllm_setup_control) }, + { "PllMSelectDiv2", TOKEN(pllm_select_div2) }, + { "PllMPDLshiftPh45", TOKEN(pllm_pdlshift_ph45) }, + { "PllMPDLshiftPh90", TOKEN(pllm_pdlshift_ph90) }, + { "PllMPDLshiftPh135", TOKEN(pllm_pdlshift_ph135) }, + { "PllMKCP", TOKEN(pllm_kcp) }, + { "PllMKVCO", TOKEN(pllm_kvco) }, + { "EmcBctSpare0", TOKEN(emc_bct_spare0) }, + { "EmcBctSpare1", TOKEN(emc_bct_spare1) }, + { "EmcBctSpare2", TOKEN(emc_bct_spare2) }, + { "EmcBctSpare3", TOKEN(emc_bct_spare3) }, + { "EmcBctSpare4", TOKEN(emc_bct_spare4) }, + { "EmcBctSpare5", TOKEN(emc_bct_spare5) }, + { "EmcBctSpare6", TOKEN(emc_bct_spare6) }, + { "EmcBctSpare7", TOKEN(emc_bct_spare7) }, + { "EmcBctSpare8", TOKEN(emc_bct_spare8) }, + { "EmcBctSpare9", TOKEN(emc_bct_spare9) }, + { "EmcBctSpare10", TOKEN(emc_bct_spare10) }, + { "EmcBctSpare11", TOKEN(emc_bct_spare11) }, + { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, + { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, + { "EmcAutoCalConfig2", TOKEN(emc_auto_cal_config2) }, + { "EmcAutoCalConfig3", TOKEN(emc_auto_cal_config3) }, + { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, + { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, + { "EmcRc", TOKEN(emc_rc) }, + { "EmcRfc", TOKEN(emc_rfc) }, + { "EmcRfcSlr", TOKEN(emc_rfc_slr) }, + { "EmcRas", TOKEN(emc_ras) }, + { "EmcRp", TOKEN(emc_rp) }, + { "EmcR2r", TOKEN(emc_r2r) }, + { "EmcW2w", TOKEN(emc_w2w) }, + { "EmcR2w", TOKEN(emc_r2w) }, + { "EmcW2r", TOKEN(emc_w2r) }, + { "EmcR2p", TOKEN(emc_r2p) }, + { "EmcW2p", TOKEN(emc_w2p) }, + { "EmcRrd", TOKEN(emc_rrd) }, + { "EmcRdRcd", TOKEN(emc_rd_rcd) }, + { "EmcWrRcd", TOKEN(emc_wr_rcd) }, + { "EmcRext", TOKEN(emc_rext) }, + { "EmcWdv", TOKEN(emc_wdv) }, + { "EmcWdvMask", TOKEN(emc_wdv_mask) }, + { "EmcQUse", TOKEN(emc_quse) }, + { "EmcQuseWidth", TOKEN(emc_quse_width) }, + { "EmcIbdly", TOKEN(emc_ibdly) }, + { "EmcEInput", TOKEN(emc_einput) }, + { "EmcEInputDuration", TOKEN(emc_einput_duration) }, + { "EmcPutermExtra", TOKEN(emc_puterm_extra) }, + { "EmcPutermWidth", TOKEN(emc_puterm_width) }, + { "EmcPutermAdj", TOKEN(emc_puterm_adj) }, + { "EmcCdbCntl1", TOKEN(emc_cdb_cntl1) }, + { "EmcCdbCntl2", TOKEN(emc_cdb_cntl2) }, + { "EmcCdbCntl3", TOKEN(emc_cdb_cntl3) }, + { "EmcQRst", TOKEN(emc_qrst) }, + { "EmcQSafe", TOKEN(emc_qsafe) }, + { "EmcRdv", TOKEN(emc_rdv) }, + { "EmcRdvMask", TOKEN(emc_rdv_mask) }, + { "EmcQpop", TOKEN(emc_qpop) }, + { "EmcRefresh", TOKEN(emc_refresh) }, + { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, + { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, + { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, + { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, + { "EmcAct2Pden", TOKEN(emc_act2pden) }, + { "EmcAr2Pden", TOKEN(emc_ar2pden) }, + { "EmcRw2Pden", TOKEN(emc_rw2pden) }, + { "EmcTxsr", TOKEN(emc_txsr) }, + { "EmcTcke", TOKEN(emc_tcke) }, + { "EmcTckesr", TOKEN(emc_tckesr) }, + { "EmcTpd", TOKEN(emc_tpd) }, + { "EmcTfaw", TOKEN(emc_tfaw) }, + { "EmcTrpab", TOKEN(emc_trpab) }, + { "EmcTClkStable", TOKEN(emc_tclkstable) }, + { "EmcTClkStop", TOKEN(emc_tclkstop) }, + { "EmcTRefBw", TOKEN(emc_trefbw) }, + { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, + { "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) }, + { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, + { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, + { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, + { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, + { "EmcMrs", TOKEN(emc_mrs) }, + { "EmcEmrs2", TOKEN(emc_emrs2) }, + { "EmcEmrs3", TOKEN(emc_emrs3) }, + { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, + { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, + { "EmcEmrs", TOKEN(emc_emrs) }, + { "EmcMrw1", TOKEN(emc_mrw1) }, + { "EmcMrw2", TOKEN(emc_mrw2) }, + { "EmcMrw3", TOKEN(emc_mrw3) }, + { "EmcMrw4", TOKEN(emc_mrw4) }, + { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, + { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, + { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, + { "McEmemCfg", TOKEN(mc_emem_cfg) }, + { "EmcCfg2", TOKEN(emc_cfg2) }, + { "EmcCfgPipe", TOKEN(emc_cfg_pipe) }, + { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, + { "EmcCfgDigDllPeriod", TOKEN(emc_cfg_dig_dll_period) }, + { "EmcCfg", TOKEN(emc_cfg) }, + { "EmcDbg", TOKEN(emc_dbg) }, + { "WarmBootWait", TOKEN(warm_boot_wait) }, + { "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) }, + { "EmcOdtWrite", TOKEN(emc_odt_write) }, + { "EmcOdtRead", TOKEN(emc_odt_read) }, + { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, + { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, + { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, + { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, + { "EmcClockSource", TOKEN(emc_clock_source) }, + { "EmcPinExtraWait", TOKEN(emc_pin_extra_wait) }, + { "EmcTimingControlWait", TOKEN(emc_timing_control_wait) }, + { "EmcWext", TOKEN(emc_wext) }, + { "EmcCtt", TOKEN(emc_ctt) }, + { "EmcCttDuration", TOKEN(emc_ctt_duration) }, + { "EmcPreRefreshReqCnt", TOKEN(emc_prerefresh_req_cnt) }, + { "EmcTxsrDll", TOKEN(emc_txsr_dll) }, + { "EmcCfgRsv", TOKEN(emc_cfg_rsv) }, + { "EmcMrwExtra", TOKEN(emc_mrw_extra) }, + { "EmcWarmBootMrwExtra", TOKEN(emc_warm_boot_mrw_extra) }, + { "EmcWarmBootExtraModeRegWriteEnable", + TOKEN(emc_warm_boot_extramode_reg_write_enable) }, + { "EmcExtraModeRegWriteEnable", TOKEN(emc_extramode_reg_write_enable) }, + { "EmcMrsWaitCnt", TOKEN(emc_mrs_wait_cnt) }, + { "EmcMrsWaitCnt2", TOKEN(emc_mrs_wait_cnt2) }, + { "EmcCmdQ", TOKEN(emc_cmd_q) }, + { "EmcMc2EmcQ", TOKEN(emc_mc2emc_q) }, + { "EmcDynSelfRefControl", TOKEN(emc_dyn_self_ref_control) }, + { "AhbArbitrationXbarCtrlMemInitDone", + TOKEN(ahb_arbitration_xbar_ctrl_meminit_done) }, + { "EmcDevSelect", TOKEN(emc_dev_select) }, + { "EmcSelDpdCtrl", TOKEN(emc_sel_dpd_ctrl) }, + { "EmcDllXformDqs0", TOKEN(emc_dll_xform_dqs0) }, + { "EmcDllXformDqs1", TOKEN(emc_dll_xform_dqs1) }, + { "EmcDllXformDqs2", TOKEN(emc_dll_xform_dqs2) }, + { "EmcDllXformDqs3", TOKEN(emc_dll_xform_dqs3) }, + { "EmcDllXformDqs4", TOKEN(emc_dll_xform_dqs4) }, + { "EmcDllXformDqs5", TOKEN(emc_dll_xform_dqs5) }, + { "EmcDllXformDqs6", TOKEN(emc_dll_xform_dqs6) }, + { "EmcDllXformDqs7", TOKEN(emc_dll_xform_dqs7) }, + { "EmcDllXformDqs8", TOKEN(emc_dll_xform_dqs8) }, + { "EmcDllXformDqs9", TOKEN(emc_dll_xform_dqs9) }, + { "EmcDllXformDqs10", TOKEN(emc_dll_xform_dqs10) }, + { "EmcDllXformDqs11", TOKEN(emc_dll_xform_dqs11) }, + { "EmcDllXformDqs12", TOKEN(emc_dll_xform_dqs12) }, + { "EmcDllXformDqs13", TOKEN(emc_dll_xform_dqs13) }, + { "EmcDllXformDqs14", TOKEN(emc_dll_xform_dqs14) }, + { "EmcDllXformDqs15", TOKEN(emc_dll_xform_dqs15) }, + { "EmcDllXformQUse0", TOKEN(emc_dll_xform_quse0) }, + { "EmcDllXformQUse1", TOKEN(emc_dll_xform_quse1) }, + { "EmcDllXformQUse2", TOKEN(emc_dll_xform_quse2) }, + { "EmcDllXformQUse3", TOKEN(emc_dll_xform_quse3) }, + { "EmcDllXformQUse4", TOKEN(emc_dll_xform_quse4) }, + { "EmcDllXformQUse5", TOKEN(emc_dll_xform_quse5) }, + { "EmcDllXformQUse6", TOKEN(emc_dll_xform_quse6) }, + { "EmcDllXformQUse7", TOKEN(emc_dll_xform_quse7) }, + { "EmcDllXformAddr0", TOKEN(emc_dll_xform_addr0) }, + { "EmcDllXformAddr1", TOKEN(emc_dll_xform_addr1) }, + { "EmcDllXformAddr2", TOKEN(emc_dll_xform_addr2) }, + { "EmcDllXformAddr3", TOKEN(emc_dll_xform_addr3) }, + { "EmcDllXformAddr4", TOKEN(emc_dll_xform_addr4) }, + { "EmcDllXformAddr5", TOKEN(emc_dll_xform_addr5) }, + { "EmcDllXformQUse8", TOKEN(emc_dll_xform_quse8) }, + { "EmcDllXformQUse9", TOKEN(emc_dll_xform_quse9) }, + { "EmcDllXformQUse10", TOKEN(emc_dll_xform_quse10) }, + { "EmcDllXformQUse11", TOKEN(emc_dll_xform_quse11) }, + { "EmcDllXformQUse12", TOKEN(emc_dll_xform_quse12) }, + { "EmcDllXformQUse13", TOKEN(emc_dll_xform_quse13) }, + { "EmcDllXformQUse14", TOKEN(emc_dll_xform_quse14) }, + { "EmcDllXformQUse15", TOKEN(emc_dll_xform_quse15) }, + { "EmcDliTrimTxDqs0", TOKEN(emc_dli_trim_tx_dqs0) }, + { "EmcDliTrimTxDqs1", TOKEN(emc_dli_trim_tx_dqs1) }, + { "EmcDliTrimTxDqs2", TOKEN(emc_dli_trim_tx_dqs2) }, + { "EmcDliTrimTxDqs3", TOKEN(emc_dli_trim_tx_dqs3) }, + { "EmcDliTrimTxDqs4", TOKEN(emc_dli_trim_tx_dqs4) }, + { "EmcDliTrimTxDqs5", TOKEN(emc_dli_trim_tx_dqs5) }, + { "EmcDliTrimTxDqs6", TOKEN(emc_dli_trim_tx_dqs6) }, + { "EmcDliTrimTxDqs7", TOKEN(emc_dli_trim_tx_dqs7) }, + { "EmcDliTrimTxDqs8", TOKEN(emc_dli_trim_tx_dqs8) }, + { "EmcDliTrimTxDqs9", TOKEN(emc_dli_trim_tx_dqs9) }, + { "EmcDliTrimTxDqs10", TOKEN(emc_dli_trim_tx_dqs10) }, + { "EmcDliTrimTxDqs11", TOKEN(emc_dli_trim_tx_dqs11) }, + { "EmcDliTrimTxDqs12", TOKEN(emc_dli_trim_tx_dqs12) }, + { "EmcDliTrimTxDqs13", TOKEN(emc_dli_trim_tx_dqs13) }, + { "EmcDliTrimTxDqs14", TOKEN(emc_dli_trim_tx_dqs14) }, + { "EmcDliTrimTxDqs15", TOKEN(emc_dli_trim_tx_dqs15) }, + { "EmcDllXformDq0", TOKEN(emc_dll_xform_dq0) }, + { "EmcDllXformDq1", TOKEN(emc_dll_xform_dq1) }, + { "EmcDllXformDq2", TOKEN(emc_dll_xform_dq2) }, + { "EmcDllXformDq3", TOKEN(emc_dll_xform_dq3) }, + { "EmcDllXformDq4", TOKEN(emc_dll_xform_dq4) }, + { "EmcDllXformDq5", TOKEN(emc_dll_xform_dq5) }, + { "EmcDllXformDq6", TOKEN(emc_dll_xform_dq6) }, + { "EmcDllXformDq7", TOKEN(emc_dll_xform_dq7) }, + { "EmcZcalInterval", TOKEN(emc_zcal_interval) }, + { "EmcZcalInitDev0", TOKEN(emc_zcal_init_dev0) }, + { "EmcZcalInitDev1", TOKEN(emc_zcal_init_dev1) }, + { "EmcZcalInitWait", TOKEN(emc_zcal_init_wait) }, + { "EmcZcalWarmColdBootEnables", TOKEN(emc_zcal_warm_cold_boot_enables) }, + { "EmcMrwLpddr2ZcalWarmBoot", TOKEN(emc_mrw_lpddr2zcal_warm_boot) }, + { "EmcZqCalDdr3WarmBoot", TOKEN(emc_zqcal_ddr3_warm_boot) }, + { "EmcZcalWarmBootWait", TOKEN(emc_zcal_warm_boot_wait) }, + { "EmcMrsWarmBootEnable", TOKEN(emc_mrs_warm_boot_enable) }, + { "EmcMrsExtra", TOKEN(emc_mrs_extra) }, + { "EmcWarmBootMrsExtra", TOKEN(emc_warm_boot_mrs_extra) }, + { "EmcClkenOverride", TOKEN(emc_clken_override) }, + { "McDisExtraSnapLevels", TOKEN(mc_dis_extra_snap_levels) }, + { "EmcExtraRefreshNum", TOKEN(emc_extra_refresh_num) }, + { "EmcClkenOverrideAllWarmBoot", + TOKEN(emc_clken_override_allwarm_boot) }, + { "McClkenOverrideAllWarmBoot", TOKEN(mc_clken_override_allwarm_boot) }, + { "EmcCfgDigDllPeriodWarmBoot", + TOKEN(emc_cfg_dig_dll_period_warm_boot) }, + { "PmcVddpSel", TOKEN(pmc_vddp_sel) }, + { "PmcVddpSelWait", TOKEN(pmc_vddp_sel_wait) }, + { "PmcDdrCfg", TOKEN(pmc_ddr_cfg) }, + { "PmcIoDpd3Req", TOKEN(pmc_io_dpd3_req) }, + { "PmcIoDpd3ReqWait", TOKEN(pmc_io_dpd3_req_wait) }, + { "PmcRegShort", TOKEN(pmc_reg_short) }, + { "PmcNoIoPower", TOKEN(pmc_no_io_power) }, + { "PmcPorDpdCtrlWait", TOKEN(pmc_por_dpd_ctrl_wait) }, + { "EmcXm2CmdPadCtrl", TOKEN(emc_xm2cmd_pad_ctrl) }, + { "EmcXm2CmdPadCtrl2", TOKEN(emc_xm2cmd_pad_ctrl2) }, + { "EmcXm2CmdPadCtrl3", TOKEN(emc_xm2cmd_pad_ctrl3) }, + { "EmcXm2CmdPadCtrl4", TOKEN(emc_xm2cmd_pad_ctrl4) }, + { "EmcXm2CmdPadCtrl5", TOKEN(emc_xm2cmd_pad_ctrl5) }, + { "EmcXm2DqsPadCtrl", TOKEN(emc_xm2dqs_pad_ctrl) }, + { "EmcXm2DqsPadCtrl2", TOKEN(emc_xm2dqs_pad_ctrl2) }, + { "EmcXm2DqsPadCtrl3", TOKEN(emc_xm2dqs_pad_ctrl3) }, + { "EmcXm2DqsPadCtrl4", TOKEN(emc_xm2dqs_pad_ctrl4) }, + { "EmcXm2DqsPadCtrl5", TOKEN(emc_xm2dqs_pad_ctrl5) }, + { "EmcXm2DqsPadCtrl6", TOKEN(emc_xm2dqs_pad_ctrl6) }, + { "EmcXm2DqPadCtrl", TOKEN(emc_xm2dq_pad_ctrl) }, + { "EmcXm2DqPadCtrl2", TOKEN(emc_xm2dq_pad_ctrl2) }, + { "EmcXm2DqPadCtrl3", TOKEN(emc_xm2dq_pad_ctrl3) }, + { "EmcXm2ClkPadCtrl", TOKEN(emc_xm2clk_pad_ctrl) }, + { "EmcXm2ClkPadCtrl2", TOKEN(emc_xm2clk_pad_ctrl2) }, + { "EmcXm2CompPadCtrl", TOKEN(emc_xm2comp_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl", TOKEN(emc_xm2vttgen_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl2", TOKEN(emc_xm2vttgen_pad_ctrl2) }, + { "EmcXm2VttGenPadCtrl3", TOKEN(emc_xm2vttgen_pad_ctrl3) }, + { "EmcAcpdControl", TOKEN(emc_acpd_control) }, + { "EmcSwizzleRank0ByteCfg", TOKEN(emc_swizzle_rank0_byte_cfg) }, + { "EmcSwizzleRank0Byte0", TOKEN(emc_swizzle_rank0_byte0) }, + { "EmcSwizzleRank0Byte1", TOKEN(emc_swizzle_rank0_byte1) }, + { "EmcSwizzleRank0Byte2", TOKEN(emc_swizzle_rank0_byte2) }, + { "EmcSwizzleRank0Byte3", TOKEN(emc_swizzle_rank0_byte3) }, + { "EmcSwizzleRank1ByteCfg", TOKEN(emc_swizzle_rank1_byte_cfg) }, + { "EmcSwizzleRank1Byte0", TOKEN(emc_swizzle_rank1_byte0) }, + { "EmcSwizzleRank1Byte1", TOKEN(emc_swizzle_rank1_byte1) }, + { "EmcSwizzleRank1Byte2", TOKEN(emc_swizzle_rank1_byte2) }, + { "EmcSwizzleRank1Byte3", TOKEN(emc_swizzle_rank1_byte3) }, + { "EmcDsrVttgenDrv", TOKEN(emc_dsr_vttgen_drv) }, + { "EmcTxdsrvttgen", TOKEN(emc_txdsrvttgen) }, + { "EmcBgbiasCtl0", TOKEN(emc_bgbias_ctl0) }, + { "McEmemAdrCfg", TOKEN(mc_emem_adr_cfg) }, + { "McEmemAdrCfgDev0", TOKEN(mc_emem_adr_cfg_dev0) }, + { "McEmemAdrCfgDev1", TOKEN(mc_emem_adr_cfg_dev1) }, + { "McEmemAdrCfgBankMask0", TOKEN(mc_emem_adr_cfg_bank_mask0) }, + { "McEmemAdrCfgBankMask1", TOKEN(mc_emem_adr_cfg_bank_mask1) }, + { "McEmemAdrCfgBankMask2", TOKEN(mc_emem_adr_cfg_bank_mask2) }, + { "McEmemAdrCfgBankSwizzle3", TOKEN(mc_emem_adr_cfg_bank_swizzle3) }, + { "McEmemArbCfg", TOKEN(mc_emem_arb_cfg) }, + { "McEmemArbOutstandingReq", TOKEN(mc_emem_arb_outstanding_req) }, + { "McEmemArbTimingRcd", TOKEN(mc_emem_arb_timing_rcd) }, + { "McEmemArbTimingRp", TOKEN(mc_emem_arb_timing_rp) }, + { "McEmemArbTimingRc", TOKEN(mc_emem_arb_timing_rc) }, + { "McEmemArbTimingRas", TOKEN(mc_emem_arb_timing_ras) }, + { "McEmemArbTimingFaw", TOKEN(mc_emem_arb_timing_faw) }, + { "McEmemArbTimingRrd", TOKEN(mc_emem_arb_timing_rrd) }, + { "McEmemArbTimingRap2Pre", TOKEN(mc_emem_arb_timing_rap2pre) }, + { "McEmemArbTimingWap2Pre", TOKEN(mc_emem_arb_timing_wap2pre) }, + { "McEmemArbTimingR2R", TOKEN(mc_emem_arb_timing_r2r) }, + { "McEmemArbTimingW2W", TOKEN(mc_emem_arb_timing_w2w) }, + { "McEmemArbTimingR2W", TOKEN(mc_emem_arb_timing_r2w) }, + { "McEmemArbTimingW2R", TOKEN(mc_emem_arb_timing_w2r) }, + { "McEmemArbDaTurns", TOKEN(mc_emem_arb_da_turns) }, + { "McEmemArbDaCovers", TOKEN(mc_emem_arb_da_covers) }, + { "McEmemArbMisc0", TOKEN(mc_emem_arb_misc0) }, + { "McEmemArbMisc1", TOKEN(mc_emem_arb_misc1) }, + { "McEmemArbRing1Throttle", TOKEN(mc_emem_arb_ring1_throttle) }, + { "McEmemArbOverride", TOKEN(mc_emem_arb_override) }, + { "McEmemArbOverride1", TOKEN(mc_emem_arb_override1) }, + { "McEmemArbRsv", TOKEN(mc_emem_arb_rsv) }, + { "McClkenOverride", TOKEN(mc_clken_override) }, + { "McStatControl", TOKEN(mc_stat_control) }, + { "McDisplaySnapRing", TOKEN(mc_display_snap_ring) }, + { "McVideoProtectBom", TOKEN(mc_video_protect_bom) }, + { "McVideoProtectBomAdrHi", + TOKEN(mc_video_protect_bom_adr_hi) }, + { "McVideoProtectSizeMb", TOKEN(mc_video_protect_size_mb) }, + { "McVideoProtectVprOverride", TOKEN(mc_video_protect_vpr_override) }, + { "McVideoProtectVprOverride1", TOKEN(mc_video_protect_vpr_override1) }, + { "McVideoProtectGpuOverride0", TOKEN(mc_video_protect_gpu_override0) }, + { "McVideoProtectGpuOverride1", TOKEN(mc_video_protect_gpu_override1) }, + { "McSecCarveoutBom", TOKEN(mc_sec_carveout_bom) }, + { "McSecCarveoutAdrHi", TOKEN(mc_sec_carveout_adr_hi) }, + { "McSecCarveoutSizeMb", TOKEN(mc_sec_carveout_size_mb) }, + { "McVideoProtectWriteAccess", TOKEN(mc_video_protect_write_access) }, + { "McSecCarveoutProtectWriteAccess", + TOKEN(mc_sec_carveout_protect_write_access) }, + { "EmcCaTrainingEnable", TOKEN(emc_ca_training_enable) }, + { "EmcCaTrainingTimingCntl1", TOKEN(emc_ca_training_timing_cntl1) }, + { "EmcCaTrainingTimingCntl2", TOKEN(emc_ca_training_timing_cntl2) }, + { "SwizzleRankByteEncode", TOKEN(swizzle_rank_byte_encode) }, + { "BootRomPatchControl", TOKEN(boot_rom_patch_control) }, + { "BootRomPatchData", TOKEN(boot_rom_patch_data) }, + { "McMtsCarveoutBom", TOKEN(mc_mts_carveout_bom) }, + { "McMtsCarveoutAdrHi", TOKEN(mc_mts_carveout_adr_hi) }, + { "McMtsCarveoutSizeMb", TOKEN(mc_mts_carveout_size_mb) }, + { "McMtsCarveoutRegCtrl", TOKEN(mc_mts_carveout_reg_ctrl) }, + { NULL, 0, 0, NULL } +}; + +field_item s_sdmmc_table_t132[] = { + { "ClockDivider", TOKEN(sdmmc_clock_divider) }, + { "DataWidth", + token_sdmmc_data_width, + field_type_enum, + s_sdmmc_data_width_table_t132 }, + { "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) }, + { "MultiPageSupport", TOKEN(sdmmc_multi_page_support) }, + { NULL, 0, 0, NULL } +}; + +field_item s_spiflash_table_t132[] = { + { "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) }, + { "PageSize2kor16k", TOKEN(spiflash_page_size_2k_or_16k) }, + { "ClockDivider", TOKEN(spiflash_clock_divider) }, + { "ClockSource", + token_spiflash_clock_source, + field_type_enum, + s_spi_clock_source_table_t132 }, + { NULL, 0, 0, NULL } +}; + +parse_subfield_item s_device_type_table_t132[] = { + { "SdmmcParams.", token_sdmmc_params, + s_sdmmc_table_t132, t132_set_dev_param }, + { "SpiFlashParams.", token_spiflash_params, + s_spiflash_table_t132, t132_set_dev_param }, + { NULL, 0, NULL } +}; diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t20/nvbctlib_t20.c b/firmware/coreboot/util/nvidia/cbootimage/src/t20/nvbctlib_t20.c new file mode 100644 index 0000000000..7a916b43bc --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t20/nvbctlib_t20.c @@ -0,0 +1,729 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include "../cbootimage.h" +#include "../parse.h" +#include "../crypto.h" +#include "nvboot_bct_t20.h" +#include "string.h" + +/* nvbctlib_t20.c: The implementation of the nvbctlib API for t20. */ + +/* Definitions that simplify the code which follows. */ +#define CASE_GET_SDRAM_PARAM(x) \ +case token_##x:\ + *value = params->x; \ + break + +#define CASE_SET_SDRAM_PARAM(x) \ +case token_##x:\ + params->x = value; \ + break + +#define CASE_GET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + *value = bct->dev_params[index].dev##_params.x; \ + break + +#define CASE_SET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + bct->dev_params[index].dev##_params.x = value; \ + break + +#define CASE_GET_BL_PARAM(x) \ +case token_bl_##x:\ + *data = bct_ptr->bootloader[set].x; \ + break + +#define CASE_SET_BL_PARAM(x) \ +case token_bl_##x:\ + bct_ptr->bootloader[set].x = *data; \ + break + +#define CASE_GET_NVU32(id) \ +case token_##id:\ + if (bct == NULL) return -ENODATA; \ + *((uint32_t *)data) = bct_ptr->id; \ + break + +#define CASE_GET_CONST(id, val) \ +case token_##id:\ + *((uint32_t *)data) = val; \ + break + +#define CASE_GET_CONST_PREFIX(id, val_prefix) \ +case token_##id:\ + *((uint32_t *)data) = val_prefix##_##id; \ + break + +#define CASE_SET_NVU32(id) \ +case token_##id:\ + bct_ptr->id = *((uint32_t *)data); \ + break + +#define CASE_GET_DATA(id, size) \ +case token_##id:\ + if (*length < size) return -ENODATA;\ + memcpy(data, &(bct_ptr->id), size); \ + *length = size;\ + break + +#define CASE_SET_DATA(id, size) \ +case token_##id:\ + if (length < size) return -ENODATA;\ + memcpy(&(bct_ptr->id), data, size); \ + break + +#define DEFAULT() \ +default : \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +parse_token t20_root_token_list[] = { + token_boot_data_version, + token_block_size, + token_page_size, + token_partition_size, + token_odm_data, + token_bootloader_used, + token_bootloaders_max, + token_bct_size, + token_hash_size, + token_crypto_offset, + token_crypto_length, + token_max_bct_search_blks +}; + +int +t20_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1); + + switch (token) { + CASE_SET_DEV_PARAM(nand, clock_divider); + CASE_SET_DEV_PARAM(nand, nand_timing); + CASE_SET_DEV_PARAM(nand, nand_timing2); + CASE_SET_DEV_PARAM(nand, block_size_log2); + CASE_SET_DEV_PARAM(nand, page_size_log2); + + CASE_SET_DEV_PARAM(sdmmc, clock_divider); + CASE_SET_DEV_PARAM(sdmmc, data_width); + CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + + CASE_SET_DEV_PARAM(spiflash, clock_source); + CASE_SET_DEV_PARAM(spiflash, clock_divider); + CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + bct->dev_type[index] = value; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + switch (token) { + CASE_GET_DEV_PARAM(nand, clock_divider); + CASE_GET_DEV_PARAM(nand, nand_timing); + CASE_GET_DEV_PARAM(nand, nand_timing2); + CASE_GET_DEV_PARAM(nand, block_size_log2); + CASE_GET_DEV_PARAM(nand, page_size_log2); + + CASE_GET_DEV_PARAM(sdmmc, clock_divider); + CASE_GET_DEV_PARAM(sdmmc, data_width); + CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); + + CASE_GET_DEV_PARAM(spiflash, clock_source); + CASE_GET_DEV_PARAM(spiflash, clock_divider); + CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + *value = bct->dev_type[index]; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + /* Update the number of SDRAM parameter sets. */ + bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1); + + switch (token) { + CASE_SET_SDRAM_PARAM(memory_type); + CASE_SET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); + CASE_SET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); + CASE_SET_SDRAM_PARAM(pllm_input_divider); + CASE_SET_SDRAM_PARAM(pllm_feedback_divider); + CASE_SET_SDRAM_PARAM(pllm_post_divider); + CASE_SET_SDRAM_PARAM(pllm_stable_time); + CASE_SET_SDRAM_PARAM(emc_clock_divider); + CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config); + CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_SET_SDRAM_PARAM(emc_pin_program_wait); + CASE_SET_SDRAM_PARAM(emc_rc); + CASE_SET_SDRAM_PARAM(emc_rfc); + CASE_SET_SDRAM_PARAM(emc_ras); + CASE_SET_SDRAM_PARAM(emc_rp); + CASE_SET_SDRAM_PARAM(emc_r2w); + CASE_SET_SDRAM_PARAM(emc_w2r); + CASE_SET_SDRAM_PARAM(emc_r2p); + CASE_SET_SDRAM_PARAM(emc_w2p); + CASE_SET_SDRAM_PARAM(emc_rd_rcd); + CASE_SET_SDRAM_PARAM(emc_wr_rcd); + CASE_SET_SDRAM_PARAM(emc_rrd); + CASE_SET_SDRAM_PARAM(emc_rext); + CASE_SET_SDRAM_PARAM(emc_wdv); + CASE_SET_SDRAM_PARAM(emc_quse); + CASE_SET_SDRAM_PARAM(emc_qrst); + CASE_SET_SDRAM_PARAM(emc_qsafe); + CASE_SET_SDRAM_PARAM(emc_rdv); + CASE_SET_SDRAM_PARAM(emc_refresh); + CASE_SET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_SET_SDRAM_PARAM(emc_pdex2wr); + CASE_SET_SDRAM_PARAM(emc_pdex2rd); + CASE_SET_SDRAM_PARAM(emc_pchg2pden); + CASE_SET_SDRAM_PARAM(emc_act2pden); + CASE_SET_SDRAM_PARAM(emc_ar2pden); + CASE_SET_SDRAM_PARAM(emc_rw2pden); + CASE_SET_SDRAM_PARAM(emc_txsr); + CASE_SET_SDRAM_PARAM(emc_tcke); + CASE_SET_SDRAM_PARAM(emc_tfaw); + CASE_SET_SDRAM_PARAM(emc_trpab); + CASE_SET_SDRAM_PARAM(emc_tclkstable); + CASE_SET_SDRAM_PARAM(emc_tclkstop); + CASE_SET_SDRAM_PARAM(emc_trefbw); + CASE_SET_SDRAM_PARAM(emc_quse_extra); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg1); + CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly); + CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb); + CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly); + CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly_msb); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_SET_SDRAM_PARAM(emc_fbio_spare); + CASE_SET_SDRAM_PARAM(emc_mrs); + CASE_SET_SDRAM_PARAM(emc_emrs); + CASE_SET_SDRAM_PARAM(emc_mrw1); + CASE_SET_SDRAM_PARAM(emc_mrw2); + CASE_SET_SDRAM_PARAM(emc_mrw3); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_SET_SDRAM_PARAM(emc_adr_cfg); + CASE_SET_SDRAM_PARAM(emc_adr_cfg1); + CASE_SET_SDRAM_PARAM(mc_emem_cfg); + CASE_SET_SDRAM_PARAM(mc_lowlatency_config); + CASE_SET_SDRAM_PARAM(emc_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg2); + CASE_SET_SDRAM_PARAM(emc_dbg); + CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse); + CASE_SET_SDRAM_PARAM(warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_SET_SDRAM_PARAM(emc_odt_write); + CASE_SET_SDRAM_PARAM(emc_odt_read); + CASE_SET_SDRAM_PARAM(emc_zcal_ref_cnt); + CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev0); + CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev1); + CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_wait); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_SET_SDRAM_PARAM(emc_emrs_emr2); + CASE_SET_SDRAM_PARAM(emc_emrs_emr3); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_SET_SDRAM_PARAM(emc_ddr2_wait); + CASE_SET_SDRAM_PARAM(emc_cfg_clktrim0); + CASE_SET_SDRAM_PARAM(emc_cfg_clktrim1); + CASE_SET_SDRAM_PARAM(emc_cfg_clktrim2); + CASE_SET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl); + CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl); + + DEFAULT(); + } + return 0; +} + +int +t20_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + + switch (token) { + CASE_GET_SDRAM_PARAM(memory_type); + CASE_GET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_input_divider); + CASE_GET_SDRAM_PARAM(pllm_feedback_divider); + CASE_GET_SDRAM_PARAM(pllm_post_divider); + CASE_GET_SDRAM_PARAM(pllm_stable_time); + CASE_GET_SDRAM_PARAM(emc_clock_divider); + CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config); + CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_GET_SDRAM_PARAM(emc_pin_program_wait); + CASE_GET_SDRAM_PARAM(emc_rc); + CASE_GET_SDRAM_PARAM(emc_rfc); + CASE_GET_SDRAM_PARAM(emc_ras); + CASE_GET_SDRAM_PARAM(emc_rp); + CASE_GET_SDRAM_PARAM(emc_r2w); + CASE_GET_SDRAM_PARAM(emc_w2r); + CASE_GET_SDRAM_PARAM(emc_r2p); + CASE_GET_SDRAM_PARAM(emc_w2p); + CASE_GET_SDRAM_PARAM(emc_rd_rcd); + CASE_GET_SDRAM_PARAM(emc_wr_rcd); + CASE_GET_SDRAM_PARAM(emc_rrd); + CASE_GET_SDRAM_PARAM(emc_rext); + CASE_GET_SDRAM_PARAM(emc_wdv); + CASE_GET_SDRAM_PARAM(emc_quse); + CASE_GET_SDRAM_PARAM(emc_qrst); + CASE_GET_SDRAM_PARAM(emc_qsafe); + CASE_GET_SDRAM_PARAM(emc_rdv); + CASE_GET_SDRAM_PARAM(emc_refresh); + CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_GET_SDRAM_PARAM(emc_pdex2wr); + CASE_GET_SDRAM_PARAM(emc_pdex2rd); + CASE_GET_SDRAM_PARAM(emc_pchg2pden); + CASE_GET_SDRAM_PARAM(emc_act2pden); + CASE_GET_SDRAM_PARAM(emc_ar2pden); + CASE_GET_SDRAM_PARAM(emc_rw2pden); + CASE_GET_SDRAM_PARAM(emc_txsr); + CASE_GET_SDRAM_PARAM(emc_tcke); + CASE_GET_SDRAM_PARAM(emc_tfaw); + CASE_GET_SDRAM_PARAM(emc_trpab); + CASE_GET_SDRAM_PARAM(emc_tclkstable); + CASE_GET_SDRAM_PARAM(emc_tclkstop); + CASE_GET_SDRAM_PARAM(emc_trefbw); + CASE_GET_SDRAM_PARAM(emc_quse_extra); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg1); + CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly); + CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb); + CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly); + CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly_msb); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_GET_SDRAM_PARAM(emc_fbio_spare); + CASE_GET_SDRAM_PARAM(emc_mrs); + CASE_GET_SDRAM_PARAM(emc_emrs); + CASE_GET_SDRAM_PARAM(emc_mrw1); + CASE_GET_SDRAM_PARAM(emc_mrw2); + CASE_GET_SDRAM_PARAM(emc_mrw3); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_GET_SDRAM_PARAM(emc_adr_cfg); + CASE_GET_SDRAM_PARAM(emc_adr_cfg1); + CASE_GET_SDRAM_PARAM(mc_emem_cfg); + CASE_GET_SDRAM_PARAM(mc_lowlatency_config); + CASE_GET_SDRAM_PARAM(emc_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg2); + CASE_GET_SDRAM_PARAM(emc_dbg); + CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse); + CASE_GET_SDRAM_PARAM(warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_GET_SDRAM_PARAM(emc_odt_write); + CASE_GET_SDRAM_PARAM(emc_odt_read); + CASE_GET_SDRAM_PARAM(emc_zcal_ref_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev0); + CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev1); + CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_wait); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_GET_SDRAM_PARAM(emc_emrs_emr2); + CASE_GET_SDRAM_PARAM(emc_emrs_emr3); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_GET_SDRAM_PARAM(emc_ddr2_wait); + CASE_GET_SDRAM_PARAM(emc_cfg_clktrim0); + CASE_GET_SDRAM_PARAM(emc_cfg_clktrim1); + CASE_GET_SDRAM_PARAM(emc_cfg_clktrim2); + CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl); + CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl); + DEFAULT(); + } + return 0; +} + +int +t20_getbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_GET_BL_PARAM(version); + CASE_GET_BL_PARAM(start_blk); + CASE_GET_BL_PARAM(start_page); + CASE_GET_BL_PARAM(length); + CASE_GET_BL_PARAM(load_addr); + CASE_GET_BL_PARAM(entry_point); + CASE_GET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(data, + &(bct_ptr->bootloader[set].crypto_hash), + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_setbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_SET_BL_PARAM(version); + CASE_SET_BL_PARAM(start_blk); + CASE_SET_BL_PARAM(start_page); + CASE_SET_BL_PARAM(length); + CASE_SET_BL_PARAM(load_addr); + CASE_SET_BL_PARAM(entry_point); + CASE_SET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(&(bct_ptr->bootloader[set].crypto_hash), + data, + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_bct_get_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + nvboot_config_table samplebct; /* Used for computing offsets. */ + + /* + * Note: Not all queries require use of the BCT, so testing for a + * valid BCT is distributed within the code. + */ + if (data == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_GET_NVU32(boot_data_version); + CASE_GET_NVU32(block_size_log2); + CASE_GET_NVU32(page_size_log2); + CASE_GET_NVU32(partition_size); + CASE_GET_NVU32(num_param_sets); + CASE_GET_NVU32(num_sdram_sets); + CASE_GET_NVU32(bootloader_used); + CASE_GET_NVU32(odm_data); + + case token_block_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->block_size_log2; + break; + + case token_page_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->page_size_log2; + break; + + /* + * Constants. + */ + + CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); + CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); + + case token_reserved_offset: + *((uint32_t *)data) = (uint8_t *)&(samplebct.reserved) + - (uint8_t *)&samplebct; + break; + + case token_bct_size: + *((uint32_t *)data) = sizeof(nvboot_config_table); + break; + + CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); + + case token_crypto_offset: + /* Offset to region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)&(samplebct.random_aes_blk) + - (uint8_t *)&samplebct; + break; + + case token_crypto_length: + /* size of region in BCT to encrypt & sign */ + *((uint32_t *)data) = sizeof(nvboot_config_table) - sizeof(nvboot_hash); + break; + + CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); + + CASE_GET_CONST_PREFIX(dev_type_nand, nvboot); + CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); + CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllc_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); + + CASE_GET_CONST_PREFIX(memory_type_none, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot); + + default: + return -ENODATA; + } + return 0; +} + +int +t20_bct_set_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (bct == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_SET_NVU32(boot_data_version); + CASE_SET_NVU32(block_size_log2); + CASE_SET_NVU32(page_size_log2); + CASE_SET_NVU32(partition_size); + CASE_SET_NVU32(num_param_sets); + CASE_SET_NVU32(num_sdram_sets); + CASE_SET_NVU32(bootloader_used); + CASE_SET_NVU32(odm_data); + + default: + return -ENODATA; + } + + return 0; +} + +int +t20_bct_set_data(parse_token id, + uint8_t *data, + uint32_t length, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + + CASE_SET_DATA(crypto_hash, sizeof(nvboot_hash)); + + default: + return -ENODATA; + } + + return 0; +} + +int t20_get_bct_size() +{ + return sizeof(nvboot_config_table); +} + +int t20_bct_token_supported(parse_token token) +{ + int index; + + for (index = 0; index < ARRAY_SIZE(t20_root_token_list); index++) + if (t20_root_token_list[index] == token) + return 1; + + return 0; +} + +void t20_init_bad_block_table(build_image_context *context) +{ + uint32_t bytes_per_entry; + nvboot_badblock_table *table; + nvboot_config_table *bct; + + bct = (nvboot_config_table *)(context->bct); + + assert(context != NULL); + assert(bct != NULL); + + table = &bct->badblock_table; + + bytes_per_entry = ICEIL(context->partition_size, + NVBOOT_BAD_BLOCK_TABLE_SIZE); + table->block_size_log2 = context->block_size_log2; + table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), + table->block_size_log2); + table->entries_used = iceil_log2(context->partition_size, + table->virtual_blk_size_log2); +} + +cbootimage_soc_config tegra20_config = { + .init_bad_block_table = t20_init_bad_block_table, + .set_dev_param = t20_set_dev_param, + .get_dev_param = t20_get_dev_param, + .set_sdram_param = t20_set_sdram_param, + .get_sdram_param = t20_get_sdram_param, + .setbl_param = t20_setbl_param, + .getbl_param = t20_getbl_param, + .set_value = t20_bct_set_value, + .get_value = t20_bct_get_value, + .set_data = t20_bct_set_data, + .get_bct_size = t20_get_bct_size, + .token_supported = t20_bct_token_supported, + + .devtype_table = s_devtype_table_t20, + .sdmmc_data_width_table = s_sdmmc_data_width_table_t20, + .spi_clock_source_table = s_spi_clock_source_table_t20, + .nvboot_memory_type_table = s_nvboot_memory_type_table_t20, + .sdram_field_table = s_sdram_field_table_t20, + .nand_table = s_nand_table_t20, + .sdmmc_table = s_sdmmc_table_t20, + .spiflash_table = s_spiflash_table_t20, + .device_type_table = s_device_type_table_t20, +}; + +void t20_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + context->boot_data_version = BOOTDATA_VERSION_T20; + *soc_config = &tegra20_config; +} + +int if_bct_is_t20_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + nvboot_config_table * bct = (nvboot_config_table *) context->bct; + + if (bct->boot_data_version == BOOTDATA_VERSION_T20) + { + t20_get_soc_config(context, soc_config); + return 1; + } + return 0; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t20/nvboot_bct_t20.h b/firmware/coreboot/util/nvidia/cbootimage/src/t20/nvboot_bct_t20.h new file mode 100644 index 0000000000..8625a93767 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t20/nvboot_bct_t20.h @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#ifndef INCLUDED_NVBOOT_BCT_T20_H +#define INCLUDED_NVBOOT_BCT_T20_H + +#include +#include "nvboot_sdram_param_t20.h" + +/** + * Defines the number of 32-bit words in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_WORDS 296 + +/** + * Defines the number of bytes in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_SIZE \ + (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) + +/** + * Defines the number of bytes in the reserved area of the BCT. + */ +#define NVBOOT_BCT_RESERVED_SIZE 3 + +/** + * Defines the maximum number of bootloader descriptions in the BCT. + */ +#define NVBOOT_MAX_BOOTLOADERS 4 + +/** + * Defines the maximum number of device parameter sets in the BCT. + * The value must be equal to (1 << # of device straps) + */ +#define NVBOOT_BCT_MAX_PARAM_SETS 4 + +/** + * Defines the maximum number of SDRAM parameter sets in the BCT. + * The value must be equal to (1 << # of SDRAM straps) + */ +#define NVBOOT_BCT_MAX_SDRAM_SETS 4 + +/** + * Defines the number of entries (bits) in the bad block table. + * The consequences of changing its value are as follows. Using P as the + * # of physical blocks in the boot loader and B as the value of this + * constant: + * B > P: There will be unused storage in the bad block table. + * B < P: The virtual block size will be greater than the physical block + * size, so the granularity of the bad block table will be less than + * one bit per physical block. + * + * 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one + * bit per block (1 virtual block = 1 physical block). This occupies 512 bytes + * of storage. + */ +#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096 + +/** + * Defines the maximum number of blocks to search for BCTs. + * + * This value covers the initial block and a set of journal blocks. + * + * Ideally, this number will span several erase units for reliable updates + * and tolerance for blocks to become bad with use. Safe updates require + * a minimum of 2 erase units in which BCTs can appear. + * + * To ensure that the BCT search spans a sufficient range of configurations, + * the search block count has been set to 64. This allows for redundancy with + * a wide range of parts and provides room for greater problems in this + * region of the device. + */ +#define NVBOOT_MAX_BCT_SEARCH_BLOCKS 64 + +/* + * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) + */ +enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; + +/** + * Defines the storage for a hash value (128 bits). + */ +typedef struct nvboot_hash_rec { + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; +} nvboot_hash; + +/* Defines the params that can be configured for NAND devices. */ +typedef struct nvboot_nand_params_rec { + /** + * Specifies the clock divider for the PLL_P 432MHz source. + * If it is set to 18, then clock source to Nand controller is + * 432 / 18 = 24MHz. + */ + uint8_t clock_divider; + + /* Specifies the value to be programmed to Nand Timing Register 1 */ + uint32_t nand_timing; + + /* Specifies the value to be programmed to Nand Timing Register 2 */ + uint32_t nand_timing2; + + /* Specifies the block size in log2 bytes */ + uint8_t block_size_log2; + + /* Specifies the page size in log2 bytes */ + uint8_t page_size_log2; +} nvboot_nand_params; + +/* Defines various data widths supported. */ +typedef enum { + /** + * Specifies a 1 bit interface to eMMC. + * Note that 1-bit data width is only for the driver's internal use. + * Fuses doesn't provide option to select 1-bit data width. + * The driver selects 1-bit internally based on need. + * It is used for reading Extended CSD and when the power class + * requirements of a card for 4-bit or 8-bit transfers are not + * supported by the target board. + */ + nvboot_sdmmc_data_width_1bit = 0, + + /* Specifies a 4 bit interface to eMMC. */ + nvboot_sdmmc_data_width_4bit = 1, + + /* Specifies a 8 bit interface to eMMC. */ + nvboot_sdmmc_data_width_8bit = 2, + + nvboot_sdmmc_data_width_num, + nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF +} nvboot_sdmmc_data_width; + +/* Defines the parameters that can be changed after BCT is read. */ +typedef struct nvboot_sdmmc_params_rec { + /** + * Specifies the clock divider for the SDMMC controller's clock source, + * which is PLLP running at 432MHz. If it is set to 18, then the SDMMC + * controller runs at 432/18 = 24MHz. + */ + uint8_t clock_divider; + + /* Specifies the data bus width. Supported data widths are 4/8 bits. */ + nvboot_sdmmc_data_width data_width; + + /** + * Max Power class supported by the target board. + * The driver determines the best data width and clock frequency + * supported within the power class range (0 to Max) if the selected + * data width cannot be used at the chosen clock frequency. + */ + uint8_t max_power_class_supported; +} nvboot_sdmmc_params; + +typedef enum { + /* Specifies SPI clock source to be PLLP. */ + nvboot_spi_clock_source_pllp_out0 = 0, + + /* Specifies SPI clock source to be PLLC. */ + nvboot_spi_clock_source_pllc_out0, + + /* Specifies SPI clock source to be PLLM. */ + nvboot_spi_clock_source_pllm_out0, + + /* Specifies SPI clock source to be ClockM. */ + nvboot_spi_clock_source_clockm, + + nvboot_spi_clock_source_num, + nvboot_spi_clock_source_force32 = 0x7FFFFFF +} nvboot_spi_clock_source; + + +/** + * Defines the parameters SPI FLASH devices. + */ +typedef struct nvboot_spiflash_params_rec { + /** + * Specifies the clock source to use. + */ + nvboot_spi_clock_source clock_source; + + /** + * Specifes the clock divider to use. + * The value is a 7-bit value based on an input clock of 432Mhz. + * Divider = (432+ DesiredFrequency-1)/DesiredFrequency; + * Typical values: + * NORMAL_READ at 20MHz: 22 + * FAST_READ at 33MHz: 14 + * FAST_READ at 40MHz: 11 + * FAST_READ at 50MHz: 9 + */ + uint8_t clock_divider; + + /** + * Specifies the type of command for read operations. + * NV_FALSE specifies a NORMAL_READ Command + * NV_TRUE specifies a FAST_READ Command + */ + uint8_t read_command_type_fast; +} nvboot_spiflash_params; + +/** +* Defines the union of the parameters required by each device. +*/ +typedef union { + /* Specifies optimized parameters for NAND */ + nvboot_nand_params nand_params; + /* Specifies optimized parameters for eMMC and eSD */ + nvboot_sdmmc_params sdmmc_params; + /* Specifies optimized parameters for SPI NOR */ + nvboot_spiflash_params spiflash_params; +} nvboot_dev_params; + +/** + * Identifies the types of devices from which the system booted. + * Used to identify primary and secondary boot devices. + * @note These no longer match the fuse API device values (for + * backward compatibility with AP15). + */ +typedef enum { + /* Specifies a default (unset) value. */ + nvboot_dev_type_none = 0, + + /* Specifies NAND. */ + nvboot_dev_type_nand, + + /* Specifies SPI NOR. */ + nvboot_dev_type_spi = 3, + + /* Specifies SDMMC (either eMMC or eSD). */ + nvboot_dev_type_sdmmc, + + nvboot_dev_type_max, + + /* Ignore -- Forces compilers to make 32-bit enums. */ + nvboot_dev_type_force32 = 0x7FFFFFFF +} nvboot_dev_type; + +/** + * Stores information needed to locate and verify a boot loader. + * + * There is one \c nv_bootloader_info structure for each copy of a BL stored on + * the device. + */ +typedef struct nv_bootloader_info_rec { + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; + nvboot_hash crypto_hash; +} nv_bootloader_info; + +/** + * Defines the bad block table structure stored in the BCT. + */ +typedef struct nvboot_badblock_table_rec { + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; +} nvboot_badblock_table; + +/** + * Contains the information needed to load BLs from the secondary boot device. + * + * - Supplying NumParamSets = 0 indicates not to load any of them. + * - Supplying NumDramSets = 0 indicates not to load any of them. + * - The \c random_aes_blk member exists to increase the difficulty of + * key attacks based on knowledge of this structure. + */ +typedef struct nvboot_config_table_rec { + nvboot_hash crypto_hash; + nvboot_hash random_aes_blk; + uint32_t boot_data_version; + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; + nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; + nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; + uint32_t num_sdram_sets; + nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; + nvboot_badblock_table badblock_table; + uint32_t bootloader_used; + nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + + /* + * ODMDATA is stored in the BCT in IRAM by the BootROM. + * Read the data @ bct_start + (bct_size - 12). This works + * on T20 and T30 BCTs, which are locked down. If this changes + * in new chips, we can revisit this algorithm. + */ + uint32_t odm_data; + uint32_t reserved1; + uint8_t enable_fail_back; + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; +} nvboot_config_table; +#endif /* #ifndef INCLUDED_NVBOOT_BCT_T20_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t20/nvboot_sdram_param_t20.h b/firmware/coreboot/util/nvidia/cbootimage/src/t20/nvboot_sdram_param_t20.h new file mode 100644 index 0000000000..d3d11f49d8 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t20/nvboot_sdram_param_t20.h @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T20_H +#define INCLUDED_NVBOOT_SDRAM_PARAM_T20_H + +#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 + +typedef enum { + /* Specifies the memory type to be undefined */ + nvboot_memory_type_none = 0, + + /* Specifies the memory type to be DDR SDRAM */ + nvboot_memory_type_ddr, + + /* Specifies the memory type to be LPDDR SDRAM */ + nvboot_memory_type_lpddr, + + /* Specifies the memory type to be DDR2 SDRAM */ + nvboot_memory_type_ddr2, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + nvboot_memory_type_lpddr2, + + nvboot_memory_type_num, + nvboot_memory_type_force32 = 0x7FFFFFF +} nvboot_memory_type; + + +/** + * Defines the SDRAM parameter structure + */ +typedef struct nvboot_sdram_params_rec { + /* Specifies the type of memory device */ + nvboot_memory_type memory_type; + + /* Specifies the CPCON value for PllM */ + uint32_t pllm_charge_pump_setup_ctrl; + /* Specifies the LPCON value for PllM */ + uint32_t pllm_loop_filter_setup_ctrl; + /* Specifies the M value for PllM */ + uint32_t pllm_input_divider; + /* Specifies the N value for PllM */ + uint32_t pllm_feedback_divider; + /* Specifies the P value for PllM */ + uint32_t pllm_post_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t pllm_stable_time; + + /* Specifies the divider for the EMC Clock Source */ + uint32_t emc_clock_divider; + + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t emc_auto_cal_interval; + /** + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t emc_auto_cal_config; + /** + * Specifies the time for the calibration to + * stabilize (in microseconds) + */ + uint32_t emc_auto_cal_wait; + + /** + * Specifies the time to wait after pin programming (in microseconds) + * Dram vendors require at least 200us. + */ + uint32_t emc_pin_program_wait; + + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t emc_rc; + /* Specifies the value for EMC_RFC */ + uint32_t emc_rfc; + /* Specifies the value for EMC_RAS */ + uint32_t emc_ras; + /* Specifies the value for EMC_RP */ + uint32_t emc_rp; + /* Specifies the value for EMC_R2W */ + uint32_t emc_r2w; + /* Specifies the value for EMC_R2W */ + uint32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + uint32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + uint32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + uint32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + uint32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + uint32_t emc_rext; + /* Specifies the value for EMC_WDV */ + uint32_t emc_wdv; + /* Specifies the value for EMC_QUSE */ + uint32_t emc_quse; + /* Specifies the value for EMC_QRST */ + uint32_t emc_qrst; + /* Specifies the value for EMC_QSAFE */ + uint32_t emc_qsafe; + /* Specifies the value for EMC_RDV */ + uint32_t emc_rdv; + /* Specifies the value for EMC_REFRESH */ + uint32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t emc_rw2pden; + /* Specifies the value for EMC_TXSR */ + uint32_t emc_txsr; + /* Specifies the value for EMC_TCKE */ + uint32_t emc_tcke; + /* Specifies the value for EMC_TFAW */ + uint32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + uint32_t emc_trefbw; + /* Specifies the value for EMC_QUSE_EXTRA */ + uint32_t emc_quse_extra; + + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG1 */ + uint32_t emc_fbio_cfg1; + /* Specifies the value for EMC_FBIO_DQSIB_DLY */ + uint32_t emc_fbio_dqsib_dly; + /* Specifies the value for EMC_FBIO_DQSIB_DLY_MSB */ + uint32_t emc_fbio_dqsib_dly_msb; + /* Specifies the value for EMC_FBIO_QUSE_DLY */ + uint32_t emc_fbio_quse_dly; + /* Specifies the value for EMC_FBIO_QUSE_DLY_MSB */ + uint32_t emc_fbio_quse_dly_msb; + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + uint32_t emc_fbio_cfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t emc_fbio_spare; + + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t emc_mrs; + /* Specifies the value for EMC_EMRS */ + uint32_t emc_emrs; + /* Specifies the first of a sequence of three values for EMC_MRW */ + uint32_t emc_mrw1; + /* Specifies the second of a sequence of three values for EMC_MRW */ + uint32_t emc_mrw2; + /* Specifies the third of a sequence of three values for EMC_MRW */ + uint32_t emc_mrw3; + + /* Specifies the EMC_MRW reset command value */ + uint32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t emc_mrw_reset_ninit_wait; + + /** + * Specifies the value for EMC_ADR_CFG + * The same value is also used for MC_EMC_ADR_CFG + */ + uint32_t emc_adr_cfg; + /* Specifies the value for EMC_ADR_CFG_1 */ + uint32_t emc_adr_cfg1; + + /** + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + * EMEM_SIZE_KB must be <= (Device size in KB * Number of Devices) + */ + uint32_t mc_emem_cfg; + + /** + * Specifies the value for MC_LOWLATENCY_CONFIG + * Mainly for LL_DRAM_INTERLEAVE: Some DRAMs do not support interleave + * mode. If so, turn off this bit to get the correct low-latency path + * behavior. Reset is ENABLED. + */ + uint32_t mc_lowlatency_config; + /* Specifies the value for EMC_CFG */ + uint32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t emc_cfg2; + /* Specifies the value for EMC_DBG */ + uint32_t emc_dbg; + + /* + * Specifies the value for AHB_ARBITRATION_XBAR_CTRL. + * This is used to set the Memory Inid done + */ + uint32_t ahb_arbitration_xbar_ctrl; + + /* + * Specifies the value for EMC_CFG_DIG_DLL + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t emc_cfg_dig_dll; + /* Specifies the value for EMC_DLL_XFORM_DQS */ + uint32_t emc_dll_xform_dqs; + /* Specifies the value for EMC_DLL_XFORM_QUSE */ + uint32_t emc_dll_xform_quse; + + /* + * Specifies the delay after prgramming the PIN/NOP register during a + * WarmBoot0 sequence (in microseconds) + */ + uint32_t warm_boot_wait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + uint32_t emc_ctt_term_ctrl; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_write; + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_read; + + /* + * Specifies the value for EMC_ZCAL_REF_CNT + * Only meaningful for LPDDR2. Set to 0 for all other memory types. + */ + uint32_t emc_zcal_ref_cnt; + /* + * Specifies the value for EMC_ZCAL_WAIT_CNT + * Only meaningful for LPDDR2. Set to 0 for all other memory types. + */ + uint32_t emc_zcal_wait_cnt; + /* + * Specifies the value for EMC_ZCAL_MRW_CMD + * Only meaningful for LPDDR2. Set to 0 for all other memory types. + */ + uint32_t emc_zcal_mrw_cmd; + + /* + * Specifies the MRS command value for initilizing + * the mode register. + */ + uint32_t emc_mrs_reset_dll; + /* Specifies the MRW command for ZQ initialization of device 0 */ + uint32_t emc_mrw_zq_init_dev0; + /* Specifies the MRW command for ZQ initialization of device 1 */ + uint32_t emc_mrw_zq_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t emc_mrw_zq_init_wait; + /* + * Specifies the wait time after sending an MRS DLL reset command + * (in microseconds) + */ + uint32_t emc_mrs_reset_dll_wait; + /* + * Specifies the first of two EMRS commands to initialize mode + * registers + */ + uint32_t emc_emrs_emr2; + /* + * Specifies the second of two EMRS commands to initialize mode + * registers + */ + uint32_t emc_emrs_emr3; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t emc_ddr2_wait; + + + /* Clock trimmers */ + + /* Specifies the value for EMC_CFG_CLKTRIM_0 */ + uint32_t emc_cfg_clktrim0; + /* Specifies the value for EMC_CFG_CLKTRIM_1 */ + uint32_t emc_cfg_clktrim1; + /* Specifies the value for EMC_CFG_CLKTRIM_2 */ + uint32_t emc_cfg_clktrim2; + + + /* Pad controls */ + + /* Specifies the value for PMC_DDR_PWR */ + uint32_t pmc_ddr_pwr; + /* Specifies the value for APB_MISC_GP_XM2CFGAPADCTRL */ + uint32_t apb_misc_gp_xm2cfga_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL */ + uint32_t apb_misc_gp_xm2cfgc_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL2 */ + uint32_t apb_misc_gp_xm2cfgc_pad_ctrl2; + /* Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL */ + uint32_t apb_misc_gp_xm2cfgd_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL2 */ + uint32_t apb_misc_gp_xm2cfgd_pad_ctrl2; + /* Specifies the value for APB_MISC_GP_XM2CLKCFGPADCTRL */ + uint32_t apb_misc_gp_xm2clkcfg_Pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2COMPPADCTRL */ + uint32_t apb_misc_gp_xm2comp_pad_ctrl; + /* Specifies the value for APB_MISC_GP_XM2VTTGENPADCTRL */ + uint32_t apb_misc_gp_xm2vttgen_pad_ctrl; + + /* + * Specifies storage for arbitration configuration registers + * Data passed through to the Bootloader but not used by + * the Boot ROM + */ + uint32_t arbitration_config[NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS]; +} nvboot_sdram_params; + +#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T20_H */ + diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t20/parse_t20.c b/firmware/coreboot/util/nvidia/cbootimage/src/t20/parse_t20.c new file mode 100644 index 0000000000..503257547b --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t20/parse_t20.c @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * parse_t20.c - Parsing code for t20 + */ + +#include "../parse.h" +#include "nvboot_bct_t20.h" + +enum_item s_devtype_table_t20[] = { + { "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc }, + { "NvBootDevType_Spi", nvboot_dev_type_spi }, + { "NvBootDevType_Nand", nvboot_dev_type_nand }, + { "Sdmmc", nvboot_dev_type_sdmmc }, + { "Spi", nvboot_dev_type_spi }, + { "Nand", nvboot_dev_type_nand }, + + { NULL, 0 } +}; + +enum_item s_sdmmc_data_width_table_t20[] = { + { + "NvBootSdmmcDataWidth_4Bit", + nvboot_sdmmc_data_width_4bit + }, + { + "NvBootSdmmcDataWidth_8Bit", + nvboot_sdmmc_data_width_8bit + }, + { "4Bit", nvboot_sdmmc_data_width_4bit }, + { "8Bit", nvboot_sdmmc_data_width_8bit }, + { NULL, 0 } +}; + +enum_item s_spi_clock_source_table_t20[] = { + { + "NvBootSpiClockSource_PllPOut0", + nvboot_spi_clock_source_pllp_out0 + }, + { + "NvBootSpiClockSource_PllCOut0", + nvboot_spi_clock_source_pllc_out0 + }, + { + "NvBootSpiClockSource_PllMOut0", + nvboot_spi_clock_source_pllm_out0 + }, + { + "NvBootSpiClockSource_ClockM", + nvboot_spi_clock_source_clockm + }, + + { "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockSource_PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "ClockSource_PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockSource_ClockM", nvboot_spi_clock_source_clockm }, + + + { "PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockM", nvboot_spi_clock_source_clockm }, + + { NULL, 0 } +}; + +enum_item s_nvboot_memory_type_table_t20[] = { + { "NvBootMemoryType_None", nvboot_memory_type_none }, + { "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 }, + { "NvBootMemoryType_Ddr", nvboot_memory_type_ddr }, + { "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 }, + { "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr }, + + { "None", nvboot_memory_type_none }, + { "Ddr2", nvboot_memory_type_ddr2 }, + { "Ddr", nvboot_memory_type_ddr }, + { "LpDdr2", nvboot_memory_type_lpddr2 }, + { "LpDdr", nvboot_memory_type_lpddr }, + + { NULL, 0 } +}; + +#define TOKEN(name) \ + token_##name, field_type_u32, NULL + +field_item s_sdram_field_table_t20[] = { + { "MemoryType", token_memory_type, + field_type_enum, s_nvboot_memory_type_table_t20 }, + + { "PllMChargePumpSetupControl", TOKEN(pllm_charge_pump_setup_ctrl) }, + { "PllMLoopFilterSetupControl", TOKEN(pllm_loop_filter_setup_ctrl) }, + { "PllMInputDivider", TOKEN(pllm_input_divider) }, + { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, + { "PllMPostDivider", TOKEN(pllm_post_divider) }, + { "PllMStableTime", TOKEN(pllm_stable_time) }, + { "EmcClockDivider", TOKEN(emc_clock_divider) }, + { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, + { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, + { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, + { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, + { "EmcRc", TOKEN(emc_rc) }, + { "EmcRfc", TOKEN(emc_rfc) }, + { "EmcRas", TOKEN(emc_ras) }, + { "EmcRp", TOKEN(emc_rp) }, + { "EmcR2w", TOKEN(emc_r2w) }, + { "EmcW2r", TOKEN(emc_w2r) }, + { "EmcR2p", TOKEN(emc_r2p) }, + { "EmcW2p", TOKEN(emc_w2p) }, + { "EmcRrd", TOKEN(emc_rrd) }, + { "EmcRdRcd", TOKEN(emc_rd_rcd) }, + { "EmcWrRcd", TOKEN(emc_wr_rcd) }, + { "EmcRext", TOKEN(emc_rext) }, + { "EmcWdv", TOKEN(emc_wdv) }, + { "EmcQUseExtra", TOKEN(emc_quse_extra) }, + { "EmcQUse", TOKEN(emc_quse) }, + { "EmcQRst", TOKEN(emc_qrst) }, + { "EmcQSafe", TOKEN(emc_qsafe) }, + { "EmcRdv", TOKEN(emc_rdv) }, + { "EmcRefresh", TOKEN(emc_refresh) }, + { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, + { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, + { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, + { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, + { "EmcAct2Pden", TOKEN(emc_act2pden) }, + { "EmcAr2Pden", TOKEN(emc_ar2pden) }, + { "EmcRw2Pden", TOKEN(emc_rw2pden) }, + { "EmcTxsr", TOKEN(emc_txsr) }, + { "EmcTcke", TOKEN(emc_tcke) }, + { "EmcTfaw", TOKEN(emc_tfaw) }, + { "EmcTrpab", TOKEN(emc_trpab) }, + { "EmcTClkStable", TOKEN(emc_tclkstable) }, + { "EmcTClkStop", TOKEN(emc_tclkstop) }, + { "EmcTRefBw", TOKEN(emc_trefbw) }, + { "EmcFbioCfg1", TOKEN(emc_fbio_cfg1) }, + { "EmcFbioDqsibDlyMsb", TOKEN(emc_fbio_dqsib_dly_msb) }, + { "EmcFbioDqsibDly", TOKEN(emc_fbio_dqsib_dly) }, + { "EmcFbioQuseDlyMsb", TOKEN(emc_fbio_quse_dly_msb) }, + { "EmcFbioQuseDly", TOKEN(emc_fbio_quse_dly) }, + { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, + { "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) }, + { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, + { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, + { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, + { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, + { "EmcMrs", TOKEN(emc_mrs) }, + { "EmcEmrsEmr2", TOKEN(emc_emrs_emr2) }, + { "EmcEmrsEmr3", TOKEN(emc_emrs_emr3) }, + { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, + { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, + { "EmcEmrs", TOKEN(emc_emrs) }, + { "EmcMrw1", TOKEN(emc_mrw1) }, + { "EmcMrw2", TOKEN(emc_mrw2) }, + { "EmcMrw3", TOKEN(emc_mrw3) }, + { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, + { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, + { "EmcAdrCfg1", TOKEN(emc_adr_cfg1) }, + { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, + { "McEmemCfg", TOKEN(mc_emem_cfg) }, + { "McLowLatencyConfig", TOKEN(mc_lowlatency_config) }, + { "EmcCfg2", TOKEN(emc_cfg2) }, + { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, + { "EmcCfgClktrim0", TOKEN(emc_cfg_clktrim0) }, + { "EmcCfgClktrim1", TOKEN(emc_cfg_clktrim1) }, + { "EmcCfgClktrim2", TOKEN(emc_cfg_clktrim2) }, + { "EmcCfg", TOKEN(emc_cfg) }, + { "EmcDbg", TOKEN(emc_dbg) }, + { "AhbArbitrationXbarCtrl", TOKEN(ahb_arbitration_xbar_ctrl) }, + { "EmcDllXformDqs", TOKEN(emc_dll_xform_dqs) }, + { "EmcDllXformQUse", TOKEN(emc_dll_xform_quse) }, + { "WarmBootWait", TOKEN(warm_boot_wait) }, + { "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) }, + { "EmcOdtWrite", TOKEN(emc_odt_write) }, + { "EmcOdtRead", TOKEN(emc_odt_read) }, + { "EmcZcalRefCnt", TOKEN(emc_zcal_ref_cnt) }, + { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, + { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, + { "EmcMrwZqInitDev0", TOKEN(emc_mrw_zq_init_dev0) }, + { "EmcMrwZqInitDev1", TOKEN(emc_mrw_zq_init_dev1) }, + { "EmcMrwZqInitWait", TOKEN(emc_mrw_zq_init_wait) }, + { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, + { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, + { "ApbMiscGpXm2CfgAPadCtrl", TOKEN(apb_misc_gp_xm2cfga_pad_ctrl) }, + { "ApbMiscGpXm2CfgCPadCtrl2", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl2) }, + { "ApbMiscGpXm2CfgCPadCtrl", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl) }, + { "ApbMiscGpXm2CfgDPadCtrl2", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl2) }, + { "ApbMiscGpXm2CfgDPadCtrl", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl) }, + { "ApbMiscGpXm2ClkCfgPadCtrl", TOKEN(apb_misc_gp_xm2clkcfg_Pad_ctrl)}, + { "ApbMiscGpXm2CompPadCtrl", TOKEN(apb_misc_gp_xm2comp_pad_ctrl) }, + { "ApbMiscGpXm2VttGenPadCtrl", TOKEN(apb_misc_gp_xm2vttgen_pad_ctrl)}, + { NULL, 0, 0, NULL } +}; + +field_item s_nand_table_t20[] = { + { "ClockDivider", TOKEN(nand_clock_divider) }, + /* Note: NandTiming2 must appear before NandTiming, because NandTiming + * is a prefix of NandTiming2 and would otherwise match first. + */ + { "NandTiming2", TOKEN(nand_nand_timing2) }, + { "NandTiming", TOKEN(nand_nand_timing) }, + { "BlockSizeLog2", TOKEN(nand_block_size_log2) }, + { "PageSizeLog2", TOKEN(nand_page_size_log2) }, + { NULL, 0, 0, NULL } +}; + +field_item s_sdmmc_table_t20[] = { + { "ClockDivider", TOKEN(sdmmc_clock_divider) }, + { "DataWidth", + token_sdmmc_data_width, + field_type_enum, + s_sdmmc_data_width_table_t20 }, + { "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) }, + { NULL, 0, 0, NULL } +}; + +field_item s_spiflash_table_t20[] = { + { "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) }, + { "ClockDivider", TOKEN(spiflash_clock_divider) }, + { "ClockSource", + token_spiflash_clock_source, + field_type_enum, + s_spi_clock_source_table_t20 }, + { NULL, 0, 0, NULL } +}; + +parse_subfield_item s_device_type_table_t20[] = { + { "NandParams.", token_nand_params, + s_nand_table_t20, t20_set_dev_param }, + { "SdmmcParams.", token_sdmmc_params, + s_sdmmc_table_t20, t20_set_dev_param }, + { "SpiFlashParams.", token_spiflash_params, + s_spiflash_table_t20, t20_set_dev_param }, + + { NULL, 0, NULL } +}; diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t210/nvbctlib_t210.c b/firmware/coreboot/util/nvidia/cbootimage/src/t210/nvbctlib_t210.c new file mode 100644 index 0000000000..53d5da790f --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t210/nvbctlib_t210.c @@ -0,0 +1,2379 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include "../cbootimage.h" +#include "../parse.h" +#include "../crypto.h" +#include "nvboot_bct_t210.h" +#include "string.h" + +/* nvbctlib_t210.c: The implementation of the nvbctlib API for t210. */ + +/* Definitions that simplify the code which follows. */ +#define CASE_GET_SDRAM_PARAM(x) \ +case token_##x:\ + *value = params->x; \ + break + +#define CASE_SET_SDRAM_PARAM(x) \ +case token_##x:\ + params->x = value; \ + break + +#define CASE_GET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + *value = bct->dev_params[index].dev##_params.x; \ + break + +#define CASE_SET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + bct->dev_params[index].dev##_params.x = value; \ + break + +#define CASE_GET_BL_PARAM(x) \ +case token_bl_##x:\ + *data = bct_ptr->bootloader[set].x; \ + break + +#define CASE_SET_BL_PARAM(x) \ +case token_bl_##x:\ + bct_ptr->bootloader[set].x = *data; \ + break + +#define CASE_GET_NVU32(id) \ +case token_##id:\ + if (bct == NULL) \ + return -ENODATA; \ + *((uint32_t *)data) = bct_ptr->id; \ + break + +#define CASE_GET_CONST(id, val) \ +case token_##id:\ + *((uint32_t *)data) = val; \ + break + +#define CASE_GET_CONST_PREFIX(id, val_prefix) \ +case token_##id:\ + *((uint32_t *)data) = val_prefix##_##id; \ + break + +#define CASE_SET_NVU32(id) \ +case token_##id:\ + bct_ptr->id = *((uint32_t *)data); \ + break + +#define CASE_GET_DATA(id, size) \ +case token_##id:\ + if (*length < size) \ + return -ENODATA;\ + memcpy(data, &(bct_ptr->id), size); \ + *length = size;\ + break + +#define CASE_SET_DATA(id, size) \ +case token_##id:\ + if (length < size) \ + return -ENODATA;\ + memcpy(&(bct_ptr->id), data, size); \ + break + +#define DEFAULT() \ +default : \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +parse_token t210_root_token_list[] = { + token_boot_data_version, + token_block_size, + token_page_size, + token_partition_size, + token_odm_data, + token_bootloader_used, + token_bootloaders_max, + token_bct_size, + token_hash_size, + token_crypto_hash, + token_bl_crypto_hash, + token_crypto_offset, + token_crypto_length, + token_max_bct_search_blks, + token_unique_chip_id, + token_secure_debug_control, + token_rsa_key_modulus, + token_rsa_pss_sig_bl, + token_rsa_pss_sig_bct +}; + +int +t210_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1); + + switch (token) { + CASE_SET_DEV_PARAM(sdmmc, clock_divider); + CASE_SET_DEV_PARAM(sdmmc, data_width); + CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_SET_DEV_PARAM(sdmmc, multi_page_support); + + CASE_SET_DEV_PARAM(spiflash, clock_source); + CASE_SET_DEV_PARAM(spiflash, clock_divider); + CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + CASE_SET_DEV_PARAM(spiflash, page_size_2k_or_16k); + + case token_dev_type: + bct->dev_type[index] = value; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t210_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + switch (token) { + CASE_GET_DEV_PARAM(sdmmc, clock_divider); + CASE_GET_DEV_PARAM(sdmmc, data_width); + CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_GET_DEV_PARAM(sdmmc, multi_page_support); + + CASE_GET_DEV_PARAM(spiflash, clock_source); + CASE_GET_DEV_PARAM(spiflash, clock_divider); + CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); + CASE_GET_DEV_PARAM(spiflash, page_size_2k_or_16k); + + case token_dev_type: + *value = bct->dev_type[index]; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t210_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + + switch (token) { + /* Specifies the type of memory device */ + CASE_GET_SDRAM_PARAM(memory_type); + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + CASE_GET_SDRAM_PARAM(pllm_input_divider); + /* Specifies the N value for PllM */ + CASE_GET_SDRAM_PARAM(pllm_feedback_divider); + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + CASE_GET_SDRAM_PARAM(pllm_stable_time); + /* Specifies misc. control bits */ + CASE_GET_SDRAM_PARAM(pllm_setup_control); + /* Specifies the P value for PLLM */ + CASE_GET_SDRAM_PARAM(pllm_post_divider); + /* Specifies value for Charge Pump Gain Control */ + CASE_GET_SDRAM_PARAM(pllm_kcp); + /* Specifies VCO gain */ + CASE_GET_SDRAM_PARAM(pllm_kvco); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare0); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare1); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare2); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare3); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare4); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare5); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare6); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare7); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare8); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare9); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare10); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare11); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare12); + /* Spare BCT param */ + CASE_GET_SDRAM_PARAM(emc_bct_spare13); + + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + CASE_GET_SDRAM_PARAM(emc_clock_source); + CASE_GET_SDRAM_PARAM(emc_clock_source_dll); + + /* Defines possible override for PLLLM_MISC2 */ + CASE_GET_SDRAM_PARAM(clk_rst_pllm_misc20_override); + /* enables override for PLLLM_MISC2 */ + CASE_GET_SDRAM_PARAM(clk_rst_pllm_misc20_override_enable); + /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ + CASE_GET_SDRAM_PARAM(clear_clock2_mc1); + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + CASE_GET_SDRAM_PARAM(emc_auto_cal_config); + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + CASE_GET_SDRAM_PARAM(emc_auto_cal_config2); + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + CASE_GET_SDRAM_PARAM(emc_auto_cal_config3); + + CASE_GET_SDRAM_PARAM(emc_auto_cal_config4); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config5); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config6); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config7); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config8); + /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ + CASE_GET_SDRAM_PARAM(emc_auto_cal_vref_sel0); + CASE_GET_SDRAM_PARAM(emc_auto_cal_vref_sel1); + + /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ + CASE_GET_SDRAM_PARAM(emc_auto_cal_channel); + + /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ + CASE_GET_SDRAM_PARAM(emc_pmacro_auto_cal_cfg0); + CASE_GET_SDRAM_PARAM(emc_pmacro_auto_cal_cfg1); + CASE_GET_SDRAM_PARAM(emc_pmacro_auto_cal_cfg2); + + CASE_GET_SDRAM_PARAM(emc_pmacro_rx_term); + CASE_GET_SDRAM_PARAM(emc_pmacro_dq_tx_drive); + CASE_GET_SDRAM_PARAM(emc_pmacro_ca_tx_drive); + CASE_GET_SDRAM_PARAM(emc_pmacro_cmd_tx_drive); + CASE_GET_SDRAM_PARAM(emc_pmacro_auto_cal_common); + CASE_GET_SDRAM_PARAM(emc_pmacro_zcrtl); + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); + + CASE_GET_SDRAM_PARAM(emc_xm2_comp_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2_comp_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2_comp_pad_ctrl3); + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + CASE_GET_SDRAM_PARAM(emc_adr_cfg); + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + CASE_GET_SDRAM_PARAM(emc_pin_program_wait); + /* Specifies the extra delay before/after pin RESET/CKE command */ + CASE_GET_SDRAM_PARAM(emc_pin_extra_wait); + + CASE_GET_SDRAM_PARAM(emc_pin_gpio_enable); + CASE_GET_SDRAM_PARAM(emc_pin_gpio); + + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + CASE_GET_SDRAM_PARAM(emc_timing_control_wait); + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + CASE_GET_SDRAM_PARAM(emc_rc); + /* Specifies the value for EMC_RFC */ + CASE_GET_SDRAM_PARAM(emc_rfc); + + CASE_GET_SDRAM_PARAM(emc_rfc_pb); + CASE_GET_SDRAM_PARAM(emc_ref_ctrl2); + + /* Specifies the value for EMC_RFC_SLR */ + CASE_GET_SDRAM_PARAM(emc_rfc_slr); + /* Specifies the value for EMC_RAS */ + CASE_GET_SDRAM_PARAM(emc_ras); + /* Specifies the value for EMC_RP */ + CASE_GET_SDRAM_PARAM(emc_rp); + /* Specifies the value for EMC_R2R */ + CASE_GET_SDRAM_PARAM(emc_r2r); + /* Specifies the value for EMC_W2W */ + CASE_GET_SDRAM_PARAM(emc_w2w); + /* Specifies the value for EMC_R2W */ + CASE_GET_SDRAM_PARAM(emc_r2w); + /* Specifies the value for EMC_W2R */ + CASE_GET_SDRAM_PARAM(emc_w2r); + /* Specifies the value for EMC_R2P */ + CASE_GET_SDRAM_PARAM(emc_r2p); + /* Specifies the value for EMC_W2P */ + CASE_GET_SDRAM_PARAM(emc_w2p); + /* Specifies the value for EMC_RD_RCD */ + + CASE_GET_SDRAM_PARAM(emc_tppd); + CASE_GET_SDRAM_PARAM(emc_ccdmw); + + CASE_GET_SDRAM_PARAM(emc_rd_rcd); + /* Specifies the value for EMC_WR_RCD */ + CASE_GET_SDRAM_PARAM(emc_wr_rcd); + /* Specifies the value for EMC_RRD */ + CASE_GET_SDRAM_PARAM(emc_rrd); + /* Specifies the value for EMC_REXT */ + CASE_GET_SDRAM_PARAM(emc_rext); + /* Specifies the value for EMC_WEXT */ + CASE_GET_SDRAM_PARAM(emc_wext); + /* Specifies the value for EMC_WDV */ + CASE_GET_SDRAM_PARAM(emc_wdv); + + CASE_GET_SDRAM_PARAM(emc_wdv_chk); + CASE_GET_SDRAM_PARAM(emc_wsv); + CASE_GET_SDRAM_PARAM(emc_wev); + + /* Specifies the value for EMC_WDV_MASK */ + CASE_GET_SDRAM_PARAM(emc_wdv_mask); + + CASE_GET_SDRAM_PARAM(emc_ws_duration); + CASE_GET_SDRAM_PARAM(emc_we_duration); + + /* Specifies the value for EMC_QUSE */ + CASE_GET_SDRAM_PARAM(emc_quse); + /* Specifies the value for EMC_QUSE_WIDTH */ + CASE_GET_SDRAM_PARAM(emc_quse_width); + /* Specifies the value for EMC_IBDLY */ + CASE_GET_SDRAM_PARAM(emc_ibdly); + + CASE_GET_SDRAM_PARAM(emc_obdly); + + /* Specifies the value for EMC_EINPUT */ + CASE_GET_SDRAM_PARAM(emc_einput); + /* Specifies the value for EMC_EINPUT_DURATION */ + CASE_GET_SDRAM_PARAM(emc_einput_duration); + /* Specifies the value for EMC_PUTERM_EXTRA */ + CASE_GET_SDRAM_PARAM(emc_puterm_extra); + /* Specifies the value for EMC_PUTERM_WIDTH */ + CASE_GET_SDRAM_PARAM(emc_puterm_width); + + CASE_GET_SDRAM_PARAM(emc_qrst); + CASE_GET_SDRAM_PARAM(emc_qsafe); + CASE_GET_SDRAM_PARAM(emc_rdv); + CASE_GET_SDRAM_PARAM(emc_rdv_mask); + + CASE_GET_SDRAM_PARAM(emc_rdv_early); + CASE_GET_SDRAM_PARAM(emc_rdv_early_mask); + + /* Specifies the value for EMC_QPOP */ + CASE_GET_SDRAM_PARAM(emc_qpop); + + /* Specifies the value for EMC_REFRESH */ + CASE_GET_SDRAM_PARAM(emc_refresh); + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + CASE_GET_SDRAM_PARAM(emc_prerefresh_req_cnt); + /* Specifies the value for EMC_PDEX2WR */ + CASE_GET_SDRAM_PARAM(emc_pdex2wr); + /* Specifies the value for EMC_PDEX2RD */ + CASE_GET_SDRAM_PARAM(emc_pdex2rd); + /* Specifies the value for EMC_PCHG2PDEN */ + CASE_GET_SDRAM_PARAM(emc_pchg2pden); + /* Specifies the value for EMC_ACT2PDEN */ + CASE_GET_SDRAM_PARAM(emc_act2pden); + /* Specifies the value for EMC_AR2PDEN */ + CASE_GET_SDRAM_PARAM(emc_ar2pden); + /* Specifies the value for EMC_RW2PDEN */ + CASE_GET_SDRAM_PARAM(emc_rw2pden); + + CASE_GET_SDRAM_PARAM(emc_cke2pden); + CASE_GET_SDRAM_PARAM(emc_pdex2che); + CASE_GET_SDRAM_PARAM(emc_pdex2mrr); + + /* Specifies the value for EMC_TXSR */ + CASE_GET_SDRAM_PARAM(emc_txsr); + /* Specifies the value for EMC_TXSRDLL */ + CASE_GET_SDRAM_PARAM(emc_txsr_dll); + /* Specifies the value for EMC_TCKE */ + CASE_GET_SDRAM_PARAM(emc_tcke); + /* Specifies the value for EMC_TCKESR */ + CASE_GET_SDRAM_PARAM(emc_tckesr); + /* Specifies the value for EMC_TPD */ + CASE_GET_SDRAM_PARAM(emc_tpd); + /* Specifies the value for EMC_TFAW */ + CASE_GET_SDRAM_PARAM(emc_tfaw); + /* Specifies the value for EMC_TRPAB */ + CASE_GET_SDRAM_PARAM(emc_trpab); + /* Specifies the value for EMC_TCLKSTABLE */ + CASE_GET_SDRAM_PARAM(emc_tclkstable); + /* Specifies the value for EMC_TCLKSTOP */ + CASE_GET_SDRAM_PARAM(emc_tclkstop); + /* Specifies the value for EMC_TREFBW */ + CASE_GET_SDRAM_PARAM(emc_trefbw); + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); + /* Specifies the value for EMC_FBIO_CFG7 */ + CASE_GET_SDRAM_PARAM(emc_fbio_cfg7); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg8); + + /* Command mapping for CMD brick 0 */ + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd0_0); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd0_1); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd0_2); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd1_0); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd1_1); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd1_2); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd2_0); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd2_1); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd2_2); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd3_0); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd3_1); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_cmd3_2); + CASE_GET_SDRAM_PARAM(emc_cmd_mapping_byte); + + /* Specifies the value for EMC_FBIO_SPARE */ + CASE_GET_SDRAM_PARAM(emc_fbio_spare); + + /* Specifies the value for EMC_CFG_RSV */ + CASE_GET_SDRAM_PARAM(emc_cfg_rsv); + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + CASE_GET_SDRAM_PARAM(emc_mrs); + /* Specifies the MP0 command to initialize mode registers */ + CASE_GET_SDRAM_PARAM(emc_emrs); + /* Specifies the MP2 command to initialize mode registers */ + CASE_GET_SDRAM_PARAM(emc_emrs2); + /* Specifies the MP3 command to initialize mode registers */ + CASE_GET_SDRAM_PARAM(emc_emrs3); + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw1); + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw2); + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw3); + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw4); + + /* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw6); + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw8); + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw9); + /* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw10); + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw12); + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw13); + /* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */ + CASE_GET_SDRAM_PARAM(emc_mrw14); + + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + CASE_GET_SDRAM_PARAM(emc_mrw_extra); + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + CASE_GET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + CASE_GET_SDRAM_PARAM(emc_extramode_reg_write_enable); + + /* Specifies the EMC_MRW reset command value */ + CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); + /* Specifies the EMC Reset wait time (in microseconds) */ + CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + /* Specifies the value for EMC_MRS_WAIT_CNT */ + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt); + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt2); + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + CASE_GET_SDRAM_PARAM(emc_cfg); + /* Specifies the value for EMC_CFG_2 */ + CASE_GET_SDRAM_PARAM(emc_cfg2); + /* Specifies the pipe bypass controls */ + CASE_GET_SDRAM_PARAM(emc_cfg_pipe); + + CASE_GET_SDRAM_PARAM(emc_cfg_pipe_clk); + CASE_GET_SDRAM_PARAM(emc_fdpd_ctrl_cmd_no_ramp); + CASE_GET_SDRAM_PARAM(emc_cfg_update); + + /* Specifies the value for EMC_DBG */ + CASE_GET_SDRAM_PARAM(emc_dbg); + + CASE_GET_SDRAM_PARAM(emc_dbg_write_mux); + + /* Specifies the value for EMC_CMDQ */ + CASE_GET_SDRAM_PARAM(emc_cmd_q); + /* Specifies the value for EMC_MC2EMCQ */ + CASE_GET_SDRAM_PARAM(emc_mc2emc_q); + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + CASE_GET_SDRAM_PARAM(emc_dyn_self_ref_control); + + /* Specifies the value for MEM_INIT_DONE */ + CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + + /* Specifies the value for EMC_CFG_DIG_DLL */ + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_1); + + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period); + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + CASE_GET_SDRAM_PARAM(emc_dev_select); + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + CASE_GET_SDRAM_PARAM(emc_sel_dpd_ctrl); + + /* Pads trimmer delays */ + CASE_GET_SDRAM_PARAM(emc_fdpd_ctrl_dq); + CASE_GET_SDRAM_PARAM(emc_fdpd_ctrl_cmd); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_vref_dq_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_vref_dq_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_vref_dqs_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_vref_dqs_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_rxrt); + CASE_GET_SDRAM_PARAM(emc_cfg_pipe1); + CASE_GET_SDRAM_PARAM(emc_cfg_pipe2); + + /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_2); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_3); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_4); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_5); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_2); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_3); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_4); + CASE_GET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_5); + + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_2); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_3); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_4); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_5); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_2); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_3); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_4); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_5); + + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_2); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_3); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_4); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_5); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_2); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_3); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_4); + CASE_GET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_5); + + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank0_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank0_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank0_2); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank0_3); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank1_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank1_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank1_2); + CASE_GET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank1_3); + + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_2); + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_3); + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_4); + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_short_cmd_0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_short_cmd_1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_short_cmd_2); + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + CASE_GET_SDRAM_PARAM(warm_boot_wait); + + /* Specifies the value for EMC_ODT_WRITE */ + CASE_GET_SDRAM_PARAM(emc_odt_write); + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + CASE_GET_SDRAM_PARAM(emc_zcal_interval); + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); + /* Specifies the command for ZQ initialization of device 0 */ + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev0); + /* Specifies the command for ZQ initialization of device 1 */ + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev1); + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + CASE_GET_SDRAM_PARAM(emc_zcal_init_wait); + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + CASE_GET_SDRAM_PARAM(emc_zcal_warm_cold_boot_enables); + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + CASE_GET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + CASE_GET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + + CASE_GET_SDRAM_PARAM(emc_zqcal_lpddr4_warm_boot); + + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + CASE_GET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + CASE_GET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + /* Specifies the extra MRS command to initialize mode registers */ + CASE_GET_SDRAM_PARAM(emc_mrs_extra); + /* Specifies the extra MRS command at warm boot */ + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + /* Specifies the EMRS command to enable the DDR2 DLL */ + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + /* Specifies the MRS command to reset the DDR2 DLL */ + CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + /* Specifies the EMRS command to set OCD calibration */ + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + CASE_GET_SDRAM_PARAM(emc_ddr2_wait); + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + CASE_GET_SDRAM_PARAM(emc_clken_override); + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + CASE_GET_SDRAM_PARAM(emc_extra_refresh_num); + /* Specifies the master override for all EMC clocks */ + CASE_GET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + /* Specifies the master override for all MC clocks */ + CASE_GET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + /* Specifies digital dll period, choosing between 4 to 64 ms */ + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + CASE_GET_SDRAM_PARAM(pmc_vddp_sel); + /* Specifies the wait time after programming PMC_VDDP_SEL */ + CASE_GET_SDRAM_PARAM(pmc_vddp_sel_wait); + /* Specifies the value for PMC_DDR_PWR */ + CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); + /* Specifies the value for PMC_DDR_CFG */ + CASE_GET_SDRAM_PARAM(pmc_ddr_cfg); + /* Specifies the value for PMC_IO_DPD3_REQ */ + CASE_GET_SDRAM_PARAM(pmc_io_dpd3_req); + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + CASE_GET_SDRAM_PARAM(pmc_io_dpd3_req_wait); + + CASE_GET_SDRAM_PARAM(pmc_io_dpd4_req_wait); + + /* Specifies the value for PMC_REG_SHORT */ + CASE_GET_SDRAM_PARAM(pmc_reg_short); + /* Specifies the value for PMC_NO_IOPOWER */ + CASE_GET_SDRAM_PARAM(pmc_no_io_power); + + CASE_GET_SDRAM_PARAM(pmc_ddr_ctrl_wait); + CASE_GET_SDRAM_PARAM(pmc_ddr_ctrl); + + /* Specifies the value for EMC_ACPD_CONTROL */ + CASE_GET_SDRAM_PARAM(emc_acpd_control); + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte0); + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte1); + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte2); + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + CASE_GET_SDRAM_PARAM(emc_swizzle_rank0_byte3); + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte0); + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte1); + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte2); + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + CASE_GET_SDRAM_PARAM(emc_swizzle_rank1_byte3); + + /* Specifies the value for EMC_TXDSRVTTGEN */ + CASE_GET_SDRAM_PARAM(emc_txdsrvttgen); + + /* Specifies the value for EMC_DATA_BRLSHFT_0 */ + CASE_GET_SDRAM_PARAM(emc_data_brlshft0); + CASE_GET_SDRAM_PARAM(emc_data_brlshft1); + + CASE_GET_SDRAM_PARAM(emc_dqs_brlshft0); + CASE_GET_SDRAM_PARAM(emc_dqs_brlshft1); + + CASE_GET_SDRAM_PARAM(emc_cmd_brlshft0); + CASE_GET_SDRAM_PARAM(emc_cmd_brlshft1); + CASE_GET_SDRAM_PARAM(emc_cmd_brlshft2); + CASE_GET_SDRAM_PARAM(emc_cmd_brlshft3); + + CASE_GET_SDRAM_PARAM(emc_quse_brlshft0); + CASE_GET_SDRAM_PARAM(emc_quse_brlshft1); + CASE_GET_SDRAM_PARAM(emc_quse_brlshft2); + CASE_GET_SDRAM_PARAM(emc_quse_brlshft3); + + CASE_GET_SDRAM_PARAM(emc_dll_cfg0); + CASE_GET_SDRAM_PARAM(emc_dll_cfg1); + + CASE_GET_SDRAM_PARAM(emc_pmc_scratch1); + CASE_GET_SDRAM_PARAM(emc_pmc_scratch2); + CASE_GET_SDRAM_PARAM(emc_pmc_scratch3); + + CASE_GET_SDRAM_PARAM(emc_pmacro_pad_cfg_ctrl); + + CASE_GET_SDRAM_PARAM(emc_pmacro_vttgen_ctrl0); + CASE_GET_SDRAM_PARAM(emc_pmacro_vttgen_ctrl1); + CASE_GET_SDRAM_PARAM(emc_pmacro_vttgen_ctrl2); + + CASE_GET_SDRAM_PARAM(emc_pmacro_brick_ctrl_rfu1); + CASE_GET_SDRAM_PARAM(emc_pmacro_cmd_brick_ctrl_fdpd); + CASE_GET_SDRAM_PARAM(emc_pmacro_brick_ctrl_rfu2); + CASE_GET_SDRAM_PARAM(emc_pmacro_data_brick_ctrl_fdpd); + CASE_GET_SDRAM_PARAM(emc_pmacro_bg_bias_ctrl0); + CASE_GET_SDRAM_PARAM(emc_pmacro_data_pad_rx_ctrl); + CASE_GET_SDRAM_PARAM(emc_pmacro_cmd_pad_rx_ctrl); + CASE_GET_SDRAM_PARAM(emc_pmacro_data_rx_term_mode); + CASE_GET_SDRAM_PARAM(emc_pmacro_cmd_rx_term_mode); + CASE_GET_SDRAM_PARAM(emc_pmacro_data_pad_tx_ctrl); + CASE_GET_SDRAM_PARAM(emc_pmacro_common_pad_tx_ctrl); + CASE_GET_SDRAM_PARAM(emc_pmacro_cmd_pad_tx_ctrl); + CASE_GET_SDRAM_PARAM(emc_cfg3); + + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_pwrd0); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_pwrd1); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_pwrd2); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_pwrd3); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_pwrd4); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_pwrd5); + + CASE_GET_SDRAM_PARAM(emc_config_sample_delay); + + CASE_GET_SDRAM_PARAM(emc_pmacro_brick_mapping0); + CASE_GET_SDRAM_PARAM(emc_pmacro_brick_mapping1); + CASE_GET_SDRAM_PARAM(emc_pmacro_brick_mapping2); + + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src0); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src1); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src2); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src3); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src4); + CASE_GET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src5); + + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_bypass); + + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_pwrd0); + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_pwrd1); + CASE_GET_SDRAM_PARAM(emc_pmacro_ddll_pwrd2); + + CASE_GET_SDRAM_PARAM(emc_pmacro_cmd_ctrl0); + CASE_GET_SDRAM_PARAM(emc_pmacro_cmd_ctrl1); + CASE_GET_SDRAM_PARAM(emc_pmacro_cmd_ctrl2); + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg); + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_channel_mask); + + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask0); + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask1); + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask2); + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + CASE_GET_SDRAM_PARAM(mc_emem_cfg); + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_cfg); + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + + CASE_GET_SDRAM_PARAM(emc_emem_arb_refpb_hp_ctrl); + CASE_GET_SDRAM_PARAM(emc_emem_arb_refpb_bank_ctrl); + + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rp); + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rc); + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_ras); + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_faw); + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rfcpb); + + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_turns); + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_covers); + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc0); + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc2); + + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_override); + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_override1); + /* Specifies the value for MC_EMEM_ARB_RSV */ + CASE_GET_SDRAM_PARAM(mc_emem_arb_rsv); + + CASE_GET_SDRAM_PARAM(mc_da_cfg0); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_ccdmw); + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + CASE_GET_SDRAM_PARAM(mc_clken_override); + + /* Specifies the value for MC_STAT_CONTROL */ + CASE_GET_SDRAM_PARAM(mc_stat_control); + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + CASE_GET_SDRAM_PARAM(mc_video_protect_bom); + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + CASE_GET_SDRAM_PARAM(mc_video_protect_bom_adr_hi); + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + CASE_GET_SDRAM_PARAM(mc_video_protect_size_mb); + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + CASE_GET_SDRAM_PARAM(mc_video_protect_vpr_override); + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + CASE_GET_SDRAM_PARAM(mc_video_protect_vpr_override1); + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + CASE_GET_SDRAM_PARAM(mc_video_protect_gpu_override0); + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + CASE_GET_SDRAM_PARAM(mc_video_protect_gpu_override1); + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + CASE_GET_SDRAM_PARAM(mc_sec_carveout_bom); + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + CASE_GET_SDRAM_PARAM(mc_sec_carveout_adr_hi); + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + CASE_GET_SDRAM_PARAM(mc_sec_carveout_size_mb); + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ + CASE_GET_SDRAM_PARAM(mc_video_protect_write_access); + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ + CASE_GET_SDRAM_PARAM(mc_sec_carveout_protect_write_access); + + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_bom); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_bom_hi); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_size_128kb); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout1_cfg0); + + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_bom); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_bom_hi); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_size_128kb); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout2_cfg0); + + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_bom); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_bom_hi); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_size_128kb); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout3_cfg0); + + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_bom); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_bom_hi); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_size_128kb); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout4_cfg0); + + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_bom); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_bom_hi); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_size_128kb); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access0); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access1); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access2); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access3); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access4); + CASE_GET_SDRAM_PARAM(mc_generalized_carveout5_cfg0); + + /* Specifies enable for CA training */ + CASE_GET_SDRAM_PARAM(emc_ca_training_enable); + /* Set if bit 6 select is greater than bit 7 select); uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ + CASE_GET_SDRAM_PARAM(swizzle_rank_byte_encode); + /* Specifies enable and offset for patched boot rom write */ + CASE_GET_SDRAM_PARAM(boot_rom_patch_control); + /* Specifies data for patched boot rom write */ + CASE_GET_SDRAM_PARAM(boot_rom_patch_data); + + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + CASE_GET_SDRAM_PARAM(mc_mts_carveout_bom); + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + CASE_GET_SDRAM_PARAM(mc_mts_carveout_adr_hi); + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + CASE_GET_SDRAM_PARAM(mc_mts_carveout_size_mb); + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + CASE_GET_SDRAM_PARAM(mc_mts_carveout_reg_ctrl); + DEFAULT(); + } + return 0; +} + +int +t210_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + /* Update the number of SDRAM parameter sets. */ + bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1); + + switch (token) { + /* Specifies the type of memory device */ + CASE_SET_SDRAM_PARAM(memory_type); + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + CASE_SET_SDRAM_PARAM(pllm_input_divider); + /* Specifies the N value for PllM */ + CASE_SET_SDRAM_PARAM(pllm_feedback_divider); + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + CASE_SET_SDRAM_PARAM(pllm_stable_time); + /* Specifies misc. control bits */ + CASE_SET_SDRAM_PARAM(pllm_setup_control); + /* Specifies the P value for PLLM */ + CASE_SET_SDRAM_PARAM(pllm_post_divider); + /* Specifies value for Charge Pump Gain Control */ + CASE_SET_SDRAM_PARAM(pllm_kcp); + /* Specifies VCO gain */ + CASE_SET_SDRAM_PARAM(pllm_kvco); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare0); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare1); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare2); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare3); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare4); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare5); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare6); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare7); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare8); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare9); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare10); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare11); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare12); + /* Spare BCT param */ + CASE_SET_SDRAM_PARAM(emc_bct_spare13); + + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + CASE_SET_SDRAM_PARAM(emc_clock_source); + CASE_SET_SDRAM_PARAM(emc_clock_source_dll); + + /* Defines possible override for PLLLM_MISC2 */ + CASE_SET_SDRAM_PARAM(clk_rst_pllm_misc20_override); + /* enables override for PLLLM_MISC2 */ + CASE_SET_SDRAM_PARAM(clk_rst_pllm_misc20_override_enable); + /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ + CASE_SET_SDRAM_PARAM(clear_clock2_mc1); + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + CASE_SET_SDRAM_PARAM(emc_auto_cal_config); + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + CASE_SET_SDRAM_PARAM(emc_auto_cal_config2); + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + CASE_SET_SDRAM_PARAM(emc_auto_cal_config3); + + CASE_SET_SDRAM_PARAM(emc_auto_cal_config4); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config5); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config6); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config7); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config8); + /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ + CASE_SET_SDRAM_PARAM(emc_auto_cal_vref_sel0); + CASE_SET_SDRAM_PARAM(emc_auto_cal_vref_sel1); + + /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ + CASE_SET_SDRAM_PARAM(emc_auto_cal_channel); + + /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ + CASE_SET_SDRAM_PARAM(emc_pmacro_auto_cal_cfg0); + CASE_SET_SDRAM_PARAM(emc_pmacro_auto_cal_cfg1); + CASE_SET_SDRAM_PARAM(emc_pmacro_auto_cal_cfg2); + + CASE_SET_SDRAM_PARAM(emc_pmacro_rx_term); + CASE_SET_SDRAM_PARAM(emc_pmacro_dq_tx_drive); + CASE_SET_SDRAM_PARAM(emc_pmacro_ca_tx_drive); + CASE_SET_SDRAM_PARAM(emc_pmacro_cmd_tx_drive); + CASE_SET_SDRAM_PARAM(emc_pmacro_auto_cal_common); + CASE_SET_SDRAM_PARAM(emc_pmacro_zcrtl); + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); + + CASE_SET_SDRAM_PARAM(emc_xm2_comp_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2_comp_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2_comp_pad_ctrl3); + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + CASE_SET_SDRAM_PARAM(emc_adr_cfg); + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + CASE_SET_SDRAM_PARAM(emc_pin_program_wait); + /* Specifies the extra delay before/after pin RESET/CKE command */ + CASE_SET_SDRAM_PARAM(emc_pin_extra_wait); + + CASE_SET_SDRAM_PARAM(emc_pin_gpio_enable); + CASE_SET_SDRAM_PARAM(emc_pin_gpio); + + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + CASE_SET_SDRAM_PARAM(emc_timing_control_wait); + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + CASE_SET_SDRAM_PARAM(emc_rc); + /* Specifies the value for EMC_RFC */ + CASE_SET_SDRAM_PARAM(emc_rfc); + + CASE_SET_SDRAM_PARAM(emc_rfc_pb); + CASE_SET_SDRAM_PARAM(emc_ref_ctrl2); + + /* Specifies the value for EMC_RFC_SLR */ + CASE_SET_SDRAM_PARAM(emc_rfc_slr); + /* Specifies the value for EMC_RAS */ + CASE_SET_SDRAM_PARAM(emc_ras); + /* Specifies the value for EMC_RP */ + CASE_SET_SDRAM_PARAM(emc_rp); + /* Specifies the value for EMC_R2R */ + CASE_SET_SDRAM_PARAM(emc_r2r); + /* Specifies the value for EMC_W2W */ + CASE_SET_SDRAM_PARAM(emc_w2w); + /* Specifies the value for EMC_R2W */ + CASE_SET_SDRAM_PARAM(emc_r2w); + /* Specifies the value for EMC_W2R */ + CASE_SET_SDRAM_PARAM(emc_w2r); + /* Specifies the value for EMC_R2P */ + CASE_SET_SDRAM_PARAM(emc_r2p); + /* Specifies the value for EMC_W2P */ + CASE_SET_SDRAM_PARAM(emc_w2p); + /* Specifies the value for EMC_RD_RCD */ + + CASE_SET_SDRAM_PARAM(emc_tppd); + CASE_SET_SDRAM_PARAM(emc_ccdmw); + + CASE_SET_SDRAM_PARAM(emc_rd_rcd); + /* Specifies the value for EMC_WR_RCD */ + CASE_SET_SDRAM_PARAM(emc_wr_rcd); + /* Specifies the value for EMC_RRD */ + CASE_SET_SDRAM_PARAM(emc_rrd); + /* Specifies the value for EMC_REXT */ + CASE_SET_SDRAM_PARAM(emc_rext); + /* Specifies the value for EMC_WEXT */ + CASE_SET_SDRAM_PARAM(emc_wext); + /* Specifies the value for EMC_WDV */ + CASE_SET_SDRAM_PARAM(emc_wdv); + + CASE_SET_SDRAM_PARAM(emc_wdv_chk); + CASE_SET_SDRAM_PARAM(emc_wsv); + CASE_SET_SDRAM_PARAM(emc_wev); + + /* Specifies the value for EMC_WDV_MASK */ + CASE_SET_SDRAM_PARAM(emc_wdv_mask); + + CASE_SET_SDRAM_PARAM(emc_ws_duration); + CASE_SET_SDRAM_PARAM(emc_we_duration); + + /* Specifies the value for EMC_QUSE */ + CASE_SET_SDRAM_PARAM(emc_quse); + /* Specifies the value for EMC_QUSE_WIDTH */ + CASE_SET_SDRAM_PARAM(emc_quse_width); + /* Specifies the value for EMC_IBDLY */ + CASE_SET_SDRAM_PARAM(emc_ibdly); + + CASE_SET_SDRAM_PARAM(emc_obdly); + + /* Specifies the value for EMC_EINPUT */ + CASE_SET_SDRAM_PARAM(emc_einput); + /* Specifies the value for EMC_EINPUT_DURATION */ + CASE_SET_SDRAM_PARAM(emc_einput_duration); + /* Specifies the value for EMC_PUTERM_EXTRA */ + CASE_SET_SDRAM_PARAM(emc_puterm_extra); + /* Specifies the value for EMC_PUTERM_WIDTH */ + CASE_SET_SDRAM_PARAM(emc_puterm_width); + + CASE_SET_SDRAM_PARAM(emc_qrst); + CASE_SET_SDRAM_PARAM(emc_qsafe); + CASE_SET_SDRAM_PARAM(emc_rdv); + CASE_SET_SDRAM_PARAM(emc_rdv_mask); + + CASE_SET_SDRAM_PARAM(emc_rdv_early); + CASE_SET_SDRAM_PARAM(emc_rdv_early_mask); + + /* Specifies the value for EMC_QPOP */ + CASE_SET_SDRAM_PARAM(emc_qpop); + + /* Specifies the value for EMC_REFRESH */ + CASE_SET_SDRAM_PARAM(emc_refresh); + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + CASE_SET_SDRAM_PARAM(emc_burst_refresh_num); + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + CASE_SET_SDRAM_PARAM(emc_prerefresh_req_cnt); + /* Specifies the value for EMC_PDEX2WR */ + CASE_SET_SDRAM_PARAM(emc_pdex2wr); + /* Specifies the value for EMC_PDEX2RD */ + CASE_SET_SDRAM_PARAM(emc_pdex2rd); + /* Specifies the value for EMC_PCHG2PDEN */ + CASE_SET_SDRAM_PARAM(emc_pchg2pden); + /* Specifies the value for EMC_ACT2PDEN */ + CASE_SET_SDRAM_PARAM(emc_act2pden); + /* Specifies the value for EMC_AR2PDEN */ + CASE_SET_SDRAM_PARAM(emc_ar2pden); + /* Specifies the value for EMC_RW2PDEN */ + CASE_SET_SDRAM_PARAM(emc_rw2pden); + + CASE_SET_SDRAM_PARAM(emc_cke2pden); + CASE_SET_SDRAM_PARAM(emc_pdex2che); + CASE_SET_SDRAM_PARAM(emc_pdex2mrr); + + /* Specifies the value for EMC_TXSR */ + CASE_SET_SDRAM_PARAM(emc_txsr); + /* Specifies the value for EMC_TXSRDLL */ + CASE_SET_SDRAM_PARAM(emc_txsr_dll); + /* Specifies the value for EMC_TCKE */ + CASE_SET_SDRAM_PARAM(emc_tcke); + /* Specifies the value for EMC_TCKESR */ + CASE_SET_SDRAM_PARAM(emc_tckesr); + /* Specifies the value for EMC_TPD */ + CASE_SET_SDRAM_PARAM(emc_tpd); + /* Specifies the value for EMC_TFAW */ + CASE_SET_SDRAM_PARAM(emc_tfaw); + /* Specifies the value for EMC_TRPAB */ + CASE_SET_SDRAM_PARAM(emc_trpab); + /* Specifies the value for EMC_TCLKSTABLE */ + CASE_SET_SDRAM_PARAM(emc_tclkstable); + /* Specifies the value for EMC_TCLKSTOP */ + CASE_SET_SDRAM_PARAM(emc_tclkstop); + /* Specifies the value for EMC_TREFBW */ + CASE_SET_SDRAM_PARAM(emc_trefbw); + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + CASE_SET_SDRAM_PARAM(emc_fbio_cfg5); + /* Specifies the value for EMC_FBIO_CFG7 */ + CASE_SET_SDRAM_PARAM(emc_fbio_cfg7); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg8); + + /* Command mapping for CMD brick 0 */ + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd0_0); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd0_1); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd0_2); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd1_0); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd1_1); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd1_2); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd2_0); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd2_1); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd2_2); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd3_0); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd3_1); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_cmd3_2); + CASE_SET_SDRAM_PARAM(emc_cmd_mapping_byte); + + /* Specifies the value for EMC_FBIO_SPARE */ + CASE_SET_SDRAM_PARAM(emc_fbio_spare); + + /* Specifies the value for EMC_CFG_RSV */ + CASE_SET_SDRAM_PARAM(emc_cfg_rsv); + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + CASE_SET_SDRAM_PARAM(emc_mrs); + /* Specifies the MP0 command to initialize mode registers */ + CASE_SET_SDRAM_PARAM(emc_emrs); + /* Specifies the MP2 command to initialize mode registers */ + CASE_SET_SDRAM_PARAM(emc_emrs2); + /* Specifies the MP3 command to initialize mode registers */ + CASE_SET_SDRAM_PARAM(emc_emrs3); + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw1); + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw2); + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw3); + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw4); + + /* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw6); + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw8); + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw9); + /* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw10); + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw12); + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw13); + /* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */ + CASE_SET_SDRAM_PARAM(emc_mrw14); + + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + CASE_SET_SDRAM_PARAM(emc_mrw_extra); + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + CASE_SET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + CASE_SET_SDRAM_PARAM(emc_extramode_reg_write_enable); + + /* Specifies the EMC_MRW reset command value */ + CASE_SET_SDRAM_PARAM(emc_mrw_reset_command); + /* Specifies the EMC Reset wait time (in microseconds) */ + CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + /* Specifies the value for EMC_MRS_WAIT_CNT */ + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt); + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt2); + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + CASE_SET_SDRAM_PARAM(emc_cfg); + /* Specifies the value for EMC_CFG_2 */ + CASE_SET_SDRAM_PARAM(emc_cfg2); + /* Specifies the pipe bypass controls */ + CASE_SET_SDRAM_PARAM(emc_cfg_pipe); + + CASE_SET_SDRAM_PARAM(emc_cfg_pipe_clk); + CASE_SET_SDRAM_PARAM(emc_fdpd_ctrl_cmd_no_ramp); + CASE_SET_SDRAM_PARAM(emc_cfg_update); + + /* Specifies the value for EMC_DBG */ + CASE_SET_SDRAM_PARAM(emc_dbg); + + CASE_SET_SDRAM_PARAM(emc_dbg_write_mux); + + /* Specifies the value for EMC_CMDQ */ + CASE_SET_SDRAM_PARAM(emc_cmd_q); + /* Specifies the value for EMC_MC2EMCQ */ + CASE_SET_SDRAM_PARAM(emc_mc2emc_q); + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + CASE_SET_SDRAM_PARAM(emc_dyn_self_ref_control); + + /* Specifies the value for MEM_INIT_DONE */ + CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + + /* Specifies the value for EMC_CFG_DIG_DLL */ + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_1); + + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period); + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + CASE_SET_SDRAM_PARAM(emc_dev_select); + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + CASE_SET_SDRAM_PARAM(emc_sel_dpd_ctrl); + + /* Pads trimmer delays */ + CASE_SET_SDRAM_PARAM(emc_fdpd_ctrl_dq); + CASE_SET_SDRAM_PARAM(emc_fdpd_ctrl_cmd); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_vref_dq_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_vref_dq_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_vref_dqs_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_vref_dqs_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_rxrt); + CASE_SET_SDRAM_PARAM(emc_cfg_pipe1); + CASE_SET_SDRAM_PARAM(emc_cfg_pipe2); + + /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_2); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_3); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_4); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank0_5); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_2); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_3); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_4); + CASE_SET_SDRAM_PARAM(emc_pmacro_quse_ddll_rank1_5); + + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_2); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_3); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_4); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank0_5); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_2); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_3); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_4); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dq_rank1_5); + + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_2); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_3); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_4); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank0_5); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_2); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_3); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_4); + CASE_SET_SDRAM_PARAM(emc_pmacro_ob_ddll_long_dqs_rank1_5); + + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank0_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank0_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank0_2); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank0_3); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank1_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank1_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank1_2); + CASE_SET_SDRAM_PARAM(emc_pmacro_ib_ddll_long_dqs_rank1_3); + + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_2); + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_3); + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_long_cmd_4); + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_short_cmd_0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_short_cmd_1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_short_cmd_2); + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + CASE_SET_SDRAM_PARAM(warm_boot_wait); + + /* Specifies the value for EMC_ODT_WRITE */ + CASE_SET_SDRAM_PARAM(emc_odt_write); + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + CASE_SET_SDRAM_PARAM(emc_zcal_interval); + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt); + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd); + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll); + /* Specifies the command for ZQ initialization of device 0 */ + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev0); + /* Specifies the command for ZQ initialization of device 1 */ + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev1); + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + CASE_SET_SDRAM_PARAM(emc_zcal_init_wait); + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + CASE_SET_SDRAM_PARAM(emc_zcal_warm_cold_boot_enables); + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + CASE_SET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + CASE_SET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + + CASE_SET_SDRAM_PARAM(emc_zqcal_lpddr4_warm_boot); + + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + CASE_SET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + /* Specifies the extra MRS command to initialize mode registers */ + CASE_SET_SDRAM_PARAM(emc_mrs_extra); + /* Specifies the extra MRS command at warm boot */ + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + /* Specifies the EMRS command to enable the DDR2 DLL */ + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + /* Specifies the MRS command to reset the DDR2 DLL */ + CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + /* Specifies the EMRS command to set OCD calibration */ + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + CASE_SET_SDRAM_PARAM(emc_ddr2_wait); + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + CASE_SET_SDRAM_PARAM(emc_clken_override); + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + CASE_SET_SDRAM_PARAM(emc_extra_refresh_num); + /* Specifies the master override for all EMC clocks */ + CASE_SET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + /* Specifies the master override for all MC clocks */ + CASE_SET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + /* Specifies digital dll period, choosing between 4 to 64 ms */ + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + CASE_SET_SDRAM_PARAM(pmc_vddp_sel); + /* Specifies the wait time after programming PMC_VDDP_SEL */ + CASE_SET_SDRAM_PARAM(pmc_vddp_sel_wait); + /* Specifies the value for PMC_DDR_PWR */ + CASE_SET_SDRAM_PARAM(pmc_ddr_pwr); + /* Specifies the value for PMC_DDR_CFG */ + CASE_SET_SDRAM_PARAM(pmc_ddr_cfg); + /* Specifies the value for PMC_IO_DPD3_REQ */ + CASE_SET_SDRAM_PARAM(pmc_io_dpd3_req); + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + CASE_SET_SDRAM_PARAM(pmc_io_dpd3_req_wait); + + CASE_SET_SDRAM_PARAM(pmc_io_dpd4_req_wait); + + /* Specifies the value for PMC_REG_SHORT */ + CASE_SET_SDRAM_PARAM(pmc_reg_short); + /* Specifies the value for PMC_NO_IOPOWER */ + CASE_SET_SDRAM_PARAM(pmc_no_io_power); + + CASE_SET_SDRAM_PARAM(pmc_ddr_ctrl_wait); + CASE_SET_SDRAM_PARAM(pmc_ddr_ctrl); + + /* Specifies the value for EMC_ACPD_CONTROL */ + CASE_SET_SDRAM_PARAM(emc_acpd_control); + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte0); + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte1); + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte2); + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte3); + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte0); + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte1); + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte2); + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte3); + + /* Specifies the value for EMC_TXDSRVTTGEN */ + CASE_SET_SDRAM_PARAM(emc_txdsrvttgen); + + /* Specifies the value for EMC_DATA_BRLSHFT_0 */ + CASE_SET_SDRAM_PARAM(emc_data_brlshft0); + CASE_SET_SDRAM_PARAM(emc_data_brlshft1); + + CASE_SET_SDRAM_PARAM(emc_dqs_brlshft0); + CASE_SET_SDRAM_PARAM(emc_dqs_brlshft1); + + CASE_SET_SDRAM_PARAM(emc_cmd_brlshft0); + CASE_SET_SDRAM_PARAM(emc_cmd_brlshft1); + CASE_SET_SDRAM_PARAM(emc_cmd_brlshft2); + CASE_SET_SDRAM_PARAM(emc_cmd_brlshft3); + + CASE_SET_SDRAM_PARAM(emc_quse_brlshft0); + CASE_SET_SDRAM_PARAM(emc_quse_brlshft1); + CASE_SET_SDRAM_PARAM(emc_quse_brlshft2); + CASE_SET_SDRAM_PARAM(emc_quse_brlshft3); + + CASE_SET_SDRAM_PARAM(emc_dll_cfg0); + CASE_SET_SDRAM_PARAM(emc_dll_cfg1); + + CASE_SET_SDRAM_PARAM(emc_pmc_scratch1); + CASE_SET_SDRAM_PARAM(emc_pmc_scratch2); + CASE_SET_SDRAM_PARAM(emc_pmc_scratch3); + + CASE_SET_SDRAM_PARAM(emc_pmacro_pad_cfg_ctrl); + + CASE_SET_SDRAM_PARAM(emc_pmacro_vttgen_ctrl0); + CASE_SET_SDRAM_PARAM(emc_pmacro_vttgen_ctrl1); + CASE_SET_SDRAM_PARAM(emc_pmacro_vttgen_ctrl2); + + CASE_SET_SDRAM_PARAM(emc_pmacro_brick_ctrl_rfu1); + CASE_SET_SDRAM_PARAM(emc_pmacro_cmd_brick_ctrl_fdpd); + CASE_SET_SDRAM_PARAM(emc_pmacro_brick_ctrl_rfu2); + CASE_SET_SDRAM_PARAM(emc_pmacro_data_brick_ctrl_fdpd); + CASE_SET_SDRAM_PARAM(emc_pmacro_bg_bias_ctrl0); + CASE_SET_SDRAM_PARAM(emc_pmacro_data_pad_rx_ctrl); + CASE_SET_SDRAM_PARAM(emc_pmacro_cmd_pad_rx_ctrl); + CASE_SET_SDRAM_PARAM(emc_pmacro_data_rx_term_mode); + CASE_SET_SDRAM_PARAM(emc_pmacro_cmd_rx_term_mode); + CASE_SET_SDRAM_PARAM(emc_pmacro_data_pad_tx_ctrl); + CASE_SET_SDRAM_PARAM(emc_pmacro_common_pad_tx_ctrl); + CASE_SET_SDRAM_PARAM(emc_pmacro_cmd_pad_tx_ctrl); + CASE_SET_SDRAM_PARAM(emc_cfg3); + + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_pwrd0); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_pwrd1); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_pwrd2); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_pwrd3); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_pwrd4); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_pwrd5); + + CASE_SET_SDRAM_PARAM(emc_config_sample_delay); + + CASE_SET_SDRAM_PARAM(emc_pmacro_brick_mapping0); + CASE_SET_SDRAM_PARAM(emc_pmacro_brick_mapping1); + CASE_SET_SDRAM_PARAM(emc_pmacro_brick_mapping2); + + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src0); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src1); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src2); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src3); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src4); + CASE_SET_SDRAM_PARAM(emc_pmacro_tx_sel_clk_src5); + + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_bypass); + + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_pwrd0); + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_pwrd1); + CASE_SET_SDRAM_PARAM(emc_pmacro_ddll_pwrd2); + + CASE_SET_SDRAM_PARAM(emc_pmacro_cmd_ctrl0); + CASE_SET_SDRAM_PARAM(emc_pmacro_cmd_ctrl1); + CASE_SET_SDRAM_PARAM(emc_pmacro_cmd_ctrl2); + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg); + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_channel_mask); + + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask0); + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask1); + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask2); + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + CASE_SET_SDRAM_PARAM(mc_emem_cfg); + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_cfg); + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + + CASE_SET_SDRAM_PARAM(emc_emem_arb_refpb_hp_ctrl); + CASE_SET_SDRAM_PARAM(emc_emem_arb_refpb_bank_ctrl); + + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rp); + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rc); + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_ras); + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_faw); + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rfcpb); + + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_turns); + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_covers); + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc0); + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc2); + + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_override); + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_override1); + /* Specifies the value for MC_EMEM_ARB_RSV */ + CASE_SET_SDRAM_PARAM(mc_emem_arb_rsv); + + CASE_SET_SDRAM_PARAM(mc_da_cfg0); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_ccdmw); + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + CASE_SET_SDRAM_PARAM(mc_clken_override); + + /* Specifies the value for MC_STAT_CONTROL */ + CASE_SET_SDRAM_PARAM(mc_stat_control); + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + CASE_SET_SDRAM_PARAM(mc_video_protect_bom); + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + CASE_SET_SDRAM_PARAM(mc_video_protect_bom_adr_hi); + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + CASE_SET_SDRAM_PARAM(mc_video_protect_size_mb); + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + CASE_SET_SDRAM_PARAM(mc_video_protect_vpr_override); + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + CASE_SET_SDRAM_PARAM(mc_video_protect_vpr_override1); + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + CASE_SET_SDRAM_PARAM(mc_video_protect_gpu_override0); + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + CASE_SET_SDRAM_PARAM(mc_video_protect_gpu_override1); + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + CASE_SET_SDRAM_PARAM(mc_sec_carveout_bom); + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + CASE_SET_SDRAM_PARAM(mc_sec_carveout_adr_hi); + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + CASE_SET_SDRAM_PARAM(mc_sec_carveout_size_mb); + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ + CASE_SET_SDRAM_PARAM(mc_video_protect_write_access); + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ + CASE_SET_SDRAM_PARAM(mc_sec_carveout_protect_write_access); + + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_bom); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_bom_hi); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_size_128kb); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_force_internal_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout1_cfg0); + + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_bom); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_bom_hi); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_size_128kb); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_force_internal_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout2_cfg0); + + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_bom); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_bom_hi); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_size_128kb); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_force_internal_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout3_cfg0); + + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_bom); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_bom_hi); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_size_128kb); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_force_internal_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout4_cfg0); + + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_bom); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_bom_hi); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_size_128kb); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access0); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access1); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access2); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access3); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_force_internal_access4); + CASE_SET_SDRAM_PARAM(mc_generalized_carveout5_cfg0); + + /* Specifies enable for CA training */ + CASE_SET_SDRAM_PARAM(emc_ca_training_enable); + /* Set if bit 6 select is greater than bit 7 select); uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ + CASE_SET_SDRAM_PARAM(swizzle_rank_byte_encode); + /* Specifies enable and offset for patched boot rom write */ + CASE_SET_SDRAM_PARAM(boot_rom_patch_control); + /* Specifies data for patched boot rom write */ + CASE_SET_SDRAM_PARAM(boot_rom_patch_data); + + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + CASE_SET_SDRAM_PARAM(mc_mts_carveout_bom); + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + CASE_SET_SDRAM_PARAM(mc_mts_carveout_adr_hi); + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + CASE_SET_SDRAM_PARAM(mc_mts_carveout_size_mb); + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + CASE_SET_SDRAM_PARAM(mc_mts_carveout_reg_ctrl); + + DEFAULT(); + } + return 0; +} + +int +t210_getbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_GET_BL_PARAM(version); + CASE_GET_BL_PARAM(start_blk); + CASE_GET_BL_PARAM(start_page); + CASE_GET_BL_PARAM(length); + CASE_GET_BL_PARAM(load_addr); + CASE_GET_BL_PARAM(entry_point); + CASE_GET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(data, + &(bct_ptr->bootloader[set].signature.crypto_hash), + sizeof(nvboot_hash)); + break; + + case token_rsa_pss_sig_bl: + reverse_byte_order((uint8_t *)data, + (const uint8_t *)&bct_ptr->bootloader[set].signature.rsa_pss_sig, + sizeof(nvboot_rsa_pss_sig)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t210_setbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_SET_BL_PARAM(version); + CASE_SET_BL_PARAM(start_blk); + CASE_SET_BL_PARAM(start_page); + CASE_SET_BL_PARAM(length); + CASE_SET_BL_PARAM(load_addr); + CASE_SET_BL_PARAM(entry_point); + CASE_SET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(&(bct_ptr->bootloader[set].signature.crypto_hash), + data, + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t210_bct_get_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + nvboot_config_table samplebct; /* Used for computing offsets. */ + + /* + * Note: Not all queries require use of the BCT, so testing for a + * valid BCT is distributed within the code. + */ + if (data == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_GET_NVU32(boot_data_version); + CASE_GET_NVU32(block_size_log2); + CASE_GET_NVU32(page_size_log2); + CASE_GET_NVU32(partition_size); + CASE_GET_NVU32(num_param_sets); + CASE_GET_NVU32(num_sdram_sets); + CASE_GET_NVU32(bootloader_used); + CASE_GET_NVU32(odm_data); + CASE_GET_NVU32(secure_debug_control); + + case token_block_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->block_size_log2; + break; + + case token_page_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->page_size_log2; + break; + + /* + * Constants. + */ + CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); + CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); + case token_crypto_hash: + memcpy(data, + &(bct_ptr->signature.crypto_hash), + sizeof(nvboot_hash)); + break; + + case token_unique_chip_id: + memcpy(data, &(bct_ptr->unique_chip_id), sizeof(nvboot_ecid)); + break; + + case token_rsa_key_modulus: + reverse_byte_order(data, (const uint8_t *)&bct_ptr->key, + sizeof(nvboot_rsa_key_modulus)); + break; + + case token_rsa_pss_sig_bct: + reverse_byte_order(data, + (const uint8_t *)&bct_ptr->signature.rsa_pss_sig, + sizeof(nvboot_rsa_pss_sig)); + break; + + case token_reserved_offset: + *((uint32_t *)data) = (uint8_t *)&(samplebct.reserved) + - (uint8_t *)&samplebct; + break; + + case token_bct_size: + *((uint32_t *)data) = sizeof(nvboot_config_table); + break; + + CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); + + case token_crypto_offset: + /* Offset to region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)&(samplebct.random_aes_blk) + - (uint8_t *)&samplebct; + break; + + case token_crypto_length: + /* size of region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)bct_ptr + sizeof(nvboot_config_table) + - (uint8_t *)&(bct_ptr->random_aes_blk); + break; + + CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); + + CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); + CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); + + CASE_GET_CONST_PREFIX(memory_type_none, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr3, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr4, nvboot); + + default: + return -ENODATA; + } + return 0; +} + +int +t210_bct_get_value_size(parse_token id) +{ + switch (id) { + case token_rsa_key_modulus: + return sizeof(nvboot_rsa_key_modulus); + + case token_rsa_pss_sig_bl: + return sizeof(nvboot_rsa_pss_sig); + + case token_rsa_pss_sig_bct: + return sizeof(nvboot_rsa_pss_sig); + + /* + * Other bct fields can be added in when needed + */ + default: + return -ENODATA; + } + return 0; +} + +int +t210_bct_set_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_SET_NVU32(boot_data_version); + CASE_SET_NVU32(block_size_log2); + CASE_SET_NVU32(page_size_log2); + CASE_SET_NVU32(partition_size); + CASE_SET_NVU32(num_param_sets); + CASE_SET_NVU32(num_sdram_sets); + CASE_SET_NVU32(bootloader_used); + CASE_SET_NVU32(odm_data); + CASE_SET_NVU32(secure_debug_control); + case token_unique_chip_id: + memcpy(&bct_ptr->unique_chip_id, data, sizeof(nvboot_ecid)); + break; + + case token_rsa_key_modulus: + reverse_byte_order((uint8_t *)&bct_ptr->key, data, + sizeof(nvboot_rsa_key_modulus)); + break; + + case token_rsa_pss_sig_bl: + /* + * Update bootloader 0 since there is only one copy + * of bootloader being built in. + */ + reverse_byte_order( + (uint8_t *)&bct_ptr->bootloader[0].signature.rsa_pss_sig, + data, sizeof(nvboot_rsa_pss_sig)); + break; + + case token_rsa_pss_sig_bct: + reverse_byte_order((uint8_t *)&bct_ptr->signature.rsa_pss_sig, + data, sizeof(nvboot_rsa_pss_sig)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t210_bct_set_data(parse_token id, + uint8_t *data, + uint32_t length, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + + case token_crypto_hash: + if (length < sizeof(nvboot_hash)) + return -ENODATA; + memcpy(&bct_ptr->signature.crypto_hash, data, sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int t210_get_bct_size() +{ + return sizeof(nvboot_config_table); +} + +int t210_bct_token_supported(parse_token token) +{ + int index; + + for (index = 0; index < ARRAY_SIZE(t210_root_token_list); index++) + if (t210_root_token_list[index] == token) + return 1; + + return 0; +} + +void t210_init_bad_block_table(build_image_context *context) +{ + uint32_t bytes_per_entry; + nvboot_badblock_table *table; + nvboot_config_table *bct; + + bct = (nvboot_config_table *)(context->bct); + + assert(context != NULL); + assert(bct != NULL); + + table = &bct->badblock_table; + + bytes_per_entry = ICEIL(context->partition_size, + NVBOOT_BAD_BLOCK_TABLE_SIZE); + table->block_size_log2 = context->block_size_log2; + table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), + table->block_size_log2); + table->entries_used = iceil_log2(context->partition_size, + table->virtual_blk_size_log2); +} + +cbootimage_soc_config tegra210_config = { + .init_bad_block_table = t210_init_bad_block_table, + .set_dev_param = t210_set_dev_param, + .get_dev_param = t210_get_dev_param, + .set_sdram_param = t210_set_sdram_param, + .get_sdram_param = t210_get_sdram_param, + .setbl_param = t210_setbl_param, + .getbl_param = t210_getbl_param, + .set_value = t210_bct_set_value, + .get_value = t210_bct_get_value, + .get_value_size = t210_bct_get_value_size, + .set_data = t210_bct_set_data, + .get_bct_size = t210_get_bct_size, + .token_supported = t210_bct_token_supported, + + .devtype_table = s_devtype_table_t210, + .sdmmc_data_width_table = s_sdmmc_data_width_table_t210, + .spi_clock_source_table = s_spi_clock_source_table_t210, + .nvboot_memory_type_table = s_nvboot_memory_type_table_t210, + .sdram_field_table = s_sdram_field_table_t210, + .nand_table = 0, + .sdmmc_table = s_sdmmc_table_t210, + .spiflash_table = s_spiflash_table_t210, + .device_type_table = s_device_type_table_t210, +}; + +void t210_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + context->boot_data_version = BOOTDATA_VERSION_T210; + *soc_config = &tegra210_config; +} + +int if_bct_is_t210_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + nvboot_config_table *bct = (nvboot_config_table*) context->bct; + + if (bct->boot_data_version == BOOTDATA_VERSION_T210) { + t210_get_soc_config(context, soc_config); + return 1; + } + return 0; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t210/nvboot_bct_t210.h b/firmware/coreboot/util/nvidia/cbootimage/src/t210/nvboot_bct_t210.h new file mode 100644 index 0000000000..09463959c2 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t210/nvboot_bct_t210.h @@ -0,0 +1,406 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#ifndef INCLUDED_NVBOOT_BCT_T210_H +#define INCLUDED_NVBOOT_BCT_T210_H + +#include +#include "nvboot_sdram_param_t210.h" + +/** + * Defines the number of 32-bit words in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_WORDS 49 + +/** + * Defines the number of bytes in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_SIZE \ + (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) + +/** + * Defines the number of bytes in the reserved area of the BCT. + */ +#define NVBOOT_BCT_RESERVED_SIZE 18 + +/** + * Defines the maximum number of bootloader descriptions in the BCT. + */ +#define NVBOOT_MAX_BOOTLOADERS 4 + +/** + * Defines the maximum number of device parameter sets in the BCT. + * The value must be equal to (1 << # of device straps) + */ +#define NVBOOT_BCT_MAX_PARAM_SETS 1 + +/** + * Defines the maximum number of SDRAM parameter sets in the BCT. + * The value must be equal to (1 << # of SDRAM straps) + */ +#define NVBOOT_BCT_MAX_SDRAM_SETS 4 + +/** + * Defines the number of entries (bits) in the bad block table. + * The consequences of changing its value are as follows. Using P as the + * # of physical blocks in the boot loader and B as the value of this + * constant: + * B > P: There will be unused storage in the bad block table. + * B < P: The virtual block size will be greater than the physical block + * size, so the granularity of the bad block table will be less than + * one bit per physical block. + * + * 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one + * bit per block (1 virtual block = 1 physical block). This occupies 512 bytes + * of storage. + */ +#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096 + +/** + * Defines the amount of padding needed to pad the bad block table to a + * multiple of AES block size. + */ +#define NVBOOT_BAD_BLOCK_TABLE_PADDING 10 + +/** + * Defines the maximum number of blocks to search for BCTs. + * + * This value covers the initial block and a set of journal blocks. + * + * Ideally, this number will span several erase units for reliable updates + * and tolerance for blocks to become bad with use. Safe updates require + * a minimum of 2 erase units in which BCTs can appear. + * + * To ensure that the BCT search spans a sufficient range of configurations, + * the search block count has been set to 64. This allows for redundancy with + * a wide range of parts and provides room for greater problems in this + * region of the device. + */ +#define NVBOOT_MAX_BCT_SEARCH_BLOCKS 64 + +#define ARSE_RSA_MAX_MODULUS_SIZE 2048 + +/** + * Defines the RSA modulus length in bits and bytes used for PKC secure boot. + */ +enum {NVBOOT_SE_RSA_MODULUS_LENGTH_BITS = ARSE_RSA_MAX_MODULUS_SIZE}; + +/* + * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) + */ +enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; + +/** + * Defines the storage for a hash value (128 bits). + */ +typedef struct nvboot_hash_rec { + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; +} nvboot_hash; + +/* + * Defines the storage for the RSA public key's modulus + * in the BCT + */ +typedef struct nvboot_rsa_key_modulus_rec { + /* The modulus size is 2048-bits. */ + uint32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; +} nvboot_rsa_key_modulus; + +typedef struct nvboot_rsa_pss_sig_rec { + /* + * The RSA-PSS signature length is equal to the + * length in octets of the RSA modulus. + * In our case, it's 2048-bits. + */ + uint32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; +} nvboot_rsa_pss_sig; + +typedef struct nvboot_object_signature_rec { + /* + * Specifies the AES-CMAC signature for the rest of the BCT structure + * if symmetric key encryption secure boot scheme is used. + */ + nvboot_hash crypto_hash; + + /* + * Specifies the RSASSA-PSS signature for the rest of the BCT structure + * if public key cryptography secure boot scheme is used. + */ + nvboot_rsa_pss_sig rsa_pss_sig; +} nvboot_object_signature; + +typedef struct nvboot_ecid_rec { + uint32_t ecid_0; + uint32_t ecid_1; + uint32_t ecid_2; + uint32_t ecid_3; +} nvboot_ecid; + +/* Defines various data widths supported. */ +typedef enum { + /** + * Specifies a 1 bit interface to eMMC. + * Note that 1-bit data width is only for the driver's internal use. + * Fuses doesn't provide option to select 1-bit data width. + * The driver selects 1-bit internally based on need. + * It is used for reading Extended CSD and when the power class + * requirements of a card for 4-bit or 8-bit transfers are not + * supported by the target board. + */ + nvboot_sdmmc_data_width_1bit = 0, + + /* Specifies a 4 bit interface to eMMC. */ + nvboot_sdmmc_data_width_4bit = 1, + + /* Specifies a 8 bit interface to eMMC. */ + nvboot_sdmmc_data_width_8bit = 2, + /* Specifies a 4 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_4bit = 5, + /* Specifies a 8 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_8bit = 6, + + nvboot_sdmmc_data_width_num, + nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF +} nvboot_sdmmc_data_width; + +/* Defines the parameters that can be changed after BCT is read. */ +typedef struct nvboot_sdmmc_params_rec { + /** + * Specifies the clock divider for the SDMMC controller's clock source, + * which is PLLP running at 216MHz. If it is set to 9, then the SDMMC + * controller runs at 216/9 = 24MHz. + */ + uint8_t clock_divider; + + /* Specifies the data bus width. Supported data widths are 4/8 bits. */ + nvboot_sdmmc_data_width data_width; + + /** + * Max Power class supported by the target board. + * The driver determines the best data width and clock frequency + * supported within the power class range (0 to Max) if the selected + * data width cannot be used at the chosen clock frequency. + */ + uint8_t max_power_class_supported; + + /* Specifies the max page size supported by driver */ + uint8_t multi_page_support; +} nvboot_sdmmc_params; + +typedef enum { + /* Specifies SPI clock source to be PLLP. */ + nvboot_spi_clock_source_pllp_out0 = 0, + + /* Specifies SPI clock source to be ClockM. */ + nvboot_spi_clock_source_clockm = 6, + + nvboot_spi_clock_source_num, + nvboot_spi_clock_source_force32 = 0x7FFFFFF +} nvboot_spi_clock_source; + +/** + * Defines the parameters SPI FLASH devices. + */ +typedef struct nvboot_spiflash_params_rec { + /** + * Specifies the clock source to use. + */ + uint32_t clock_source; + + /** + * Specifes the clock divider to use. + * The value is a 7-bit value based on an input clock of 432Mhz. + * Divider = (432+ DesiredFrequency-1)/DesiredFrequency; + * Typical values: + * NORMAL_READ at 20MHz: 22 + * FAST_READ at 33MHz: 14 + * FAST_READ at 40MHz: 11 + * FAST_READ at 50MHz: 9 + */ + uint8_t clock_divider; + + /** + * Specifies the type of command for read operations. + * NV_FALSE specifies a NORMAL_READ Command + * NV_TRUE specifies a FAST_READ Command + */ + uint8_t read_command_type_fast; + + /* 0 = 2k page size, 1 = 16K page size */ + uint8_t page_size_2k_or_16k; +} nvboot_spiflash_params; + +/** +* Defines the union of the parameters required by each device. +*/ +typedef union { + uint8_t size[64]; + /* Specifies optimized parameters for eMMC and eSD */ + nvboot_sdmmc_params sdmmc_params; + /* Specifies optimized parameters for SPI NOR */ + nvboot_spiflash_params spiflash_params; +} nvboot_dev_params; + +/** + * Identifies the types of devices from which the system booted. + * Used to identify primary and secondary boot devices. + * @note These no longer match the fuse API device values (for + * backward compatibility with AP15). + */ +typedef enum { + /* Specifies a default (unset) value. */ + nvboot_dev_type_none = 0, + + /* Specifies SPI NOR. */ + nvboot_dev_type_spi = 3, + + /* Specifies SDMMC (either eMMC or eSD). */ + nvboot_dev_type_sdmmc = 4, + + nvboot_dev_type_max, + + /* Ignore -- Forces compilers to make 32-bit enums. */ + nvboot_dev_type_force32 = 0x7FFFFFFF +} nvboot_dev_type; + +/** + * Stores information needed to locate and verify a boot loader. + * + * There is one \c nv_bootloader_info structure for each copy of a BL stored on + * the device. + */ +typedef struct nv_bootloader_info_rec { + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; + + /* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */ + nvboot_object_signature signature; +} nv_bootloader_info; + +/** + * Defines the bad block table structure stored in the BCT. + */ +typedef struct nvboot_badblock_table_rec { + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; + /* + * Add a reserved field as padding to make the bad block table structure + * a multiple of 16 bytes (AES block size). + */ + uint8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; +} nvboot_badblock_table; + +enum {NVBOOT_SE_AES_KEY256_LENGTH_BYTES = 32}; +/** + * Contains the information needed to load BLs from the secondary boot device. + * + * - Supplying NumParamSets = 0 indicates not to load any of them. + * - Supplying NumDramSets = 0 indicates not to load any of them. + * - The \c random_aes_blk member exists to increase the difficulty of + * key attacks based on knowledge of this structure. + */ +typedef struct nvboot_config_table_rec { + nvboot_badblock_table badblock_table; + nvboot_rsa_key_modulus key; + nvboot_object_signature signature; /* 310 */ + + /** + * Specifies the Factory Secure Provisioning number to be used. + * Only valid and consumed by BR in NvProduction Mode. + * Because the key number is specified in the BCT, BR needs to read in + * the BCT first to know the key number to validate against. + * This field must match SecProvisioningKeyNum_Secure to be a valid + * BCT for use in the Factory Secure Provisioning mode. + */ + uint32_t secure_provisioning_key_number_insecure; /* 420 */ + + /** + * A 256-bit AES key encrypted by a reserved 256-bit AES "key wrap" + * key. Only used in Factory Secure Provisioning mode. + */ + uint8_t aes_key[NVBOOT_SE_AES_KEY256_LENGTH_BYTES]; /* 424 */ + + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; /* 444 */ + uint32_t odm_data; /* 508 */ + uint32_t reserved1; + + /* START OF SIGNED SECTION OF THE BCT */ + nvboot_hash random_aes_blk; /* 0x510 */ + nvboot_ecid unique_chip_id; /* 0x520 */ + uint32_t boot_data_version; /* 0x530 */ + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; + nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; + nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; + uint32_t num_sdram_sets; /* 0x588 */ + nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; /* 0x58c */ + + uint32_t bootloader_used; /* 0x232c */ + nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; /* 0x2330 */ + + uint8_t enable_fail_back; + + /** + * Specifies which debug features to be enabled or disabled. + * Maps directly to APBDEV_PMC_DEBUG_AUTHENTICATION_0. Must specify + * the ECID of the chip in UniqueChipId on production systems. + * 0x1 = ENABLED. 0x0 = DISABLED. + * DBGEN - bit 5 + * NIDEN - bit 4 + * SPIDEN - bit 3 + * SPNIDEN - bit 2 + * DEVICEEN - bit 1 + * JTAG_ENABLE - bit 0 + */ + uint32_t secure_debug_control; + + /** + * Specifies the factory secure provisioning key number to use. + * There are 64 such 256-bit AES keys. + * + * Specifying a key number of 0 will cause Boot ROM to default to + * NvProduction mode boot (i.e. Factory Secure Provisioning mode + * disabled). + * + * Specifying a key number of 1 to 15 is invalid. These are + * anti-cloning keys numbers and BR will ignore these values. + * BR will ignore this field if the secure_provision_index fuse is + * burned. + * + * Key number 64 (index [63]) is reserved for NVIDIA debug use. + * So, this field will only be used if the chip is in NvProductionMode, + * and when secure_provision_index is zero, and when + * SecProvisioningKeyNum is not 0 to 15. + * + * This key number must match SecProvisioningKeyNum_Insecure. + */ + uint32_t secure_provisioning_key_number_secure; + + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; +} nvboot_config_table; +#endif /* #ifndef INCLUDED_NVBOOT_BCT_T210_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t210/nvboot_sdram_param_t210.h b/firmware/coreboot/util/nvidia/cbootimage/src/t210/nvboot_sdram_param_t210.h new file mode 100644 index 0000000000..67ae9f6b8e --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t210/nvboot_sdram_param_t210.h @@ -0,0 +1,953 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T210_H +#define INCLUDED_NVBOOT_SDRAM_PARAM_T210_H + +#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 + +typedef enum { + /* Specifies the memory type to be undefined */ + nvboot_memory_type_none = 0, + + /* Specifies the memory type to be DDR SDRAM */ + nvboot_memory_type_ddr = 0, + + /* Specifies the memory type to be LPDDR SDRAM */ + nvboot_memory_type_lpddr = 0, + + /* Specifies the memory type to be DDR2 SDRAM */ + nvboot_memory_type_ddr2 = 0, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + nvboot_memory_type_lpddr2, + + /* Specifies the memory type to be DDR3 SDRAM */ + nvboot_memory_type_ddr3, + + /* Specifies the memory type to be LPDDR4 SDRAM */ + nvboot_memory_type_lpddr4, + + nvboot_memory_type_num, + nvboot_memory_type_force32 = 0x7FFFFFF +} nvboot_memory_type; + +/** + * Defines the SDRAM parameter structure + */ +typedef struct nvboot_sdram_params_rec { + /* sdram data structure generated by tool warmboot_code_gen */ + + /* Specifies the type of memory device */ + nvboot_memory_type memory_type; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t pllm_input_divider; + /* Specifies the N value for PllM */ + uint32_t pllm_feedback_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t pllm_stable_time; + /* Specifies misc. control bits */ + uint32_t pllm_setup_control; + /* Specifies the P value for PLLM */ + uint32_t pllm_post_divider; + /* Specifies value for Charge Pump Gain Control */ + uint32_t pllm_kcp; + /* Specifies VCO gain */ + uint32_t pllm_kvco; + /* Spare BCT param */ + uint32_t emc_bct_spare0; + /* Spare BCT param */ + uint32_t emc_bct_spare1; + /* Spare BCT param */ + uint32_t emc_bct_spare2; + /* Spare BCT param */ + uint32_t emc_bct_spare3; + /* Spare BCT param */ + uint32_t emc_bct_spare4; + /* Spare BCT param */ + uint32_t emc_bct_spare5; + /* Spare BCT param */ + uint32_t emc_bct_spare6; + /* Spare BCT param */ + uint32_t emc_bct_spare7; + /* Spare BCT param */ + uint32_t emc_bct_spare8; + /* Spare BCT param */ + uint32_t emc_bct_spare9; + /* Spare BCT param */ + uint32_t emc_bct_spare10; + /* Spare BCT param */ + uint32_t emc_bct_spare11; + /* Spare BCT param */ + uint32_t emc_bct_spare12; + /* Spare BCT param */ + uint32_t emc_bct_spare13; + + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t emc_clock_source; + uint32_t emc_clock_source_dll; + + /* Defines possible override for PLLLM_MISC2 */ + uint32_t clk_rst_pllm_misc20_override; + /* enables override for PLLLM_MISC2 */ + uint32_t clk_rst_pllm_misc20_override_enable; + /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ + uint32_t clear_clock2_mc1; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t emc_auto_cal_interval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t emc_auto_cal_config; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t emc_auto_cal_config2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t emc_auto_cal_config3; + + uint32_t emc_auto_cal_config4; + uint32_t emc_auto_cal_config5; + uint32_t emc_auto_cal_config6; + uint32_t emc_auto_cal_config7; + uint32_t emc_auto_cal_config8; + /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ + uint32_t emc_auto_cal_vref_sel0; + uint32_t emc_auto_cal_vref_sel1; + + /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ + uint32_t emc_auto_cal_channel; + + /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ + uint32_t emc_pmacro_auto_cal_cfg0; + uint32_t emc_pmacro_auto_cal_cfg1; + uint32_t emc_pmacro_auto_cal_cfg2; + + uint32_t emc_pmacro_rx_term; + uint32_t emc_pmacro_dq_tx_drive; + uint32_t emc_pmacro_ca_tx_drive; + uint32_t emc_pmacro_cmd_tx_drive; + uint32_t emc_pmacro_auto_cal_common; + uint32_t emc_pmacro_zcrtl; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t emc_auto_cal_wait; + + uint32_t emc_xm2_comp_pad_ctrl; + uint32_t emc_xm2_comp_pad_ctrl2; + uint32_t emc_xm2_comp_pad_ctrl3; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t emc_adr_cfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t emc_pin_program_wait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t emc_pin_extra_wait; + + uint32_t emc_pin_gpio_enable; + uint32_t emc_pin_gpio; + + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t emc_timing_control_wait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t emc_rc; + /* Specifies the value for EMC_RFC */ + uint32_t emc_rfc; + + uint32_t emc_rfc_pb; + uint32_t emc_ref_ctrl2; + + /* Specifies the value for EMC_RFC_SLR */ + uint32_t emc_rfc_slr; + /* Specifies the value for EMC_RAS */ + uint32_t emc_ras; + /* Specifies the value for EMC_RP */ + uint32_t emc_rp; + /* Specifies the value for EMC_R2R */ + uint32_t emc_r2r; + /* Specifies the value for EMC_W2W */ + uint32_t emc_w2w; + /* Specifies the value for EMC_R2W */ + uint32_t emc_r2w; + /* Specifies the value for EMC_W2R */ + uint32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + uint32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + uint32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + + uint32_t emc_tppd; + uint32_t emc_ccdmw; + + uint32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + uint32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + uint32_t emc_rext; + /* Specifies the value for EMC_WEXT */ + uint32_t emc_wext; + /* Specifies the value for EMC_WDV */ + uint32_t emc_wdv; + + uint32_t emc_wdv_chk; + uint32_t emc_wsv; + uint32_t emc_wev; + + /* Specifies the value for EMC_WDV_MASK */ + uint32_t emc_wdv_mask; + + uint32_t emc_ws_duration; + uint32_t emc_we_duration; + + /* Specifies the value for EMC_QUSE */ + uint32_t emc_quse; + /* Specifies the value for EMC_QUSE_WIDTH */ + uint32_t emc_quse_width; + /* Specifies the value for EMC_IBDLY */ + uint32_t emc_ibdly; + + uint32_t emc_obdly; + + /* Specifies the value for EMC_EINPUT */ + uint32_t emc_einput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t emc_einput_duration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t emc_puterm_extra; + /* Specifies the value for EMC_PUTERM_WIDTH */ + uint32_t emc_puterm_width; + + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; + + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; + + /* Specifies the value for EMC_QPOP */ + uint32_t emc_qpop; + + /* Specifies the value for EMC_REFRESH */ + uint32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t emc_prerefresh_req_cnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t emc_rw2pden; + + uint32_t emc_cke2pden; + uint32_t emc_pdex2che; + uint32_t emc_pdex2mrr; + + /* Specifies the value for EMC_TXSR */ + uint32_t emc_txsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t emc_txsr_dll; + /* Specifies the value for EMC_TCKE */ + uint32_t emc_tcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t emc_tckesr; + /* Specifies the value for EMC_TPD */ + uint32_t emc_tpd; + /* Specifies the value for EMC_TFAW */ + uint32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + uint32_t emc_trefbw; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG7 */ + uint32_t emc_fbio_cfg7; + uint32_t emc_fbio_cfg8; + + /* Command mapping for CMD brick 0 */ + uint32_t emc_cmd_mapping_cmd0_0; + uint32_t emc_cmd_mapping_cmd0_1; + uint32_t emc_cmd_mapping_cmd0_2; + uint32_t emc_cmd_mapping_cmd1_0; + uint32_t emc_cmd_mapping_cmd1_1; + uint32_t emc_cmd_mapping_cmd1_2; + uint32_t emc_cmd_mapping_cmd2_0; + uint32_t emc_cmd_mapping_cmd2_1; + uint32_t emc_cmd_mapping_cmd2_2; + uint32_t emc_cmd_mapping_cmd3_0; + uint32_t emc_cmd_mapping_cmd3_1; + uint32_t emc_cmd_mapping_cmd3_2; + uint32_t emc_cmd_mapping_byte; + + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t emc_fbio_spare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t emc_cfg_rsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t emc_mrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t emc_emrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t emc_emrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t emc_emrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t emc_mrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t emc_mrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t emc_mrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t emc_mrw4; + + /* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */ + uint32_t emc_mrw6; + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + uint32_t emc_mrw8; + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + uint32_t emc_mrw9; + /* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */ + uint32_t emc_mrw10; + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + uint32_t emc_mrw12; + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + uint32_t emc_mrw13; + /* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */ + uint32_t emc_mrw14; + + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t emc_mrw_extra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t emc_warm_boot_mrw_extra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t emc_warm_boot_extramode_reg_write_enable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t emc_extramode_reg_write_enable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t emc_mrw_reset_ninit_wait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t emc_mrs_wait_cnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t emc_mrs_wait_cnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t emc_cfg2; + /* Specifies the pipe bypass controls */ + uint32_t emc_cfg_pipe; + + uint32_t emc_cfg_pipe_clk; + uint32_t emc_fdpd_ctrl_cmd_no_ramp; + uint32_t emc_cfg_update; + + /* Specifies the value for EMC_DBG */ + uint32_t emc_dbg; + + uint32_t emc_dbg_write_mux; + + /* Specifies the value for EMC_CMDQ */ + uint32_t emc_cmd_q; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t emc_mc2emc_q; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t emc_dyn_self_ref_control; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t ahb_arbitration_xbar_ctrl_meminit_done; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_1; + + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t emc_cfg_dig_dll_period; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t emc_dev_select; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t emc_sel_dpd_ctrl; + + /* Pads trimmer delays */ + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_pmacro_ib_vref_dq_0; + uint32_t emc_pmacro_ib_vref_dq_1; + uint32_t emc_pmacro_ib_vref_dqs_0; + uint32_t emc_pmacro_ib_vref_dqs_1; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe1; + uint32_t emc_cfg_pipe2; + + /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ + uint32_t emc_pmacro_quse_ddll_rank0_0; + uint32_t emc_pmacro_quse_ddll_rank0_1; + uint32_t emc_pmacro_quse_ddll_rank0_2; + uint32_t emc_pmacro_quse_ddll_rank0_3; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_0; + uint32_t emc_pmacro_quse_ddll_rank1_1; + uint32_t emc_pmacro_quse_ddll_rank1_2; + uint32_t emc_pmacro_quse_ddll_rank1_3; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3; + + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t warm_boot_wait; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_write; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t emc_zcal_interval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t emc_zcal_wait_cnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t emc_zcal_mrw_cmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t emc_mrs_reset_dll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t emc_zcal_init_dev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t emc_zcal_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t emc_zcal_init_wait; + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + uint32_t emc_zcal_warm_cold_boot_enables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t emc_mrw_lpddr2zcal_warm_boot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t emc_zqcal_ddr3_warm_boot; + + uint32_t emc_zqcal_lpddr4_warm_boot; + + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t emc_zcal_warm_boot_wait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t emc_mrs_warm_boot_enable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t emc_mrs_reset_dll_wait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t emc_mrs_extra; + /* Specifies the extra MRS command at warm boot */ + uint32_t emc_warm_boot_mrs_extra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t emc_ddr2_wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t emc_clken_override; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t emc_extra_refresh_num; + /* Specifies the master override for all EMC clocks */ + uint32_t emc_clken_override_allwarm_boot; + /* Specifies the master override for all MC clocks */ + uint32_t mc_clken_override_allwarm_boot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t emc_cfg_dig_dll_period_warm_boot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel; + /* Specifies the wait time after programming PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel_wait; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t pmc_ddr_pwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t pmc_ddr_cfg; + /* Specifies the value for PMC_IO_DPD3_REQ */ + uint32_t pmc_io_dpd3_req; + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + uint32_t pmc_io_dpd3_req_wait; + + uint32_t pmc_io_dpd4_req_wait; + + /* Specifies the value for PMC_REG_SHORT */ + uint32_t pmc_reg_short; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t pmc_no_io_power; + + uint32_t pmc_ddr_ctrl_wait; + uint32_t pmc_ddr_ctrl; + + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t emc_acpd_control; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t emc_swizzle_rank0_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t emc_swizzle_rank0_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t emc_swizzle_rank0_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t emc_swizzle_rank0_byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t emc_swizzle_rank1_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t emc_swizzle_rank1_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t emc_swizzle_rank1_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t emc_swizzle_rank1_byte3; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t emc_txdsrvttgen; + + /* Specifies the value for EMC_DATA_BRLSHFT_0 */ + uint32_t emc_data_brlshft0; + uint32_t emc_data_brlshft1; + + uint32_t emc_dqs_brlshft0; + uint32_t emc_dqs_brlshft1; + + uint32_t emc_cmd_brlshft0; + uint32_t emc_cmd_brlshft1; + uint32_t emc_cmd_brlshft2; + uint32_t emc_cmd_brlshft3; + + uint32_t emc_quse_brlshft0; + uint32_t emc_quse_brlshft1; + uint32_t emc_quse_brlshft2; + uint32_t emc_quse_brlshft3; + + uint32_t emc_dll_cfg0; + uint32_t emc_dll_cfg1; + + uint32_t emc_pmc_scratch1; + uint32_t emc_pmc_scratch2; + uint32_t emc_pmc_scratch3; + + uint32_t emc_pmacro_pad_cfg_ctrl; + + uint32_t emc_pmacro_vttgen_ctrl0; + uint32_t emc_pmacro_vttgen_ctrl1; + uint32_t emc_pmacro_vttgen_ctrl2; + + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl0; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_common_pad_tx_ctrl; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_cfg3; + + uint32_t emc_pmacro_tx_pwrd0; + uint32_t emc_pmacro_tx_pwrd1; + uint32_t emc_pmacro_tx_pwrd2; + uint32_t emc_pmacro_tx_pwrd3; + uint32_t emc_pmacro_tx_pwrd4; + uint32_t emc_pmacro_tx_pwrd5; + + uint32_t emc_config_sample_delay; + + uint32_t emc_pmacro_brick_mapping0; + uint32_t emc_pmacro_brick_mapping1; + uint32_t emc_pmacro_brick_mapping2; + + uint32_t emc_pmacro_tx_sel_clk_src0; + uint32_t emc_pmacro_tx_sel_clk_src1; + uint32_t emc_pmacro_tx_sel_clk_src2; + uint32_t emc_pmacro_tx_sel_clk_src3; + uint32_t emc_pmacro_tx_sel_clk_src4; + uint32_t emc_pmacro_tx_sel_clk_src5; + + uint32_t emc_pmacro_ddll_bypass; + + uint32_t emc_pmacro_ddll_pwrd0; + uint32_t emc_pmacro_ddll_pwrd1; + uint32_t emc_pmacro_ddll_pwrd2; + + uint32_t emc_pmacro_cmd_ctrl0; + uint32_t emc_pmacro_cmd_ctrl1; + uint32_t emc_pmacro_cmd_ctrl2; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t mc_emem_adr_cfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t mc_emem_adr_cfg_dev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t mc_emem_adr_cfg_dev1; + + uint32_t mc_emem_adr_cfg_channel_mask; + + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ + uint32_t mc_emem_adr_cfg_bank_mask0; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + uint32_t mc_emem_adr_cfg_bank_mask1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + uint32_t mc_emem_adr_cfg_bank_mask2; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t mc_emem_cfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t mc_emem_arb_cfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t mc_emem_arb_outstanding_req; + + uint32_t emc_emem_arb_refpb_hp_ctrl; + uint32_t emc_emem_arb_refpb_bank_ctrl; + + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t mc_emem_arb_timing_rcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t mc_emem_arb_timing_rp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t mc_emem_arb_timing_rc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t mc_emem_arb_timing_ras; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t mc_emem_arb_timing_faw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t mc_emem_arb_timing_rrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t mc_emem_arb_timing_rap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t mc_emem_arb_timing_wap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t mc_emem_arb_timing_r2r; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t mc_emem_arb_timing_w2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t mc_emem_arb_timing_r2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t mc_emem_arb_timing_w2r; + + uint32_t mc_emem_arb_timing_rfcpb; + + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t mc_emem_arb_da_turns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t mc_emem_arb_da_covers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t mc_emem_arb_misc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t mc_emem_arb_misc1; + uint32_t mc_emem_arb_misc2; + + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t mc_emem_arb_ring1_throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t mc_emem_arb_override; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + uint32_t mc_emem_arb_override1; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t mc_emem_arb_rsv; + + uint32_t mc_da_cfg0; + uint32_t mc_emem_arb_timing_ccdmw; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t mc_clken_override; + + /* Specifies the value for MC_STAT_CONTROL */ + uint32_t mc_stat_control; + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t mc_video_protect_bom; + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + uint32_t mc_video_protect_bom_adr_hi; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t mc_video_protect_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t mc_video_protect_vpr_override; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + uint32_t mc_video_protect_vpr_override1; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + uint32_t mc_video_protect_gpu_override0; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + uint32_t mc_video_protect_gpu_override1; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t mc_sec_carveout_bom; + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + uint32_t mc_sec_carveout_adr_hi; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t mc_sec_carveout_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ + uint32_t mc_video_protect_write_access; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ + uint32_t mc_sec_carveout_protect_write_access; + + uint32_t mc_generalized_carveout1_bom; + uint32_t mc_generalized_carveout1_bom_hi; + uint32_t mc_generalized_carveout1_size_128kb; + uint32_t mc_generalized_carveout1_access0; + uint32_t mc_generalized_carveout1_access1; + uint32_t mc_generalized_carveout1_access2; + uint32_t mc_generalized_carveout1_access3; + uint32_t mc_generalized_carveout1_access4; + uint32_t mc_generalized_carveout1_force_internal_access0; + uint32_t mc_generalized_carveout1_force_internal_access1; + uint32_t mc_generalized_carveout1_force_internal_access2; + uint32_t mc_generalized_carveout1_force_internal_access3; + uint32_t mc_generalized_carveout1_force_internal_access4; + uint32_t mc_generalized_carveout1_cfg0; + + uint32_t mc_generalized_carveout2_bom; + uint32_t mc_generalized_carveout2_bom_hi; + uint32_t mc_generalized_carveout2_size_128kb; + uint32_t mc_generalized_carveout2_access0; + uint32_t mc_generalized_carveout2_access1; + uint32_t mc_generalized_carveout2_access2; + uint32_t mc_generalized_carveout2_access3; + uint32_t mc_generalized_carveout2_access4; + uint32_t mc_generalized_carveout2_force_internal_access0; + uint32_t mc_generalized_carveout2_force_internal_access1; + uint32_t mc_generalized_carveout2_force_internal_access2; + uint32_t mc_generalized_carveout2_force_internal_access3; + uint32_t mc_generalized_carveout2_force_internal_access4; + uint32_t mc_generalized_carveout2_cfg0; + + uint32_t mc_generalized_carveout3_bom; + uint32_t mc_generalized_carveout3_bom_hi; + uint32_t mc_generalized_carveout3_size_128kb; + uint32_t mc_generalized_carveout3_access0; + uint32_t mc_generalized_carveout3_access1; + uint32_t mc_generalized_carveout3_access2; + uint32_t mc_generalized_carveout3_access3; + uint32_t mc_generalized_carveout3_access4; + uint32_t mc_generalized_carveout3_force_internal_access0; + uint32_t mc_generalized_carveout3_force_internal_access1; + uint32_t mc_generalized_carveout3_force_internal_access2; + uint32_t mc_generalized_carveout3_force_internal_access3; + uint32_t mc_generalized_carveout3_force_internal_access4; + uint32_t mc_generalized_carveout3_cfg0; + + uint32_t mc_generalized_carveout4_bom; + uint32_t mc_generalized_carveout4_bom_hi; + uint32_t mc_generalized_carveout4_size_128kb; + uint32_t mc_generalized_carveout4_access0; + uint32_t mc_generalized_carveout4_access1; + uint32_t mc_generalized_carveout4_access2; + uint32_t mc_generalized_carveout4_access3; + uint32_t mc_generalized_carveout4_access4; + uint32_t mc_generalized_carveout4_force_internal_access0; + uint32_t mc_generalized_carveout4_force_internal_access1; + uint32_t mc_generalized_carveout4_force_internal_access2; + uint32_t mc_generalized_carveout4_force_internal_access3; + uint32_t mc_generalized_carveout4_force_internal_access4; + uint32_t mc_generalized_carveout4_cfg0; + + uint32_t mc_generalized_carveout5_bom; + uint32_t mc_generalized_carveout5_bom_hi; + uint32_t mc_generalized_carveout5_size_128kb; + uint32_t mc_generalized_carveout5_access0; + uint32_t mc_generalized_carveout5_access1; + uint32_t mc_generalized_carveout5_access2; + uint32_t mc_generalized_carveout5_access3; + uint32_t mc_generalized_carveout5_access4; + uint32_t mc_generalized_carveout5_force_internal_access0; + uint32_t mc_generalized_carveout5_force_internal_access1; + uint32_t mc_generalized_carveout5_force_internal_access2; + uint32_t mc_generalized_carveout5_force_internal_access3; + uint32_t mc_generalized_carveout5_force_internal_access4; + uint32_t mc_generalized_carveout5_cfg0; + + /* Specifies enable for CA training */ + uint32_t emc_ca_training_enable; + /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t swizzle_rank_byte_encode; + /* Specifies enable and offset for patched boot rom write */ + uint32_t boot_rom_patch_control; + /* Specifies data for patched boot rom write */ + uint32_t boot_rom_patch_data; + + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + uint32_t mc_mts_carveout_bom; + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + uint32_t mc_mts_carveout_adr_hi; + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + uint32_t mc_mts_carveout_size_mb; + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + uint32_t mc_mts_carveout_reg_ctrl; + /* End of generated code by warmboot_code_gen */ + +} nvboot_sdram_params; +#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T210_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t210/parse_t210.c b/firmware/coreboot/util/nvidia/cbootimage/src/t210/parse_t210.c new file mode 100644 index 0000000000..309a1e6020 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t210/parse_t210.c @@ -0,0 +1,741 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * parse_t210.c - The implementation for parsing dev/sdram parameters + */ + +#include "../parse.h" +#include "nvboot_bct_t210.h" + +enum_item s_devtype_table_t210[] = { + { "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc }, + { "NvBootDevType_Spi", nvboot_dev_type_spi }, + { "Sdmmc", nvboot_dev_type_sdmmc }, + { "Spi", nvboot_dev_type_spi }, + { NULL, 0 } +}; + +enum_item s_sdmmc_data_width_table_t210[] = { + { + "NvBootSdmmcDataWidth_4Bit", + nvboot_sdmmc_data_width_4bit + }, + { + "NvBootSdmmcDataWidth_8Bit", + nvboot_sdmmc_data_width_8bit + }, + { "4Bit", nvboot_sdmmc_data_width_4bit }, + { "8Bit", nvboot_sdmmc_data_width_8bit }, + { NULL, 0 } +}; + +enum_item s_spi_clock_source_table_t210[] = { + { "NvBootSpiClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "NvBootSpiClockSource_ClockM", nvboot_spi_clock_source_clockm }, + { "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockSource_ClockM", nvboot_spi_clock_source_clockm }, + { "PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockM", nvboot_spi_clock_source_clockm }, + { NULL, 0 } +}; + +enum_item s_nvboot_memory_type_table_t210[] = { + { "NvBootMemoryType_None", nvboot_memory_type_none }, + { "NvBootMemoryType_Ddr3", nvboot_memory_type_ddr3 }, + { "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 }, + { "NvBootMemoryType_Ddr", nvboot_memory_type_ddr }, + { "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 }, + { "NvBootMemoryType_LpDdr4", nvboot_memory_type_lpddr4 }, + { "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr }, + + { "None", nvboot_memory_type_none }, + { "Ddr3", nvboot_memory_type_ddr3 }, + { "Ddr2", nvboot_memory_type_ddr2 }, + { "Ddr", nvboot_memory_type_ddr }, + { "LpDdr2", nvboot_memory_type_lpddr2 }, + { "LpDdr4", nvboot_memory_type_lpddr4 }, + { "LpDdr", nvboot_memory_type_lpddr }, + + { NULL, 0 } +}; + +#define TOKEN(name) \ + token_##name, field_type_u32, NULL + +field_item s_sdram_field_table_t210[] = { + { "MemoryType", token_memory_type, + field_type_enum, s_nvboot_memory_type_table_t210 }, + + { "PllMInputDivider", TOKEN(pllm_input_divider) }, + { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, + { "PllMStableTime", TOKEN(pllm_stable_time) }, + { "PllMSetupControl", TOKEN(pllm_setup_control) }, + { "PllMPostDivider", TOKEN(pllm_post_divider) }, + { "PllMKCP", TOKEN(pllm_kcp) }, + { "PllMKVCO", TOKEN(pllm_kvco) }, + { "EmcBctSpare0", TOKEN(emc_bct_spare0) }, + { "EmcBctSpare1", TOKEN(emc_bct_spare1) }, + { "EmcBctSpare2", TOKEN(emc_bct_spare2) }, + { "EmcBctSpare3", TOKEN(emc_bct_spare3) }, + { "EmcBctSpare4", TOKEN(emc_bct_spare4) }, + { "EmcBctSpare5", TOKEN(emc_bct_spare5) }, + { "EmcBctSpare6", TOKEN(emc_bct_spare6) }, + { "EmcBctSpare7", TOKEN(emc_bct_spare7) }, + { "EmcBctSpare8", TOKEN(emc_bct_spare8) }, + { "EmcBctSpare9", TOKEN(emc_bct_spare9) }, + { "EmcBctSpare10", TOKEN(emc_bct_spare10) }, + { "EmcBctSpare11", TOKEN(emc_bct_spare11) }, + { "EmcBctSpare12", TOKEN(emc_bct_spare12) }, + { "EmcBctSpare13", TOKEN(emc_bct_spare13) }, + { "EmcClockSource", TOKEN(emc_clock_source) }, + { "EmcClockSourceDll", TOKEN(emc_clock_source_dll) }, + + { "ClkRstControllerPllmMisc2Override", + TOKEN(clk_rst_pllm_misc20_override) }, + { "ClkRstControllerPllmMisc2OverrideEnable", + TOKEN(clk_rst_pllm_misc20_override_enable) }, + { "ClearClk2Mc1", TOKEN(clear_clock2_mc1) }, + + { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, + { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, + { "EmcAutoCalConfig2", TOKEN(emc_auto_cal_config2) }, + { "EmcAutoCalConfig3", TOKEN(emc_auto_cal_config3) }, + { "EmcAutoCalConfig4", TOKEN(emc_auto_cal_config4) }, + { "EmcAutoCalConfig5", TOKEN(emc_auto_cal_config5) }, + { "EmcAutoCalConfig6", TOKEN(emc_auto_cal_config6) }, + { "EmcAutoCalConfig7", TOKEN(emc_auto_cal_config7) }, + { "EmcAutoCalConfig8", TOKEN(emc_auto_cal_config8) }, + + { "EmcAutoCalVrefSel0", TOKEN(emc_auto_cal_vref_sel0) }, + { "EmcAutoCalVrefSel1", TOKEN(emc_auto_cal_vref_sel1) }, + + { "EmcAutoCalChannel", TOKEN(emc_auto_cal_channel) }, + { "EmcPmacroAutocalCfg0", TOKEN(emc_pmacro_auto_cal_cfg0) }, + { "EmcPmacroAutocalCfg1", TOKEN(emc_pmacro_auto_cal_cfg1) }, + { "EmcPmacroAutocalCfg2", TOKEN(emc_pmacro_auto_cal_cfg2) }, + { "EmcPmacroRxTerm", TOKEN(emc_pmacro_rx_term) }, + { "EmcPmacroDqTxDrv", TOKEN(emc_pmacro_dq_tx_drive) }, + { "EmcPmacroCaTxDrv", TOKEN(emc_pmacro_ca_tx_drive) }, + { "EmcPmacroCmdTxDrv", TOKEN(emc_pmacro_cmd_tx_drive) }, + { "EmcPmacroAutocalCfgCommon", TOKEN(emc_pmacro_auto_cal_common) }, + { "EmcPmacroZctrl", TOKEN(emc_pmacro_zcrtl) }, + + { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, + + { "EmcXm2CompPadCtrl", TOKEN(emc_xm2_comp_pad_ctrl) }, + { "EmcXm2CompPadCtrl2", TOKEN(emc_xm2_comp_pad_ctrl2) }, + { "EmcXm2CompPadCtrl3", TOKEN(emc_xm2_comp_pad_ctrl3) }, + + { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, + + { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, + { "EmcPinExtraWait", TOKEN(emc_pin_extra_wait) }, + + { "EmcPinGpioEn", TOKEN(emc_pin_gpio_enable) }, + { "EmcPinGpio", TOKEN(emc_pin_gpio) }, + + { "EmcTimingControlWait", TOKEN(emc_timing_control_wait) }, + + { "EmcRc", TOKEN(emc_rc) }, + { "EmcRfc", TOKEN(emc_rfc) }, + + { "EmcRfcPb", TOKEN(emc_rfc_pb) }, + { "EmcRefctrl2", TOKEN(emc_ref_ctrl2) }, + + { "EmcRfcSlr", TOKEN(emc_rfc_slr) }, + { "EmcRas", TOKEN(emc_ras) }, + { "EmcRp", TOKEN(emc_rp) }, + { "EmcR2r", TOKEN(emc_r2r) }, + { "EmcW2w", TOKEN(emc_w2w) }, + { "EmcR2w", TOKEN(emc_r2w) }, + { "EmcW2r", TOKEN(emc_w2r) }, + { "EmcR2p", TOKEN(emc_r2p) }, + { "EmcW2p", TOKEN(emc_w2p) }, + + { "EmcTppd", TOKEN(emc_tppd) }, + { "EmcCcdmw", TOKEN(emc_ccdmw) }, + + { "EmcRdRcd", TOKEN(emc_rd_rcd) }, + { "EmcWrRcd", TOKEN(emc_wr_rcd) }, + { "EmcRrd", TOKEN(emc_rrd) }, + { "EmcRext", TOKEN(emc_rext) }, + { "EmcWext", TOKEN(emc_wext) }, + { "EmcWdv", TOKEN(emc_wdv) }, + + { "EmcWdvChk", TOKEN(emc_wdv_chk) }, + { "EmcWsv", TOKEN(emc_wsv) }, + { "EmcWev", TOKEN(emc_wev) }, + + { "EmcWdvMask", TOKEN(emc_wdv_mask) }, + + { "EmcWsDuration", TOKEN(emc_ws_duration) }, + { "EmcWeDuration", TOKEN(emc_we_duration) }, + + { "EmcQUse", TOKEN(emc_quse) }, + { "EmcQuseWidth", TOKEN(emc_quse_width) }, + { "EmcIbdly", TOKEN(emc_ibdly) }, + + { "EmcObdly", TOKEN(emc_obdly) }, + + { "EmcEInput", TOKEN(emc_einput) }, + { "EmcEInputDuration", TOKEN(emc_einput_duration) }, + { "EmcPutermExtra", TOKEN(emc_puterm_extra) }, + { "EmcPutermWidth", TOKEN(emc_puterm_width) }, + { "EmcQRst", TOKEN(emc_qrst) }, + { "EmcQSafe", TOKEN(emc_qsafe) }, + { "EmcRdv", TOKEN(emc_rdv) }, + { "EmcRdvMask", TOKEN(emc_rdv_mask) }, + + { "EmcRdvEarly", TOKEN(emc_rdv_early) }, + { "EmcRdvEarlyMask", TOKEN(emc_rdv_early_mask) }, + + { "EmcQpop", TOKEN(emc_qpop) }, + { "EmcRefresh", TOKEN(emc_refresh) }, + { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, + + { "EmcPreRefreshReqCnt", TOKEN(emc_prerefresh_req_cnt) }, + + { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, + { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, + { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, + { "EmcAct2Pden", TOKEN(emc_act2pden) }, + { "EmcAr2Pden", TOKEN(emc_ar2pden) }, + { "EmcRw2Pden", TOKEN(emc_rw2pden) }, + + { "EmcCke2Pden", TOKEN(emc_cke2pden) }, + { "EmcPdex2Cke", TOKEN(emc_pdex2che) }, + { "EmcPdex2Mrr", TOKEN(emc_pdex2mrr) }, + + { "EmcTxsr", TOKEN(emc_txsr) }, + { "EmcTxsrDll", TOKEN(emc_txsr_dll) }, + { "EmcTcke", TOKEN(emc_tcke) }, + { "EmcTckesr", TOKEN(emc_tckesr) }, + { "EmcTpd", TOKEN(emc_tpd) }, + { "EmcTfaw", TOKEN(emc_tfaw) }, + { "EmcTrpab", TOKEN(emc_trpab) }, + { "EmcTClkStable", TOKEN(emc_tclkstable) }, + { "EmcTClkStop", TOKEN(emc_tclkstop) }, + { "EmcTRefBw", TOKEN(emc_trefbw) }, + { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, + { "EmcFbioCfg7", TOKEN(emc_fbio_cfg7) }, + { "EmcFbioCfg8", TOKEN(emc_fbio_cfg8) }, + + { "EmcCmdMappingCmd0_0", TOKEN(emc_cmd_mapping_cmd0_0) }, + { "EmcCmdMappingCmd0_1", TOKEN(emc_cmd_mapping_cmd0_1) }, + { "EmcCmdMappingCmd0_2", TOKEN(emc_cmd_mapping_cmd0_2) }, + { "EmcCmdMappingCmd1_0", TOKEN(emc_cmd_mapping_cmd1_0) }, + { "EmcCmdMappingCmd1_1", TOKEN(emc_cmd_mapping_cmd1_1) }, + { "EmcCmdMappingCmd1_2", TOKEN(emc_cmd_mapping_cmd1_2) }, + { "EmcCmdMappingCmd2_0", TOKEN(emc_cmd_mapping_cmd2_0) }, + { "EmcCmdMappingCmd2_1", TOKEN(emc_cmd_mapping_cmd2_1) }, + { "EmcCmdMappingCmd2_2", TOKEN(emc_cmd_mapping_cmd2_2) }, + { "EmcCmdMappingCmd3_0", TOKEN(emc_cmd_mapping_cmd3_0) }, + { "EmcCmdMappingCmd3_1", TOKEN(emc_cmd_mapping_cmd3_1) }, + { "EmcCmdMappingCmd3_2", TOKEN(emc_cmd_mapping_cmd3_2) }, + { "EmcCmdMappingByte", TOKEN(emc_cmd_mapping_byte) }, + + { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, + { "EmcCfgRsv", TOKEN(emc_cfg_rsv) }, + { "EmcMrs", TOKEN(emc_mrs) }, + + { "EmcEmrs", TOKEN(emc_emrs) }, + + { "EmcEmrs2", TOKEN(emc_emrs2) }, + { "EmcEmrs3", TOKEN(emc_emrs3) }, + { "EmcMrw1", TOKEN(emc_mrw1) }, + { "EmcMrw2", TOKEN(emc_mrw2) }, + { "EmcMrw3", TOKEN(emc_mrw3) }, + { "EmcMrw4", TOKEN(emc_mrw4) }, + + { "EmcMrw6", TOKEN(emc_mrw6) }, + { "EmcMrw8", TOKEN(emc_mrw8) }, + { "EmcMrw9", TOKEN(emc_mrw9) }, + { "EmcMrw10", TOKEN(emc_mrw10) }, + { "EmcMrw12", TOKEN(emc_mrw12) }, + { "EmcMrw13", TOKEN(emc_mrw13) }, + { "EmcMrw14", TOKEN(emc_mrw14) }, + + { "EmcMrwExtra", TOKEN(emc_mrw_extra) }, + { "EmcWarmBootMrwExtra", TOKEN(emc_warm_boot_mrw_extra) }, + { "EmcWarmBootExtraModeRegWriteEnable", + TOKEN(emc_warm_boot_extramode_reg_write_enable) }, + { "EmcExtraModeRegWriteEnable", TOKEN(emc_extramode_reg_write_enable) }, + { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, + { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, + { "EmcMrsWaitCnt", TOKEN(emc_mrs_wait_cnt) }, + { "EmcMrsWaitCnt2", TOKEN(emc_mrs_wait_cnt2) }, + { "EmcCfg", TOKEN(emc_cfg) }, + { "EmcCfg2", TOKEN(emc_cfg2) }, + { "EmcCfgPipe", TOKEN(emc_cfg_pipe) }, + + { "EmcCfgPipeClk", TOKEN(emc_cfg_pipe_clk) }, + { "EmcFdpdCtrlCmdNoRamp", TOKEN(emc_fdpd_ctrl_cmd_no_ramp) }, + { "EmcCfgUpdate", TOKEN(emc_cfg_update) }, + + { "EmcDbg", TOKEN(emc_dbg) }, + { "EmcDbgWriteMux", TOKEN(emc_dbg_write_mux) }, + + { "EmcCmdQ", TOKEN(emc_cmd_q) }, + { "EmcMc2EmcQ", TOKEN(emc_mc2emc_q) }, + { "EmcDynSelfRefControl", TOKEN(emc_dyn_self_ref_control) }, + { "AhbArbitrationXbarCtrlMemInitDone", + TOKEN(ahb_arbitration_xbar_ctrl_meminit_done) }, + { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, + + { "EmcCfgDigDll_1", TOKEN(emc_cfg_dig_dll_1) }, + + { "EmcCfgDigDllPeriod", TOKEN(emc_cfg_dig_dll_period) }, + { "EmcDevSelect", TOKEN(emc_dev_select) }, + { "EmcSelDpdCtrl", TOKEN(emc_sel_dpd_ctrl) }, + + { "EmcFdpdCtrlDq", TOKEN(emc_fdpd_ctrl_dq) }, + { "EmcFdpdCtrlCmd", TOKEN(emc_fdpd_ctrl_cmd) }, + { "EmcPmacroIbVrefDq_0", TOKEN(emc_pmacro_ib_vref_dq_0) }, + { "EmcPmacroIbVrefDq_1", TOKEN(emc_pmacro_ib_vref_dq_1) }, + { "EmcPmacroIbVrefDqs_0", TOKEN(emc_pmacro_ib_vref_dqs_0) }, + { "EmcPmacroIbVrefDqs_1", TOKEN(emc_pmacro_ib_vref_dqs_1) }, + { "EmcPmacroIbRxrt", TOKEN(emc_pmacro_ib_rxrt) }, + { "EmcCfgPipe1", TOKEN(emc_cfg_pipe1) }, + { "EmcCfgPipe2", TOKEN(emc_cfg_pipe2) }, + { "EmcPmacroQuseDdllRank0_0", TOKEN(emc_pmacro_quse_ddll_rank0_0) }, + { "EmcPmacroQuseDdllRank0_1", TOKEN(emc_pmacro_quse_ddll_rank0_1) }, + { "EmcPmacroQuseDdllRank0_2", TOKEN(emc_pmacro_quse_ddll_rank0_2) }, + { "EmcPmacroQuseDdllRank0_3", TOKEN(emc_pmacro_quse_ddll_rank0_3) }, + { "EmcPmacroQuseDdllRank0_4", TOKEN(emc_pmacro_quse_ddll_rank0_4) }, + { "EmcPmacroQuseDdllRank0_5", TOKEN(emc_pmacro_quse_ddll_rank0_5) }, + { "EmcPmacroQuseDdllRank1_0", TOKEN(emc_pmacro_quse_ddll_rank1_0) }, + { "EmcPmacroQuseDdllRank1_1", TOKEN(emc_pmacro_quse_ddll_rank1_1) }, + { "EmcPmacroQuseDdllRank1_2", TOKEN(emc_pmacro_quse_ddll_rank1_2) }, + { "EmcPmacroQuseDdllRank1_3", TOKEN(emc_pmacro_quse_ddll_rank1_3) }, + { "EmcPmacroQuseDdllRank1_4", TOKEN(emc_pmacro_quse_ddll_rank1_4) }, + { "EmcPmacroQuseDdllRank1_5", TOKEN(emc_pmacro_quse_ddll_rank1_5) }, + { "EmcPmacroObDdllLongDqRank0_0", TOKEN(emc_pmacro_ob_ddll_long_dq_rank0_0) }, + { "EmcPmacroObDdllLongDqRank0_1", TOKEN(emc_pmacro_ob_ddll_long_dq_rank0_1) }, + { "EmcPmacroObDdllLongDqRank0_2", TOKEN(emc_pmacro_ob_ddll_long_dq_rank0_2) }, + { "EmcPmacroObDdllLongDqRank0_3", TOKEN(emc_pmacro_ob_ddll_long_dq_rank0_3) }, + { "EmcPmacroObDdllLongDqRank0_4", TOKEN(emc_pmacro_ob_ddll_long_dq_rank0_4) }, + { "EmcPmacroObDdllLongDqRank0_5", TOKEN(emc_pmacro_ob_ddll_long_dq_rank0_5) }, + { "EmcPmacroObDdllLongDqRank1_0", TOKEN(emc_pmacro_ob_ddll_long_dq_rank1_0) }, + { "EmcPmacroObDdllLongDqRank1_1", TOKEN(emc_pmacro_ob_ddll_long_dq_rank1_1) }, + { "EmcPmacroObDdllLongDqRank1_2", TOKEN(emc_pmacro_ob_ddll_long_dq_rank1_2) }, + { "EmcPmacroObDdllLongDqRank1_3", TOKEN(emc_pmacro_ob_ddll_long_dq_rank1_3) }, + { "EmcPmacroObDdllLongDqRank1_4", TOKEN(emc_pmacro_ob_ddll_long_dq_rank1_4) }, + { "EmcPmacroObDdllLongDqRank1_5", TOKEN(emc_pmacro_ob_ddll_long_dq_rank1_5) }, + { "EmcPmacroObDdllLongDqsRank0_0", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank0_0) }, + { "EmcPmacroObDdllLongDqsRank0_1", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank0_1) }, + { "EmcPmacroObDdllLongDqsRank0_2", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank0_2) }, + { "EmcPmacroObDdllLongDqsRank0_3", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank0_3) }, + { "EmcPmacroObDdllLongDqsRank0_4", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank0_4) }, + { "EmcPmacroObDdllLongDqsRank0_5", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank0_5) }, + { "EmcPmacroObDdllLongDqsRank1_0", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank1_0) }, + { "EmcPmacroObDdllLongDqsRank1_1", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank1_1) }, + { "EmcPmacroObDdllLongDqsRank1_2", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank1_2) }, + { "EmcPmacroObDdllLongDqsRank1_3", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank1_3) }, + { "EmcPmacroObDdllLongDqsRank1_4", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank1_4) }, + { "EmcPmacroObDdllLongDqsRank1_5", TOKEN(emc_pmacro_ob_ddll_long_dqs_rank1_5) }, + + { "EmcPmacroIbDdllLongDqsRank0_0", TOKEN(emc_pmacro_ib_ddll_long_dqs_rank0_0) }, + { "EmcPmacroIbDdllLongDqsRank0_1", TOKEN(emc_pmacro_ib_ddll_long_dqs_rank0_1) }, + { "EmcPmacroIbDdllLongDqsRank0_2", TOKEN(emc_pmacro_ib_ddll_long_dqs_rank0_2) }, + { "EmcPmacroIbDdllLongDqsRank0_3", TOKEN(emc_pmacro_ib_ddll_long_dqs_rank0_3) }, + { "EmcPmacroIbDdllLongDqsRank1_0", TOKEN(emc_pmacro_ib_ddll_long_dqs_rank1_0) }, + { "EmcPmacroIbDdllLongDqsRank1_1", TOKEN(emc_pmacro_ib_ddll_long_dqs_rank1_1) }, + { "EmcPmacroIbDdllLongDqsRank1_2", TOKEN(emc_pmacro_ib_ddll_long_dqs_rank1_2) }, + { "EmcPmacroIbDdllLongDqsRank1_3", TOKEN(emc_pmacro_ib_ddll_long_dqs_rank1_3) }, + + { "EmcPmacroDdllLongCmd_0", TOKEN(emc_pmacro_ddll_long_cmd_0) }, + { "EmcPmacroDdllLongCmd_1", TOKEN(emc_pmacro_ddll_long_cmd_1) }, + { "EmcPmacroDdllLongCmd_2", TOKEN(emc_pmacro_ddll_long_cmd_2) }, + { "EmcPmacroDdllLongCmd_3", TOKEN(emc_pmacro_ddll_long_cmd_3) }, + { "EmcPmacroDdllLongCmd_4", TOKEN(emc_pmacro_ddll_long_cmd_4) }, + { "EmcPmacroDdllShortCmd_0", TOKEN(emc_pmacro_ddll_short_cmd_0) }, + { "EmcPmacroDdllShortCmd_1", TOKEN(emc_pmacro_ddll_short_cmd_1) }, + { "EmcPmacroDdllShortCmd_2", TOKEN(emc_pmacro_ddll_short_cmd_2) }, + + { "WarmBootWait", TOKEN(warm_boot_wait) }, + { "EmcOdtWrite", TOKEN(emc_odt_write) }, + { "EmcZcalInterval", TOKEN(emc_zcal_interval) }, + { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, + { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, + { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, + + + { "EmcZcalInitDev0", TOKEN(emc_zcal_init_dev0) }, + { "EmcZcalInitDev1", TOKEN(emc_zcal_init_dev1) }, + { "EmcZcalInitWait", TOKEN(emc_zcal_init_wait) }, + { "EmcZcalWarmColdBootEnables", TOKEN(emc_zcal_warm_cold_boot_enables) }, + { "EmcMrwLpddr2ZcalWarmBoot", TOKEN(emc_mrw_lpddr2zcal_warm_boot) }, + { "EmcZqCalDdr3WarmBoot", TOKEN(emc_zqcal_ddr3_warm_boot) }, + + { "EmcZqCalLpDdr4WarmBoot", TOKEN(emc_zqcal_lpddr4_warm_boot) }, + + { "EmcZcalWarmBootWait", TOKEN(emc_zcal_warm_boot_wait) }, + { "EmcMrsWarmBootEnable", TOKEN(emc_mrs_warm_boot_enable) }, + + { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, + + { "EmcMrsExtra", TOKEN(emc_mrs_extra) }, + { "EmcWarmBootMrsExtra", TOKEN(emc_warm_boot_mrs_extra) }, + + { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, + { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, + { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, + + { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, + { "EmcClkenOverride", TOKEN(emc_clken_override) }, + { "EmcExtraRefreshNum", TOKEN(emc_extra_refresh_num) }, + { "EmcClkenOverrideAllWarmBoot", + TOKEN(emc_clken_override_allwarm_boot) }, + { "McClkenOverrideAllWarmBoot", TOKEN(mc_clken_override_allwarm_boot) }, + { "EmcCfgDigDllPeriodWarmBoot", + TOKEN(emc_cfg_dig_dll_period_warm_boot) }, + { "PmcVddpSel", TOKEN(pmc_vddp_sel) }, + { "PmcVddpSelWait", TOKEN(pmc_vddp_sel_wait) }, + { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, + { "PmcDdrCfg", TOKEN(pmc_ddr_cfg) }, + { "PmcIoDpd3Req", TOKEN(pmc_io_dpd3_req) }, + { "PmcIoDpd3ReqWait", TOKEN(pmc_io_dpd3_req_wait) }, + + { "PmcIoDpd4ReqWait", TOKEN(pmc_io_dpd4_req_wait) }, + + { "PmcRegShort", TOKEN(pmc_reg_short) }, + { "PmcNoIoPower", TOKEN(pmc_no_io_power) }, + + { "PmcDdrCntrlWait", TOKEN(pmc_ddr_ctrl_wait) }, + { "PmcDdrCntrl", TOKEN(pmc_ddr_ctrl) }, + + { "EmcAcpdControl", TOKEN(emc_acpd_control) }, + { "EmcSwizzleRank0Byte0", TOKEN(emc_swizzle_rank0_byte0) }, + { "EmcSwizzleRank0Byte1", TOKEN(emc_swizzle_rank0_byte1) }, + { "EmcSwizzleRank0Byte2", TOKEN(emc_swizzle_rank0_byte2) }, + { "EmcSwizzleRank0Byte3", TOKEN(emc_swizzle_rank0_byte3) }, + { "EmcSwizzleRank1Byte0", TOKEN(emc_swizzle_rank1_byte0) }, + { "EmcSwizzleRank1Byte1", TOKEN(emc_swizzle_rank1_byte1) }, + { "EmcSwizzleRank1Byte2", TOKEN(emc_swizzle_rank1_byte2) }, + { "EmcSwizzleRank1Byte3", TOKEN(emc_swizzle_rank1_byte3) }, + + { "EmcTxdsrvttgen", TOKEN(emc_txdsrvttgen) }, + + { "EmcDataBrlshft0", TOKEN(emc_data_brlshft0) }, + { "EmcDataBrlshft1", TOKEN(emc_data_brlshft1) }, + { "EmcDqsBrlshft0", TOKEN(emc_dqs_brlshft0) }, + { "EmcDqsBrlshft1", TOKEN(emc_dqs_brlshft1) }, + { "EmcCmdBrlshft0", TOKEN(emc_cmd_brlshft0) }, + { "EmcCmdBrlshft1", TOKEN(emc_cmd_brlshft1) }, + { "EmcCmdBrlshft2", TOKEN(emc_cmd_brlshft2) }, + { "EmcCmdBrlshft3", TOKEN(emc_cmd_brlshft3) }, + + { "EmcQuseBrlshft0", TOKEN(emc_quse_brlshft0) }, + { "EmcQuseBrlshft1", TOKEN(emc_quse_brlshft1) }, + { "EmcQuseBrlshft2", TOKEN(emc_quse_brlshft2) }, + { "EmcQuseBrlshft3", TOKEN(emc_quse_brlshft3) }, + + { "EmcDllCfg0", TOKEN(emc_dll_cfg0) }, + { "EmcDllCfg1", TOKEN(emc_dll_cfg1) }, + + { "EmcPmcScratch1", TOKEN(emc_pmc_scratch1) }, + { "EmcPmcScratch2", TOKEN(emc_pmc_scratch2) }, + { "EmcPmcScratch3", TOKEN(emc_pmc_scratch3) }, + + { "EmcPmacroPadCfgCtrl", TOKEN(emc_pmacro_pad_cfg_ctrl) }, + + { "EmcPmacroVttgenCtrl0", TOKEN(emc_pmacro_vttgen_ctrl0) }, + { "EmcPmacroVttgenCtrl1", TOKEN(emc_pmacro_vttgen_ctrl1) }, + { "EmcPmacroVttgenCtrl2", TOKEN(emc_pmacro_vttgen_ctrl2) }, + + { "EmcPmacroBrickCtrlRfu1", TOKEN(emc_pmacro_brick_ctrl_rfu1) }, + { "EmcPmacroCmdBrickCtrlFdpd", TOKEN(emc_pmacro_cmd_brick_ctrl_fdpd) }, + + { "EmcPmacroBrickCtrlRfu2", TOKEN(emc_pmacro_brick_ctrl_rfu2) }, + { "EmcPmacroDataBrickCtrlFdpd", TOKEN(emc_pmacro_data_brick_ctrl_fdpd) }, + + { "EmcPmacroBgBiasCtrl0", TOKEN(emc_pmacro_bg_bias_ctrl0) }, + { "EmcPmacroDataPadRxCtrl", TOKEN(emc_pmacro_data_pad_rx_ctrl) }, + { "EmcPmacroCmdPadRxCtrl", TOKEN(emc_pmacro_cmd_pad_rx_ctrl) }, + { "EmcPmacroDataRxTermMode", TOKEN(emc_pmacro_data_rx_term_mode) }, + + { "EmcPmacroCmdRxTermMode", TOKEN(emc_pmacro_cmd_rx_term_mode) }, + { "EmcPmacroDataPadTxCtrl", TOKEN(emc_pmacro_data_pad_tx_ctrl) }, + { "EmcPmacroCommonPadTxCtrl", TOKEN(emc_pmacro_common_pad_tx_ctrl) }, + { "EmcPmacroCmdPadTxCtrl", TOKEN(emc_pmacro_cmd_pad_tx_ctrl) }, + + { "EmcCfg3", TOKEN(emc_cfg3) }, + + { "EmcPmacroTxPwrd0", TOKEN(emc_pmacro_tx_pwrd0) }, + { "EmcPmacroTxPwrd1", TOKEN(emc_pmacro_tx_pwrd1) }, + { "EmcPmacroTxPwrd2", TOKEN(emc_pmacro_tx_pwrd2) }, + { "EmcPmacroTxPwrd3", TOKEN(emc_pmacro_tx_pwrd3) }, + { "EmcPmacroTxPwrd4", TOKEN(emc_pmacro_tx_pwrd4) }, + { "EmcPmacroTxPwrd5", TOKEN(emc_pmacro_tx_pwrd5) }, + + { "EmcConfigSampleDelay", TOKEN(emc_config_sample_delay) }, + + { "EmcPmacroBrickMapping0", TOKEN(emc_pmacro_brick_mapping0) }, + { "EmcPmacroBrickMapping1", TOKEN(emc_pmacro_brick_mapping1) }, + { "EmcPmacroBrickMapping2", TOKEN(emc_pmacro_brick_mapping2) }, + + { "EmcPmacroTxSelClkSrc0", TOKEN(emc_pmacro_tx_sel_clk_src0) }, + { "EmcPmacroTxSelClkSrc1", TOKEN(emc_pmacro_tx_sel_clk_src1) }, + { "EmcPmacroTxSelClkSrc2", TOKEN(emc_pmacro_tx_sel_clk_src2) }, + { "EmcPmacroTxSelClkSrc3", TOKEN(emc_pmacro_tx_sel_clk_src3) }, + { "EmcPmacroTxSelClkSrc4", TOKEN(emc_pmacro_tx_sel_clk_src4) }, + { "EmcPmacroTxSelClkSrc5", TOKEN(emc_pmacro_tx_sel_clk_src5) }, + + { "EmcPmacroDdllBypass", TOKEN(emc_pmacro_ddll_bypass) }, + + { "EmcPmacroDdllPwrd0", TOKEN(emc_pmacro_ddll_pwrd0) }, + { "EmcPmacroDdllPwrd1", TOKEN(emc_pmacro_ddll_pwrd1) }, + { "EmcPmacroDdllPwrd2", TOKEN(emc_pmacro_ddll_pwrd2) }, + + { "EmcPmacroCmdCtrl0", TOKEN(emc_pmacro_cmd_ctrl0) }, + { "EmcPmacroCmdCtrl1", TOKEN(emc_pmacro_cmd_ctrl1) }, + { "EmcPmacroCmdCtrl2", TOKEN(emc_pmacro_cmd_ctrl2) }, + + { "McEmemAdrCfg", TOKEN(mc_emem_adr_cfg) }, + { "McEmemAdrCfgDev0", TOKEN(mc_emem_adr_cfg_dev0) }, + { "McEmemAdrCfgDev1", TOKEN(mc_emem_adr_cfg_dev1) }, + { "McEmemAdrCfgChannelMask", TOKEN(mc_emem_adr_cfg_channel_mask) }, + { "McEmemAdrCfgBankMask0", TOKEN(mc_emem_adr_cfg_bank_mask0) }, + { "McEmemAdrCfgBankMask1", TOKEN(mc_emem_adr_cfg_bank_mask1) }, + { "McEmemAdrCfgBankMask2", TOKEN(mc_emem_adr_cfg_bank_mask2) }, + + { "McEmemCfg", TOKEN(mc_emem_cfg) }, + { "McEmemArbCfg", TOKEN(mc_emem_arb_cfg) }, + { "McEmemArbOutstandingReq", TOKEN(mc_emem_arb_outstanding_req) }, + + { "McEmemArbRefpbHpCtrl", TOKEN(emc_emem_arb_refpb_hp_ctrl) }, + { "McEmemArbRefpbBankCtrl", TOKEN(emc_emem_arb_refpb_bank_ctrl) }, + + { "McEmemArbTimingRcd", TOKEN(mc_emem_arb_timing_rcd) }, + { "McEmemArbTimingRp", TOKEN(mc_emem_arb_timing_rp) }, + { "McEmemArbTimingRc", TOKEN(mc_emem_arb_timing_rc) }, + { "McEmemArbTimingRas", TOKEN(mc_emem_arb_timing_ras) }, + { "McEmemArbTimingFaw", TOKEN(mc_emem_arb_timing_faw) }, + { "McEmemArbTimingRrd", TOKEN(mc_emem_arb_timing_rrd) }, + { "McEmemArbTimingRap2Pre", TOKEN(mc_emem_arb_timing_rap2pre) }, + { "McEmemArbTimingWap2Pre", TOKEN(mc_emem_arb_timing_wap2pre) }, + { "McEmemArbTimingR2R", TOKEN(mc_emem_arb_timing_r2r) }, + { "McEmemArbTimingW2W", TOKEN(mc_emem_arb_timing_w2w) }, + { "McEmemArbTimingR2W", TOKEN(mc_emem_arb_timing_r2w) }, + { "McEmemArbTimingW2R", TOKEN(mc_emem_arb_timing_w2r) }, + + { "McEmemArbTimingRFCPB", TOKEN(mc_emem_arb_timing_rfcpb) }, + + { "McEmemArbDaTurns", TOKEN(mc_emem_arb_da_turns) }, + { "McEmemArbDaCovers", TOKEN(mc_emem_arb_da_covers) }, + { "McEmemArbMisc0", TOKEN(mc_emem_arb_misc0) }, + { "McEmemArbMisc1", TOKEN(mc_emem_arb_misc1) }, + { "McEmemArbMisc2", TOKEN(mc_emem_arb_misc2) }, + { "McEmemArbRing1Throttle", TOKEN(mc_emem_arb_ring1_throttle) }, + { "McEmemArbOverride", TOKEN(mc_emem_arb_override) }, + { "McEmemArbOverride1", TOKEN(mc_emem_arb_override1) }, + { "McEmemArbRsv", TOKEN(mc_emem_arb_rsv) }, + + { "McDaCfg0", TOKEN(mc_da_cfg0) }, + { "McEmemArbTimingCcdmw", TOKEN(mc_emem_arb_timing_ccdmw) }, + + { "McClkenOverride", TOKEN(mc_clken_override) }, + { "McStatControl", TOKEN(mc_stat_control) }, + { "McVideoProtectBom", TOKEN(mc_video_protect_bom) }, + { "McVideoProtectBomAdrHi", + TOKEN(mc_video_protect_bom_adr_hi) }, + { "McVideoProtectSizeMb", TOKEN(mc_video_protect_size_mb) }, + { "McVideoProtectVprOverride", TOKEN(mc_video_protect_vpr_override) }, + { "McVideoProtectVprOverride1", TOKEN(mc_video_protect_vpr_override1) }, + { "McVideoProtectGpuOverride0", TOKEN(mc_video_protect_gpu_override0) }, + { "McVideoProtectGpuOverride1", TOKEN(mc_video_protect_gpu_override1) }, + { "McSecCarveoutBom", TOKEN(mc_sec_carveout_bom) }, + { "McSecCarveoutAdrHi", TOKEN(mc_sec_carveout_adr_hi) }, + { "McSecCarveoutSizeMb", TOKEN(mc_sec_carveout_size_mb) }, + { "McVideoProtectWriteAccess", TOKEN(mc_video_protect_write_access) }, + { "McSecCarveoutProtectWriteAccess", + TOKEN(mc_sec_carveout_protect_write_access) }, + + { "McGeneralizedCarveout1Bom", TOKEN(mc_generalized_carveout1_bom) }, + { "McGeneralizedCarveout1BomHi",TOKEN(mc_generalized_carveout1_bom_hi) }, + { "McGeneralizedCarveout1Size128kb", + TOKEN(mc_generalized_carveout1_size_128kb) }, + { "McGeneralizedCarveout1Access0", + TOKEN(mc_generalized_carveout1_access0) }, + { "McGeneralizedCarveout1Access1", + TOKEN(mc_generalized_carveout1_access1) }, + { "McGeneralizedCarveout1Access2", + TOKEN(mc_generalized_carveout1_access2) }, + { "McGeneralizedCarveout1Access3", + TOKEN(mc_generalized_carveout1_access3) }, + { "McGeneralizedCarveout1Access4", + TOKEN(mc_generalized_carveout1_access4) }, + { "McGeneralizedCarveout1ForceInternalAccess0", + TOKEN(mc_generalized_carveout1_force_internal_access0) }, + { "McGeneralizedCarveout1ForceInternalAccess1", + TOKEN(mc_generalized_carveout1_force_internal_access1) }, + { "McGeneralizedCarveout1ForceInternalAccess2", + TOKEN(mc_generalized_carveout1_force_internal_access2) }, + { "McGeneralizedCarveout1ForceInternalAccess3", + TOKEN(mc_generalized_carveout1_force_internal_access3) }, + { "McGeneralizedCarveout1ForceInternalAccess4", + TOKEN(mc_generalized_carveout1_force_internal_access4) }, + { "McGeneralizedCarveout1Cfg0", TOKEN(mc_generalized_carveout1_cfg0) }, + + { "McGeneralizedCarveout2Bom", TOKEN(mc_generalized_carveout2_bom) }, + { "McGeneralizedCarveout2BomHi",TOKEN(mc_generalized_carveout2_bom_hi) }, + { "McGeneralizedCarveout2Size128kb", + TOKEN(mc_generalized_carveout2_size_128kb) }, + { "McGeneralizedCarveout2Access0", + TOKEN(mc_generalized_carveout2_access0) }, + { "McGeneralizedCarveout2Access1", + TOKEN(mc_generalized_carveout2_access1) }, + { "McGeneralizedCarveout2Access2", + TOKEN(mc_generalized_carveout2_access2) }, + { "McGeneralizedCarveout2Access3", + TOKEN(mc_generalized_carveout2_access3) }, + { "McGeneralizedCarveout2Access4", + TOKEN(mc_generalized_carveout2_access4) }, + { "McGeneralizedCarveout2ForceInternalAccess0", + TOKEN(mc_generalized_carveout2_force_internal_access0) }, + { "McGeneralizedCarveout2ForceInternalAccess1", + TOKEN(mc_generalized_carveout2_force_internal_access1) }, + { "McGeneralizedCarveout2ForceInternalAccess2", + TOKEN(mc_generalized_carveout2_force_internal_access2) }, + { "McGeneralizedCarveout2ForceInternalAccess3", + TOKEN(mc_generalized_carveout2_force_internal_access3) }, + { "McGeneralizedCarveout2ForceInternalAccess4", + TOKEN(mc_generalized_carveout2_force_internal_access4) }, + { "McGeneralizedCarveout2Cfg0", TOKEN(mc_generalized_carveout2_cfg0) }, + + { "McGeneralizedCarveout3Bom", TOKEN(mc_generalized_carveout3_bom) }, + { "McGeneralizedCarveout3BomHi",TOKEN(mc_generalized_carveout3_bom_hi) }, + { "McGeneralizedCarveout3Size128kb", + TOKEN(mc_generalized_carveout3_size_128kb) }, + { "McGeneralizedCarveout3Access0", + TOKEN(mc_generalized_carveout3_access0) }, + { "McGeneralizedCarveout3Access1", + TOKEN(mc_generalized_carveout3_access1) }, + { "McGeneralizedCarveout3Access2", + TOKEN(mc_generalized_carveout3_access2) }, + { "McGeneralizedCarveout3Access3", + TOKEN(mc_generalized_carveout3_access3) }, + { "McGeneralizedCarveout3Access4", + TOKEN(mc_generalized_carveout3_access4) }, + { "McGeneralizedCarveout3ForceInternalAccess0", + TOKEN(mc_generalized_carveout3_force_internal_access0) }, + { "McGeneralizedCarveout3ForceInternalAccess1", + TOKEN(mc_generalized_carveout3_force_internal_access1) }, + { "McGeneralizedCarveout3ForceInternalAccess2", + TOKEN(mc_generalized_carveout3_force_internal_access2) }, + { "McGeneralizedCarveout3ForceInternalAccess3", + TOKEN(mc_generalized_carveout3_force_internal_access3) }, + { "McGeneralizedCarveout3ForceInternalAccess4", + TOKEN(mc_generalized_carveout3_force_internal_access4) }, + { "McGeneralizedCarveout3Cfg0", TOKEN(mc_generalized_carveout3_cfg0) }, + + { "McGeneralizedCarveout4Bom", TOKEN(mc_generalized_carveout4_bom) }, + { "McGeneralizedCarveout4BomHi",TOKEN(mc_generalized_carveout4_bom_hi) }, + { "McGeneralizedCarveout4Size128kb", + TOKEN(mc_generalized_carveout4_size_128kb) }, + { "McGeneralizedCarveout4Access0", + TOKEN(mc_generalized_carveout4_access0) }, + { "McGeneralizedCarveout4Access1", + TOKEN(mc_generalized_carveout4_access1) }, + { "McGeneralizedCarveout4Access2", + TOKEN(mc_generalized_carveout4_access2) }, + { "McGeneralizedCarveout4Access3", + TOKEN(mc_generalized_carveout4_access3) }, + { "McGeneralizedCarveout4Access4", + TOKEN(mc_generalized_carveout4_access4) }, + { "McGeneralizedCarveout4ForceInternalAccess0", + TOKEN(mc_generalized_carveout4_force_internal_access0) }, + { "McGeneralizedCarveout4ForceInternalAccess1", + TOKEN(mc_generalized_carveout4_force_internal_access1) }, + { "McGeneralizedCarveout4ForceInternalAccess2", + TOKEN(mc_generalized_carveout4_force_internal_access2) }, + { "McGeneralizedCarveout4ForceInternalAccess3", + TOKEN(mc_generalized_carveout4_force_internal_access3) }, + { "McGeneralizedCarveout4ForceInternalAccess4", + TOKEN(mc_generalized_carveout4_force_internal_access4) }, + { "McGeneralizedCarveout4Cfg0", TOKEN(mc_generalized_carveout4_cfg0) }, + + { "McGeneralizedCarveout5Bom", TOKEN(mc_generalized_carveout5_bom) }, + { "McGeneralizedCarveout5BomHi",TOKEN(mc_generalized_carveout5_bom_hi) }, + { "McGeneralizedCarveout5Size128kb", + TOKEN(mc_generalized_carveout5_size_128kb) }, + { "McGeneralizedCarveout5Access0", + TOKEN(mc_generalized_carveout5_access0) }, + { "McGeneralizedCarveout5Access1", + TOKEN(mc_generalized_carveout5_access1) }, + { "McGeneralizedCarveout5Access2", + TOKEN(mc_generalized_carveout5_access2) }, + { "McGeneralizedCarveout5Access3", + TOKEN(mc_generalized_carveout5_access3) }, + { "McGeneralizedCarveout5Access4", + TOKEN(mc_generalized_carveout5_access4) }, + { "McGeneralizedCarveout5ForceInternalAccess0", + TOKEN(mc_generalized_carveout5_force_internal_access0) }, + { "McGeneralizedCarveout5ForceInternalAccess1", + TOKEN(mc_generalized_carveout5_force_internal_access1) }, + { "McGeneralizedCarveout5ForceInternalAccess2", + TOKEN(mc_generalized_carveout5_force_internal_access2) }, + { "McGeneralizedCarveout5ForceInternalAccess3", + TOKEN(mc_generalized_carveout5_force_internal_access3) }, + { "McGeneralizedCarveout5ForceInternalAccess4", + TOKEN(mc_generalized_carveout5_force_internal_access4) }, + { "McGeneralizedCarveout5Cfg0", TOKEN(mc_generalized_carveout5_cfg0) }, + + { "EmcCaTrainingEnable", TOKEN(emc_ca_training_enable) }, + { "SwizzleRankByteEncode", TOKEN(swizzle_rank_byte_encode) }, + { "BootRomPatchControl", TOKEN(boot_rom_patch_control) }, + { "BootRomPatchData", TOKEN(boot_rom_patch_data) }, + + { "McMtsCarveoutBom", TOKEN(mc_mts_carveout_bom) }, + { "McMtsCarveoutAdrHi", TOKEN(mc_mts_carveout_adr_hi) }, + { "McMtsCarveoutSizeMb", TOKEN(mc_mts_carveout_size_mb) }, + { "McMtsCarveoutRegCtrl", TOKEN(mc_mts_carveout_reg_ctrl) }, + { NULL, 0, 0, NULL } +}; + +field_item s_sdmmc_table_t210[] = { + { "ClockDivider", TOKEN(sdmmc_clock_divider) }, + { "DataWidth", + token_sdmmc_data_width, + field_type_enum, + s_sdmmc_data_width_table_t210 }, + { "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) }, + { "MultiPageSupport", TOKEN(sdmmc_multi_page_support) }, + { NULL, 0, 0, NULL } +}; + +field_item s_spiflash_table_t210[] = { + { "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) }, + { "PageSize2kor16k", TOKEN(spiflash_page_size_2k_or_16k) }, + { "ClockDivider", TOKEN(spiflash_clock_divider) }, + { "ClockSource", + token_spiflash_clock_source, + field_type_enum, + s_spi_clock_source_table_t210 }, + { NULL, 0, 0, NULL } +}; + +parse_subfield_item s_device_type_table_t210[] = { + { "SdmmcParams.", token_sdmmc_params, + s_sdmmc_table_t210, t210_set_dev_param }, + { "SpiFlashParams.", token_spiflash_params, + s_spiflash_table_t210, t210_set_dev_param }, + { NULL, 0, NULL } +}; diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t30/nvbctlib_t30.c b/firmware/coreboot/util/nvidia/cbootimage/src/t30/nvbctlib_t30.c new file mode 100644 index 0000000000..2cb7ab88bb --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t30/nvbctlib_t30.c @@ -0,0 +1,936 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include "../cbootimage.h" +#include "../parse.h" +#include "../crypto.h" +#include "nvboot_bct_t30.h" +#include "string.h" + +/* nvbctlib_t30.c: The implementation of the nvbctlib API for t30. */ + +/* Definitions that simplify the code which follows. */ +#define CASE_GET_SDRAM_PARAM(x) \ +case token_##x:\ + *value = params->x; \ + break + +#define CASE_SET_SDRAM_PARAM(x) \ +case token_##x:\ + params->x = value; \ + break + +#define CASE_GET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + *value = bct->dev_params[index].dev##_params.x; \ + break + +#define CASE_SET_DEV_PARAM(dev, x) \ +case token_##dev##_##x:\ + bct->dev_params[index].dev##_params.x = value; \ + break + +#define CASE_GET_BL_PARAM(x) \ +case token_bl_##x:\ + *data = bct_ptr->bootloader[set].x; \ + break + +#define CASE_SET_BL_PARAM(x) \ +case token_bl_##x:\ + bct_ptr->bootloader[set].x = *data; \ + break + +#define CASE_GET_NVU32(id) \ +case token_##id:\ + if (bct == NULL) return -ENODATA; \ + *((uint32_t *)data) = bct_ptr->id; \ + break + +#define CASE_GET_CONST(id, val) \ +case token_##id:\ + *((uint32_t *)data) = val; \ + break + +#define CASE_GET_CONST_PREFIX(id, val_prefix) \ +case token_##id:\ + *((uint32_t *)data) = val_prefix##_##id; \ + break + +#define CASE_SET_NVU32(id) \ +case token_##id:\ + bct_ptr->id = *((uint32_t *)data); \ + break + +#define CASE_GET_DATA(id, size) \ +case token_##id:\ + if (*length < size) return -ENODATA;\ + memcpy(data, &(bct_ptr->id), size); \ + *length = size;\ + break + +#define CASE_SET_DATA(id, size) \ +case token_##id:\ + if (length < size) return -ENODATA;\ + memcpy(&(bct_ptr->id), data, size); \ + break + +#define DEFAULT() \ +default : \ + printf("Unexpected token %d at line %d\n", \ + token, __LINE__); \ + return 1 + +parse_token t30_root_token_list[] = { + token_boot_data_version, + token_block_size, + token_page_size, + token_partition_size, + token_odm_data, + token_bootloader_used, + token_bootloaders_max, + token_bct_size, + token_hash_size, + token_crypto_offset, + token_crypto_length, + token_max_bct_search_blks +}; + +int +t30_set_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1); + + switch (token) { + CASE_SET_DEV_PARAM(nand, clock_divider); + CASE_SET_DEV_PARAM(nand, block_size_log2); + CASE_SET_DEV_PARAM(nand, page_size_log2); + CASE_SET_DEV_PARAM(nand, async_timing0); + CASE_SET_DEV_PARAM(nand, async_timing1); + CASE_SET_DEV_PARAM(nand, async_timing2); + CASE_SET_DEV_PARAM(nand, async_timing3); + CASE_SET_DEV_PARAM(nand, sddr_timing0); + CASE_SET_DEV_PARAM(nand, sddr_timing1); + CASE_SET_DEV_PARAM(nand, tddr_timing0); + CASE_SET_DEV_PARAM(nand, tddr_timing1); + CASE_SET_DEV_PARAM(nand, fbio_dqsib_dly_byte); + CASE_SET_DEV_PARAM(nand, fbio_quse_dly_byte); + CASE_SET_DEV_PARAM(nand, fbio_cfg_quse_late); + CASE_SET_DEV_PARAM(nand, disable_sync_ddr); + + CASE_SET_DEV_PARAM(sdmmc, clock_divider); + CASE_SET_DEV_PARAM(sdmmc, data_width); + CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_SET_DEV_PARAM(sdmmc, sd_controller); + + CASE_SET_DEV_PARAM(spiflash, clock_source); + CASE_SET_DEV_PARAM(spiflash, clock_divider); + CASE_SET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + bct->dev_type[index] = value; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_get_dev_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + + switch (token) { + CASE_GET_DEV_PARAM(nand, clock_divider); + CASE_GET_DEV_PARAM(nand, block_size_log2); + CASE_GET_DEV_PARAM(nand, page_size_log2); + CASE_GET_DEV_PARAM(nand, async_timing0); + CASE_GET_DEV_PARAM(nand, async_timing1); + CASE_GET_DEV_PARAM(nand, async_timing2); + CASE_GET_DEV_PARAM(nand, async_timing3); + CASE_GET_DEV_PARAM(nand, sddr_timing0); + CASE_GET_DEV_PARAM(nand, sddr_timing1); + CASE_GET_DEV_PARAM(nand, tddr_timing0); + CASE_GET_DEV_PARAM(nand, tddr_timing1); + CASE_GET_DEV_PARAM(nand, fbio_dqsib_dly_byte); + CASE_GET_DEV_PARAM(nand, fbio_quse_dly_byte); + CASE_GET_DEV_PARAM(nand, fbio_cfg_quse_late); + CASE_GET_DEV_PARAM(nand, disable_sync_ddr); + + CASE_GET_DEV_PARAM(sdmmc, clock_divider); + CASE_GET_DEV_PARAM(sdmmc, data_width); + CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); + CASE_GET_DEV_PARAM(sdmmc, sd_controller); + + CASE_GET_DEV_PARAM(spiflash, clock_source); + CASE_GET_DEV_PARAM(spiflash, clock_divider); + CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); + + case token_dev_type: + *value = bct->dev_type[index]; + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_get_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t *value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + + switch (token) { + CASE_GET_SDRAM_PARAM(memory_type); + CASE_GET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); + CASE_GET_SDRAM_PARAM(pllm_input_divider); + CASE_GET_SDRAM_PARAM(pllm_feedback_divider); + CASE_GET_SDRAM_PARAM(pllm_post_divider); + CASE_GET_SDRAM_PARAM(pllm_stable_time); + CASE_GET_SDRAM_PARAM(emc_clock_divider); + CASE_GET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_GET_SDRAM_PARAM(emc_auto_cal_config); + CASE_GET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_GET_SDRAM_PARAM(emc_pin_program_wait); + CASE_GET_SDRAM_PARAM(emc_rc); + CASE_GET_SDRAM_PARAM(emc_rfc); + CASE_GET_SDRAM_PARAM(emc_ras); + CASE_GET_SDRAM_PARAM(emc_rp); + CASE_GET_SDRAM_PARAM(emc_r2w); + CASE_GET_SDRAM_PARAM(emc_w2r); + CASE_GET_SDRAM_PARAM(emc_r2p); + CASE_GET_SDRAM_PARAM(emc_w2p); + CASE_GET_SDRAM_PARAM(emc_rd_rcd); + CASE_GET_SDRAM_PARAM(emc_wr_rcd); + CASE_GET_SDRAM_PARAM(emc_rrd); + CASE_GET_SDRAM_PARAM(emc_rext); + CASE_GET_SDRAM_PARAM(emc_wdv); + CASE_GET_SDRAM_PARAM(emc_quse); + CASE_GET_SDRAM_PARAM(emc_qrst); + CASE_GET_SDRAM_PARAM(emc_qsafe); + CASE_GET_SDRAM_PARAM(emc_rdv); + CASE_GET_SDRAM_PARAM(emc_refresh); + CASE_GET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_GET_SDRAM_PARAM(emc_pdex2wr); + CASE_GET_SDRAM_PARAM(emc_pdex2rd); + CASE_GET_SDRAM_PARAM(emc_pchg2pden); + CASE_GET_SDRAM_PARAM(emc_act2pden); + CASE_GET_SDRAM_PARAM(emc_ar2pden); + CASE_GET_SDRAM_PARAM(emc_rw2pden); + CASE_GET_SDRAM_PARAM(emc_txsr); + CASE_GET_SDRAM_PARAM(emc_tcke); + CASE_GET_SDRAM_PARAM(emc_tfaw); + CASE_GET_SDRAM_PARAM(emc_trpab); + CASE_GET_SDRAM_PARAM(emc_tclkstable); + CASE_GET_SDRAM_PARAM(emc_tclkstop); + CASE_GET_SDRAM_PARAM(emc_trefbw); + CASE_GET_SDRAM_PARAM(emc_quse_extra); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_GET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_GET_SDRAM_PARAM(emc_fbio_spare); + CASE_GET_SDRAM_PARAM(emc_mrs); + CASE_GET_SDRAM_PARAM(emc_emrs); + CASE_GET_SDRAM_PARAM(emc_mrw1); + CASE_GET_SDRAM_PARAM(emc_mrw2); + CASE_GET_SDRAM_PARAM(emc_mrw3); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_GET_SDRAM_PARAM(emc_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg); + CASE_GET_SDRAM_PARAM(emc_cfg2); + CASE_GET_SDRAM_PARAM(emc_dbg); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_GET_SDRAM_PARAM(warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_GET_SDRAM_PARAM(emc_odt_write); + CASE_GET_SDRAM_PARAM(emc_odt_read); + CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_GET_SDRAM_PARAM(emc_emrs_emr2); + CASE_GET_SDRAM_PARAM(emc_emrs_emr3); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_GET_SDRAM_PARAM(emc_ddr2_wait); + CASE_GET_SDRAM_PARAM(pmc_ddr_pwr); + + CASE_GET_SDRAM_PARAM(emc_clock_source); + CASE_GET_SDRAM_PARAM(emc_clock_use_pll_mud); + CASE_GET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_GET_SDRAM_PARAM(emc_timing_control_wait); + CASE_GET_SDRAM_PARAM(emc_wext); + CASE_GET_SDRAM_PARAM(emc_ctt); + CASE_GET_SDRAM_PARAM(emc_ctt_duration); + CASE_GET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_GET_SDRAM_PARAM(emc_txsr_dll); + CASE_GET_SDRAM_PARAM(emc_cfg_rsv); + CASE_GET_SDRAM_PARAM(emc_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw1); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw2); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw3); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_GET_SDRAM_PARAM(emc_cmd_q); + CASE_GET_SDRAM_PARAM(emc_mc2emc_q); + CASE_GET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_GET_SDRAM_PARAM(emc_dev_select); + CASE_GET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_GET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_GET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_GET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_GET_SDRAM_PARAM(emc_zcal_interval); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_GET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_GET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_GET_SDRAM_PARAM(emc_zcal_cold_boot_enable); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_boot_enable); + CASE_GET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_GET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_GET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_GET_SDRAM_PARAM(emc_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrs); + CASE_GET_SDRAM_PARAM(emc_warm_boot_emrs); + CASE_GET_SDRAM_PARAM(emc_warm_boot_emr2); + CASE_GET_SDRAM_PARAM(emc_warm_boot_emr3); + CASE_GET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_GET_SDRAM_PARAM(emc_clken_override); + CASE_GET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_GET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_GET_SDRAM_PARAM(pmc_vddp_sel); + CASE_GET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_GET_SDRAM_PARAM(pmc_io_dpd_req); + CASE_GET_SDRAM_PARAM(pmc_eno_vtt_gen); + CASE_GET_SDRAM_PARAM(pmc_no_io_power); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_GET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_GET_SDRAM_PARAM(emc_xm2quse_pad_ctrl); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_GET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_GET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_GET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_GET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_GET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_GET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_GET_SDRAM_PARAM(mc_emem_arb_override); + CASE_GET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_GET_SDRAM_PARAM(mc_clken_override); + + DEFAULT(); + } + return 0; +} + +int +t30_set_sdram_param(build_image_context *context, + uint32_t index, + parse_token token, + uint32_t value) +{ + nvboot_sdram_params *params; + nvboot_config_table *bct = NULL; + + bct = (nvboot_config_table *)(context->bct); + assert(context != NULL); + assert(bct != NULL); + params = &(bct->sdram_params[index]); + /* Update the number of SDRAM parameter sets. */ + bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1); + + switch (token) { + CASE_SET_SDRAM_PARAM(memory_type); + CASE_SET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl); + CASE_SET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl); + CASE_SET_SDRAM_PARAM(pllm_input_divider); + CASE_SET_SDRAM_PARAM(pllm_feedback_divider); + CASE_SET_SDRAM_PARAM(pllm_post_divider); + CASE_SET_SDRAM_PARAM(pllm_stable_time); + CASE_SET_SDRAM_PARAM(emc_clock_divider); + CASE_SET_SDRAM_PARAM(emc_auto_cal_interval); + CASE_SET_SDRAM_PARAM(emc_auto_cal_config); + CASE_SET_SDRAM_PARAM(emc_auto_cal_wait); + CASE_SET_SDRAM_PARAM(emc_pin_program_wait); + CASE_SET_SDRAM_PARAM(emc_rc); + CASE_SET_SDRAM_PARAM(emc_rfc); + CASE_SET_SDRAM_PARAM(emc_ras); + CASE_SET_SDRAM_PARAM(emc_rp); + CASE_SET_SDRAM_PARAM(emc_r2w); + CASE_SET_SDRAM_PARAM(emc_w2r); + CASE_SET_SDRAM_PARAM(emc_r2p); + CASE_SET_SDRAM_PARAM(emc_w2p); + CASE_SET_SDRAM_PARAM(emc_rd_rcd); + CASE_SET_SDRAM_PARAM(emc_wr_rcd); + CASE_SET_SDRAM_PARAM(emc_rrd); + CASE_SET_SDRAM_PARAM(emc_rext); + CASE_SET_SDRAM_PARAM(emc_wdv); + CASE_SET_SDRAM_PARAM(emc_quse); + CASE_SET_SDRAM_PARAM(emc_qrst); + CASE_SET_SDRAM_PARAM(emc_qsafe); + CASE_SET_SDRAM_PARAM(emc_rdv); + CASE_SET_SDRAM_PARAM(emc_refresh); + CASE_SET_SDRAM_PARAM(emc_burst_refresh_num); + CASE_SET_SDRAM_PARAM(emc_pdex2wr); + CASE_SET_SDRAM_PARAM(emc_pdex2rd); + CASE_SET_SDRAM_PARAM(emc_pchg2pden); + CASE_SET_SDRAM_PARAM(emc_act2pden); + CASE_SET_SDRAM_PARAM(emc_ar2pden); + CASE_SET_SDRAM_PARAM(emc_rw2pden); + CASE_SET_SDRAM_PARAM(emc_txsr); + CASE_SET_SDRAM_PARAM(emc_tcke); + CASE_SET_SDRAM_PARAM(emc_tfaw); + CASE_SET_SDRAM_PARAM(emc_trpab); + CASE_SET_SDRAM_PARAM(emc_tclkstable); + CASE_SET_SDRAM_PARAM(emc_tclkstop); + CASE_SET_SDRAM_PARAM(emc_trefbw); + CASE_SET_SDRAM_PARAM(emc_quse_extra); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg5); + CASE_SET_SDRAM_PARAM(emc_fbio_cfg6); + CASE_SET_SDRAM_PARAM(emc_fbio_spare); + CASE_SET_SDRAM_PARAM(emc_mrs); + CASE_SET_SDRAM_PARAM(emc_emrs); + CASE_SET_SDRAM_PARAM(emc_mrw1); + CASE_SET_SDRAM_PARAM(emc_mrw2); + CASE_SET_SDRAM_PARAM(emc_mrw3); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_command); + CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait); + CASE_SET_SDRAM_PARAM(emc_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg); + CASE_SET_SDRAM_PARAM(emc_cfg2); + CASE_SET_SDRAM_PARAM(emc_dbg); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period); + CASE_SET_SDRAM_PARAM(warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl); + CASE_SET_SDRAM_PARAM(emc_odt_write); + CASE_SET_SDRAM_PARAM(emc_odt_read); + CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll); + CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait); + CASE_SET_SDRAM_PARAM(emc_emrs_emr2); + CASE_SET_SDRAM_PARAM(emc_emrs_emr3); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset); + CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib); + CASE_SET_SDRAM_PARAM(emc_ddr2_wait); + CASE_SET_SDRAM_PARAM(pmc_ddr_pwr); + + CASE_SET_SDRAM_PARAM(emc_clock_source); + CASE_SET_SDRAM_PARAM(emc_clock_use_pll_mud); + CASE_SET_SDRAM_PARAM(emc_pin_extra_wait); + CASE_SET_SDRAM_PARAM(emc_timing_control_wait); + CASE_SET_SDRAM_PARAM(emc_wext); + CASE_SET_SDRAM_PARAM(emc_ctt); + CASE_SET_SDRAM_PARAM(emc_ctt_duration); + CASE_SET_SDRAM_PARAM(emc_prerefresh_req_cnt); + CASE_SET_SDRAM_PARAM(emc_txsr_dll); + CASE_SET_SDRAM_PARAM(emc_cfg_rsv); + CASE_SET_SDRAM_PARAM(emc_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw1); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw2); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw3); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_extramode_reg_write_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt); + CASE_SET_SDRAM_PARAM(emc_cmd_q); + CASE_SET_SDRAM_PARAM(emc_mc2emc_q); + CASE_SET_SDRAM_PARAM(emc_dyn_self_ref_control); + CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done); + CASE_SET_SDRAM_PARAM(emc_dev_select); + CASE_SET_SDRAM_PARAM(emc_sel_dpd_ctrl); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse3); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse4); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse5); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse6); + CASE_SET_SDRAM_PARAM(emc_dll_xform_quse7); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs0); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs1); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs2); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs3); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs4); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs5); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs6); + CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs7); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq0); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq1); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq2); + CASE_SET_SDRAM_PARAM(emc_dll_xform_dq3); + CASE_SET_SDRAM_PARAM(emc_zcal_interval); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev0); + CASE_SET_SDRAM_PARAM(emc_zcal_init_dev1); + CASE_SET_SDRAM_PARAM(emc_zcal_init_wait); + CASE_SET_SDRAM_PARAM(emc_zcal_cold_boot_enable); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_enable); + CASE_SET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot); + CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_wait); + CASE_SET_SDRAM_PARAM(emc_mrs_warm_boot_enable); + CASE_SET_SDRAM_PARAM(emc_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs); + CASE_SET_SDRAM_PARAM(emc_warm_boot_emrs); + CASE_SET_SDRAM_PARAM(emc_warm_boot_emr2); + CASE_SET_SDRAM_PARAM(emc_warm_boot_emr3); + CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs_extra); + CASE_SET_SDRAM_PARAM(emc_clken_override); + CASE_SET_SDRAM_PARAM(emc_extra_refresh_num); + CASE_SET_SDRAM_PARAM(emc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(mc_clken_override_allwarm_boot); + CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot); + CASE_SET_SDRAM_PARAM(pmc_vddp_sel); + CASE_SET_SDRAM_PARAM(pmc_ddr_cfg); + CASE_SET_SDRAM_PARAM(pmc_io_dpd_req); + CASE_SET_SDRAM_PARAM(pmc_eno_vtt_gen); + CASE_SET_SDRAM_PARAM(pmc_no_io_power); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2comp_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl); + CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2); + CASE_SET_SDRAM_PARAM(emc_xm2quse_pad_ctrl); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev0); + CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_cfg); + CASE_SET_SDRAM_PARAM(mc_emem_arb_outstanding_req); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rcd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rp); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rc); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_ras); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_faw); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rrd); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2w); + CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2r); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_turns); + CASE_SET_SDRAM_PARAM(mc_emem_arb_da_covers); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc0); + CASE_SET_SDRAM_PARAM(mc_emem_arb_misc1); + CASE_SET_SDRAM_PARAM(mc_emem_arb_ring1_throttle); + CASE_SET_SDRAM_PARAM(mc_emem_arb_override); + CASE_SET_SDRAM_PARAM(mc_emem_arb_rsv); + CASE_SET_SDRAM_PARAM(mc_clken_override); + + DEFAULT(); + } + return 0; +} + +int +t30_getbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_GET_BL_PARAM(version); + CASE_GET_BL_PARAM(start_blk); + CASE_GET_BL_PARAM(start_page); + CASE_GET_BL_PARAM(length); + CASE_GET_BL_PARAM(load_addr); + CASE_GET_BL_PARAM(entry_point); + CASE_GET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(data, + &(bct_ptr->bootloader[set].crypto_hash), + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_setbl_param(uint32_t set, + parse_token id, + uint32_t *data, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (set >= NVBOOT_MAX_BOOTLOADERS) + return -ENODATA; + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + CASE_SET_BL_PARAM(version); + CASE_SET_BL_PARAM(start_blk); + CASE_SET_BL_PARAM(start_page); + CASE_SET_BL_PARAM(length); + CASE_SET_BL_PARAM(load_addr); + CASE_SET_BL_PARAM(entry_point); + CASE_SET_BL_PARAM(attribute); + + case token_bl_crypto_hash: + memcpy(&(bct_ptr->bootloader[set].crypto_hash), + data, + sizeof(nvboot_hash)); + break; + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_bct_get_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + nvboot_config_table samplebct; /* Used for computing offsets. */ + + /* + * Note: Not all queries require use of the BCT, so testing for a + * valid BCT is distributed within the code. + */ + if (data == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_GET_NVU32(boot_data_version); + CASE_GET_NVU32(block_size_log2); + CASE_GET_NVU32(page_size_log2); + CASE_GET_NVU32(partition_size); + CASE_GET_NVU32(num_param_sets); + CASE_GET_NVU32(num_sdram_sets); + CASE_GET_NVU32(bootloader_used); + CASE_GET_NVU32(odm_data); + + case token_block_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->block_size_log2; + break; + + case token_page_size: + if (bct == NULL) + return -ENODATA; + *((uint32_t *)data) = 1 << bct_ptr->page_size_log2; + break; + + /* + * Constants. + */ + + CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS); + CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); + + case token_reserved_offset: + *((uint32_t *)data) = (uint8_t *)&(samplebct.reserved) + - (uint8_t *)&samplebct; + break; + + case token_bct_size: + *((uint32_t *)data) = sizeof(nvboot_config_table); + break; + + CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); + + case token_crypto_offset: + /* Offset to region in BCT to encrypt & sign */ + *((uint32_t *)data) = (uint8_t *)&(samplebct.random_aes_blk) + - (uint8_t *)&samplebct; + break; + + case token_crypto_length: + /* size of region in BCT to encrypt & sign */ + *((uint32_t *)data) = sizeof(nvboot_config_table) - sizeof(nvboot_hash); + break; + + CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); + + CASE_GET_CONST_PREFIX(dev_type_nand, nvboot); + CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot); + CASE_GET_CONST_PREFIX(dev_type_spi, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot); + CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllc_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot); + CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot); + + CASE_GET_CONST_PREFIX(memory_type_none, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot); + CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot); + CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot); + + default: + return -ENODATA; + } + return 0; +} + +int +t30_bct_set_value(parse_token id, void *data, uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (bct == NULL) + return -ENODATA; + + switch (id) { + /* + * Simple BCT fields + */ + CASE_SET_NVU32(boot_data_version); + CASE_SET_NVU32(block_size_log2); + CASE_SET_NVU32(page_size_log2); + CASE_SET_NVU32(partition_size); + CASE_SET_NVU32(num_param_sets); + CASE_SET_NVU32(num_sdram_sets); + CASE_SET_NVU32(bootloader_used); + CASE_SET_NVU32(odm_data); + + default: + return -ENODATA; + } + + return 0; +} + +int +t30_bct_set_data(parse_token id, + uint8_t *data, + uint32_t length, + uint8_t *bct) +{ + nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; + + if (data == NULL || bct == NULL) + return -ENODATA; + + switch (id) { + + CASE_SET_DATA(crypto_hash, sizeof(nvboot_hash)); + + default: + return -ENODATA; + } + + return 0; +} + +int t30_get_bct_size() +{ + return sizeof(nvboot_config_table); +} + +int t30_bct_token_supported(parse_token token) +{ + int index; + + for (index = 0; index < ARRAY_SIZE(t30_root_token_list); index++) + if (t30_root_token_list[index] == token) + return 1; + + return 0; +} + +void t30_init_bad_block_table(build_image_context *context) +{ + uint32_t bytes_per_entry; + nvboot_badblock_table *table; + nvboot_config_table *bct; + + bct = (nvboot_config_table *)(context->bct); + + assert(context != NULL); + assert(bct != NULL); + + table = &bct->badblock_table; + + bytes_per_entry = ICEIL(context->partition_size, + NVBOOT_BAD_BLOCK_TABLE_SIZE); + table->block_size_log2 = context->block_size_log2; + table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry), + table->block_size_log2); + table->entries_used = iceil_log2(context->partition_size, + table->virtual_blk_size_log2); +} + +cbootimage_soc_config tegra30_config = { + .init_bad_block_table = t30_init_bad_block_table, + .set_dev_param = t30_set_dev_param, + .get_dev_param = t30_get_dev_param, + .set_sdram_param = t30_set_sdram_param, + .get_sdram_param = t30_get_sdram_param, + .setbl_param = t30_setbl_param, + .getbl_param = t30_getbl_param, + .set_value = t30_bct_set_value, + .get_value = t30_bct_get_value, + .set_data = t30_bct_set_data, + .get_bct_size = t30_get_bct_size, + .token_supported = t30_bct_token_supported, + + .devtype_table = s_devtype_table_t30, + .sdmmc_data_width_table = s_sdmmc_data_width_table_t30, + .spi_clock_source_table = s_spi_clock_source_table_t30, + .nvboot_memory_type_table = s_nvboot_memory_type_table_t30, + .sdram_field_table = s_sdram_field_table_t30, + .nand_table = s_nand_table_t30, + .sdmmc_table = s_sdmmc_table_t30, + .spiflash_table = s_spiflash_table_t30, + .device_type_table = s_device_type_table_t30, +}; + +void t30_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + context->boot_data_version = BOOTDATA_VERSION_T30; + *soc_config = &tegra30_config; +} + +int if_bct_is_t30_get_soc_config(build_image_context *context, + cbootimage_soc_config **soc_config) +{ + nvboot_config_table * bct = (nvboot_config_table *) context->bct; + + if (bct->boot_data_version == BOOTDATA_VERSION_T30) + { + t30_get_soc_config(context, soc_config); + return 1; + } + return 0; +} diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t30/nvboot_bct_t30.h b/firmware/coreboot/util/nvidia/cbootimage/src/t30/nvboot_bct_t30.h new file mode 100644 index 0000000000..84c6d3bcab --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t30/nvboot_bct_t30.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#ifndef INCLUDED_NVBOOT_BCT_T30_H +#define INCLUDED_NVBOOT_BCT_T30_H + +#include +#include "nvboot_sdram_param_t30.h" + +/** + * Defines the number of 32-bit words in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_WORDS 504 + +/** + * Defines the number of bytes in the customer_data area of the BCT. + */ +#define NVBOOT_BCT_CUSTOMER_DATA_SIZE \ + (NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4) + +/** + * Defines the number of bytes in the reserved area of the BCT. + */ +#define NVBOOT_BCT_RESERVED_SIZE 3 + +/** + * Defines the maximum number of bootloader descriptions in the BCT. + */ +#define NVBOOT_MAX_BOOTLOADERS 4 + +/** + * Defines the maximum number of device parameter sets in the BCT. + * The value must be equal to (1 << # of device straps) + */ +#define NVBOOT_BCT_MAX_PARAM_SETS 4 + +/** + * Defines the maximum number of SDRAM parameter sets in the BCT. + * The value must be equal to (1 << # of SDRAM straps) + */ +#define NVBOOT_BCT_MAX_SDRAM_SETS 4 + +/** + * Defines the number of entries (bits) in the bad block table. + * The consequences of changing its value are as follows. Using P as the + * # of physical blocks in the boot loader and B as the value of this + * constant: + * B > P: There will be unused storage in the bad block table. + * B < P: The virtual block size will be greater than the physical block + * size, so the granularity of the bad block table will be less than + * one bit per physical block. + * + * 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one + * bit per block (1 virtual block = 1 physical block). This occupies 512 bytes + * of storage. + */ +#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096 + +/** + * Defines the maximum number of blocks to search for BCTs. + * + * This value covers the initial block and a set of journal blocks. + * + * Ideally, this number will span several erase units for reliable updates + * and tolerance for blocks to become bad with use. Safe updates require + * a minimum of 2 erase units in which BCTs can appear. + * + * To ensure that the BCT search spans a sufficient range of configurations, + * the search block count has been set to 64. This allows for redundancy with + * a wide range of parts and provides room for greater problems in this + * region of the device. + */ +#define NVBOOT_MAX_BCT_SEARCH_BLOCKS 64 + +/* + * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) + */ +enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; + +/** + * Defines the storage for a hash value (128 bits). + */ +typedef struct nvboot_hash_rec { + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; +} nvboot_hash; + +/** + * Defines the params that can be configured for NAND devices. + */ +typedef struct nvboot_nand_params_rec { + /** + * Specifies the clock divider for the PLL_P 432MHz source. + * If it is set to 18, then clock source to Nand controller is + * 432 / 18 = 24MHz. + */ + uint8_t clock_divider; + + /** + * Specifies the value to be programmed to Nand Async Timing + * Register 0 + */ + uint32_t async_timing0; + /** + * Specifies the value to be programmed to Nand Async Timing + * Register 1 + */ + uint32_t async_timing1; + /** + * Specifies the value to be programmed to Nand Async Timing + * Register 2 + */ + uint32_t async_timing2; + /** + * Specifies the value to be programmed to Nand Async Timing + * Register 3 + */ + uint32_t async_timing3; + /** + * Specifies the value to be programmed to Nand Sync DDR Timing + * Register 0 + */ + uint32_t sddr_timing0; + /** + * Specifies the value to be programmed to Nand Sync DDR Timing + * Register 1 + */ + uint32_t sddr_timing1; + /** + * Specifies the value to be programmed to Nand Toggle DDR Timing + * Register 0 + */ + uint32_t tddr_timing0; + /** + * Specifies the value to be programmed to Nand Toggle DDR Timing + * Register 1 + */ + uint32_t tddr_timing1; + /* Specifies the value to be programmed to FBIO_DQSIB_DELAY register */ + uint8_t fbio_dqsib_dly_byte; + /* Specifies the value to be programmed to FBIO_DQUSE_DELAY register */ + uint8_t fbio_quse_dly_byte; + /* Specifies the CFG_QUSE_LATE value to be programmed to FBIO + * configuration register */ + uint8_t fbio_cfg_quse_late; + /* Specifies whether to enable sync DDR more or not */ + uint8_t disable_sync_ddr; + + /* Specifies the block size in log2 bytes */ + uint8_t block_size_log2; + + /* Specifies the page size in log2 bytes */ + uint8_t page_size_log2; +} nvboot_nand_params; + +/* Defines various data widths supported. */ +typedef enum { + /** + * Specifies a 1 bit interface to eMMC. + * Note that 1-bit data width is only for the driver's internal use. + * Fuses doesn't provide option to select 1-bit data width. + * The driver selects 1-bit internally based on need. + * It is used for reading Extended CSD and when the power class + * requirements of a card for 4-bit or 8-bit transfers are not + * supported by the target board. + */ + nvboot_sdmmc_data_width_1bit = 0, + + /* Specifies a 4 bit interface to eMMC. */ + nvboot_sdmmc_data_width_4bit = 1, + + /* Specifies a 8 bit interface to eMMC. */ + nvboot_sdmmc_data_width_8bit = 2, + /* Specifies a 4 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_4bit = 5, + /* Specifies a 8 bit Ddr interface to eMMC. */ + nvboot_sdmmc_data_width_ddr_8bit = 6, + + nvboot_sdmmc_data_width_num, + nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF +} nvboot_sdmmc_data_width; + +/* Defines various sd controllers supported. */ +typedef enum { + /* Specifies Sdmmc 4 controller interface */ + nvboot_sdmmc_cntrl_4 = 0, + /* Specifies Sdmmc 3 controller interface */ + nvboot_sdmmc_cntrl_3 = 1, + nvboot_sdmmc_cntrl_num, + nvboot_sdmmc_cntrl_force32 = 0x7FFFFFFF +} nvboot_sdmmc_cntrl; + +/* Defines the parameters that can be changed after BCT is read. */ +typedef struct nvboot_sdmmc_params_rec { + /** + * Specifies the clock divider for the SDMMC controller's clock source, + * which is PLLP running at 432MHz. If it is set to 18, then the SDMMC + * controller runs at 432/18 = 24MHz. + */ + uint8_t clock_divider; + + /* Specifies the data bus width. Supported data widths are 4/8 bits. */ + nvboot_sdmmc_data_width data_width; + + /** + * Max Power class supported by the target board. + * The driver determines the best data width and clock frequency + * supported within the power class range (0 to Max) if the selected + * data width cannot be used at the chosen clock frequency. + */ + uint8_t max_power_class_supported; + + /* Specifies the SD controller to be selected */ + nvboot_sdmmc_cntrl sd_controller; +} nvboot_sdmmc_params; + +typedef enum { + /* Specifies SPI clock source to be PLLP. */ + nvboot_spi_clock_source_pllp_out0 = 0, + + /* Specifies SPI clock source to be PLLC. */ + nvboot_spi_clock_source_pllc_out0, + + /* Specifies SPI clock source to be PLLM. */ + nvboot_spi_clock_source_pllm_out0, + + /* Specifies SPI clock source to be ClockM. */ + nvboot_spi_clock_source_clockm, + + nvboot_spi_clock_source_num, + nvboot_spi_clock_source_force32 = 0x7FFFFFF +} nvboot_spi_clock_source; + + +/** + * Defines the parameters SPI FLASH devices. + */ +typedef struct nvboot_spiflash_params_rec { + /** + * Specifies the clock source to use. + */ + nvboot_spi_clock_source clock_source; + + /** + * Specifes the clock divider to use. + * The value is a 7-bit value based on an input clock of 432Mhz. + * Divider = (432+ DesiredFrequency-1)/DesiredFrequency; + * Typical values: + * NORMAL_READ at 20MHz: 22 + * FAST_READ at 33MHz: 14 + * FAST_READ at 40MHz: 11 + * FAST_READ at 50MHz: 9 + */ + uint8_t clock_divider; + + /** + * Specifies the type of command for read operations. + * NV_FALSE specifies a NORMAL_READ Command + * NV_TRUE specifies a FAST_READ Command + */ + uint8_t read_command_type_fast; +} nvboot_spiflash_params; + +/** +* Defines the union of the parameters required by each device. +*/ +typedef union { + uint8_t size[64]; + /* Specifies optimized parameters for NAND */ + nvboot_nand_params nand_params; + /* Specifies optimized parameters for eMMC and eSD */ + nvboot_sdmmc_params sdmmc_params; + /* Specifies optimized parameters for SPI NOR */ + nvboot_spiflash_params spiflash_params; +} nvboot_dev_params; + +/** + * Identifies the types of devices from which the system booted. + * Used to identify primary and secondary boot devices. + * @note These no longer match the fuse API device values (for + * backward compatibility with AP15). + */ +typedef enum { + /* Specifies a default (unset) value. */ + nvboot_dev_type_none = 0, + + /* Specifies NAND. */ + nvboot_dev_type_nand, + + /* Specifies SPI NOR. */ + nvboot_dev_type_spi = 3, + + /* Specifies SDMMC (either eMMC or eSD). */ + nvboot_dev_type_sdmmc, + + nvboot_dev_type_max, + + /* Ignore -- Forces compilers to make 32-bit enums. */ + nvboot_dev_type_force32 = 0x7FFFFFFF +} nvboot_dev_type; + +/** + * Stores information needed to locate and verify a boot loader. + * + * There is one \c nv_bootloader_info structure for each copy of a BL stored on + * the device. + */ +typedef struct nv_bootloader_info_rec { + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; + nvboot_hash crypto_hash; +} nv_bootloader_info; + +/** + * Defines the bad block table structure stored in the BCT. + */ +typedef struct nvboot_badblock_table_rec { + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; +} nvboot_badblock_table; + +/** + * Contains the information needed to load BLs from the secondary boot device. + * + * - Supplying NumParamSets = 0 indicates not to load any of them. + * - Supplying NumDramSets = 0 indicates not to load any of them. + * - The \c random_aes_blk member exists to increase the difficulty of + * key attacks based on knowledge of this structure. + */ +typedef struct nvboot_config_table_rec { + nvboot_hash crypto_hash; + nvboot_hash random_aes_blk; + uint32_t boot_data_version; + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; + nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; + nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; + uint32_t num_sdram_sets; + nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; + nvboot_badblock_table badblock_table; + uint32_t bootloader_used; + nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + /* + * ODMDATA is stored in the BCT in IRAM by the BootROM. + * Read the data @ bct_start + (bct_size - 12). This works + * on T20 and T30 BCTs, which are locked down. If this changes + * in new chips, we can revisit this algorithm. + */ + uint32_t odm_data; + uint32_t reserved1; + uint8_t enable_fail_back; + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; +} nvboot_config_table; +#endif /* #ifndef INCLUDED_NVBOOT_BCT_T30_H */ diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t30/nvboot_sdram_param_t30.h b/firmware/coreboot/util/nvidia/cbootimage/src/t30/nvboot_sdram_param_t30.h new file mode 100644 index 0000000000..ab6d536161 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t30/nvboot_sdram_param_t30.h @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T30_H +#define INCLUDED_NVBOOT_SDRAM_PARAM_T30_H + +#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 + +typedef enum { + /* Specifies the memory type to be undefined */ + nvboot_memory_type_none = 0, + + /* Specifies the memory type to be DDR SDRAM */ + nvboot_memory_type_ddr, + + /* Specifies the memory type to be LPDDR SDRAM */ + nvboot_memory_type_lpddr, + + /* Specifies the memory type to be DDR2 SDRAM */ + nvboot_memory_type_ddr2, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + nvboot_memory_type_lpddr2, + + /* Specifies the memory type to be DDR3 SDRAM */ + nvboot_memory_type_ddr3, + + nvboot_memory_type_num, + nvboot_memory_type_force32 = 0x7FFFFFF +} nvboot_memory_type; + +/** + * Defines the SDRAM parameter structure + */ +typedef struct nvboot_sdram_params_rec { + /* sdram data structure generated by tool warmboot_code_gen */ + + /* Specifies the type of memory device */ + nvboot_memory_type memory_type; + + /* MC/EMC clock source configuration */ + + /* Specifies the CPCON value for PllM */ + uint32_t pllm_charge_pump_setup_ctrl; + /* Specifies the LPCON value for PllM */ + uint32_t pllm_loop_filter_setup_ctrl; + /* Specifies the M value for PllM */ + uint32_t pllm_input_divider; + /* Specifies the N value for PllM */ + uint32_t pllm_feedback_divider; + /* Specifies the P value for PllM */ + uint32_t pllm_post_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t pllm_stable_time; + + /* Specifies the divider for the EMC Clock Source */ + uint32_t emc_clock_divider; + /* Specifies the PLL source for the EMC Clock Source */ + uint32_t emc_clock_source; + /* + * Specifies the enable for using low jitter clock for + * the EMC Clock Source + */ + uint32_t emc_clock_use_pll_mud; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t emc_auto_cal_interval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t emc_auto_cal_config; + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t emc_auto_cal_wait; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t emc_adr_cfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t emc_pin_program_wait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t emc_pin_extra_wait; + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t emc_timing_control_wait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t emc_rc; + /* Specifies the value for EMC_RFC */ + uint32_t emc_rfc; + /* Specifies the value for EMC_RAS */ + uint32_t emc_ras; + /* Specifies the value for EMC_RP */ + uint32_t emc_rp; + /* Specifies the value for EMC_R2W */ + uint32_t emc_r2w; + /* Specifies the value for EMC_R2W */ + uint32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + uint32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + uint32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + uint32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + uint32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + uint32_t emc_rext; + /* Specifies the value for EMC_WEXT */ + uint32_t emc_wext; + /* Specifies the value for EMC_WDV */ + uint32_t emc_wdv; + /* Specifies the value for EMC_QUSE */ + uint32_t emc_quse; + /* Specifies the value for EMC_QRST */ + uint32_t emc_qrst; + /* Specifies the value for EMC_QSAFE */ + uint32_t emc_qsafe; + /* Specifies the value for EMC_RDV */ + uint32_t emc_rdv; + /* Specifies the value for EMC_CTT */ + uint32_t emc_ctt; + /* Specifies the value for EMC_CTT_DURATION */ + uint32_t emc_ctt_duration; + /* Specifies the value for EMC_REFRESH */ + uint32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t emc_prerefresh_req_cnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t emc_rw2pden; + /* Specifies the value for EMC_TXSR */ + uint32_t emc_txsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t emc_txsr_dll; + /* Specifies the value for EMC_TCKE */ + uint32_t emc_tcke; + /* Specifies the value for EMC_TFAW */ + uint32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + uint32_t emc_trefbw; + /* Specifies the value for EMC_QUSE_EXTRA */ + uint32_t emc_quse_extra; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + uint32_t emc_fbio_cfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t emc_fbio_spare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t emc_cfg_rsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t emc_mrs; + /* Specifies the value for EMC_EMRS */ + uint32_t emc_emrs; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t emc_mrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t emc_mrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t emc_mrw3; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t emc_mrw_extra; + /* Specifies the programming to LPDDR2 Mode Register 1 at warm boot */ + uint32_t emc_warm_boot_mrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at warm boot */ + uint32_t emc_warm_boot_mrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at warm boot */ + uint32_t emc_warm_boot_mrw3; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t emc_warm_boot_mrw_extra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t emc_warm_boot_extramode_reg_write_enable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t emc_extramode_reg_write_enable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t emc_mrw_reset_ninit_wait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t emc_mrs_wait_cnt; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t emc_cfg2; + /* Specifies the value for EMC_DBG */ + uint32_t emc_dbg; + /* Specifies the value for EMC_CMDQ */ + uint32_t emc_cmd_q; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t emc_mc2emc_q; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t emc_dyn_self_ref_control; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t ahb_arbitration_xbar_ctrl_meminit_done; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t emc_cfg_dig_dll; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t emc_cfg_dig_dll_period; + /* Specifies the vlaue of *DEV_SELECTN of various EMC registers */ + uint32_t emc_dev_select; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t emc_sel_dpd_ctrl; + + /* Pads trimmer delays */ + + /* Specifies the value for EMC_DLL_XFORM_DQS0 */ + uint32_t emc_dll_xform_dqs0; + /* Specifies the value for EMC_DLL_XFORM_DQS1 */ + uint32_t emc_dll_xform_dqs1; + /* Specifies the value for EMC_DLL_XFORM_DQS2 */ + uint32_t emc_dll_xform_dqs2; + /* Specifies the value for EMC_DLL_XFORM_DQS3 */ + uint32_t emc_dll_xform_dqs3; + /* Specifies the value for EMC_DLL_XFORM_DQS4 */ + uint32_t emc_dll_xform_dqs4; + /* Specifies the value for EMC_DLL_XFORM_DQS5 */ + uint32_t emc_dll_xform_dqs5; + /* Specifies the value for EMC_DLL_XFORM_DQS6 */ + uint32_t emc_dll_xform_dqs6; + /* Specifies the value for EMC_DLL_XFORM_DQS7 */ + uint32_t emc_dll_xform_dqs7; + /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ + uint32_t emc_dll_xform_quse0; + /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ + uint32_t emc_dll_xform_quse1; + /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ + uint32_t emc_dll_xform_quse2; + /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ + uint32_t emc_dll_xform_quse3; + /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ + uint32_t emc_dll_xform_quse4; + /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ + uint32_t emc_dll_xform_quse5; + /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ + uint32_t emc_dll_xform_quse6; + /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ + uint32_t emc_dll_xform_quse7; + /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ + uint32_t emc_dli_trim_tx_dqs0; + /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ + uint32_t emc_dli_trim_tx_dqs1; + /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ + uint32_t emc_dli_trim_tx_dqs2; + /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ + uint32_t emc_dli_trim_tx_dqs3; + /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ + uint32_t emc_dli_trim_tx_dqs4; + /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ + uint32_t emc_dli_trim_tx_dqs5; + /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ + uint32_t emc_dli_trim_tx_dqs6; + /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ + uint32_t emc_dli_trim_tx_dqs7; + /* Specifies the value for EMC_DLL_XFORM_DQ0 */ + uint32_t emc_dll_xform_dq0; + /* Specifies the value for EMC_DLL_XFORM_DQ1 */ + uint32_t emc_dll_xform_dq1; + /* Specifies the value for EMC_DLL_XFORM_DQ2 */ + uint32_t emc_dll_xform_dq2; + /* Specifies the value for EMC_DLL_XFORM_DQ3 */ + uint32_t emc_dll_xform_dq3; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t warm_boot_wait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + uint32_t emc_ctt_term_ctrl; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_write; + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_read; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t emc_zcal_interval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t emc_zcal_wait_cnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t emc_zcal_mrw_cmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t emc_mrs_reset_dll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t emc_zcal_init_dev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t emc_zcal_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t emc_zcal_init_wait; + /* Specifies the enable for ZQ calibration at cold boot */ + uint32_t emc_zcal_cold_boot_enable; + /* Specifies the enable for ZQ calibration at warm boot */ + uint32_t emc_zcal_warm_boot_enable; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + *on warmboot + */ + /* Is issued to both devices separately */ + uint32_t emc_mrw_lpddr2zcal_warm_boot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t emc_zqcal_ddr3_warm_boot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t emc_zcal_warm_boot_wait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t emc_mrs_warm_boot_enable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t emc_mrs_reset_dll_wait; + /* + * Specifies the first of two EMRS commands to initialize mode + * registers + */ + uint32_t emc_emrs_emr2; + /* + * Specifies the second of two EMRS commands to initialize mode + * registers + */ + uint32_t emc_emrs_emr3; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t emc_mrs_extra; + /* Specifies the programming to DDR3 Mode Register 0 at warm boot */ + uint32_t emc_warm_boot_mrs; + /* Specifies the programming to DDR3 Mode Register 1 at warm boot */ + uint32_t emc_warm_boot_emrs; + /* Specifies the programming to DDR3 Mode Register 2 at warm boot */ + uint32_t emc_warm_boot_emr2; + /* Specifies the programming to DDR3 Mode Register 3 at warm boot */ + uint32_t emc_warm_boot_emr3; + /* Specifies the extra MRS command at warm boot */ + uint32_t emc_warm_boot_mrs_extra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t emc_ddr2_wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t emc_clken_override; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t emc_extra_refresh_num; + /* Specifies the master override for all EMC clocks */ + uint32_t emc_clken_override_allwarm_boot; + /* Specifies the master override for all MC clocks */ + uint32_t mc_clken_override_allwarm_boot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t emc_cfg_dig_dll_period_warm_boot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t pmc_ddr_pwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t pmc_ddr_cfg; + /* Specifies the value for PMC_IO_DPD_REQ */ + uint32_t pmc_io_dpd_req; + /* Specifies the value for PMC_E_NO_VTTGEN */ + uint32_t pmc_eno_vtt_gen; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t pmc_no_io_power; + /* Specifies the value for EMC_XM2CMDPADCTRL */ + uint32_t emc_xm2cmd_pad_ctrl; + /* Specifies the value for EMC_XM2CMDPADCTRL2 */ + uint32_t emc_xm2cmd_pad_ctrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL */ + uint32_t emc_xm2dqs_pad_ctrl; + /* Specifies the value for EMC_XM2DQSPADCTRL2 */ + uint32_t emc_xm2dqs_pad_ctrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL3 */ + uint32_t emc_xm2dqs_pad_ctrl3; + /* Specifies the value for EMC_XM2DQPADCTRL */ + uint32_t emc_xm2dq_pad_ctrl; + /* Specifies the value for EMC_XM2DQPADCTRL2 */ + uint32_t emc_xm2dq_pad_ctrl2; + /* Specifies the value for EMC_XM2CLKPADCTRL */ + uint32_t emc_xm2clk_pad_ctrl; + /* Specifies the value for EMC_XM2COMPPADCTRL */ + uint32_t emc_xm2comp_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL */ + uint32_t emc_xm2vttgen_pad_ctrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ + uint32_t emc_xm2vttgen_pad_ctrl2; + /* Specifies the value for EMC_XM2QUSEPADCTRL */ + uint32_t emc_xm2quse_pad_ctrl; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t mc_emem_adr_cfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t mc_emem_adr_cfg_dev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t mc_emem_adr_cfg_dev1; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t mc_emem_cfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t mc_emem_arb_cfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t mc_emem_arb_outstanding_req; + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t mc_emem_arb_timing_rcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t mc_emem_arb_timing_rp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t mc_emem_arb_timing_rc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t mc_emem_arb_timing_ras; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t mc_emem_arb_timing_faw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t mc_emem_arb_timing_rrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t mc_emem_arb_timing_rap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t mc_emem_arb_timing_wap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t mc_emem_arb_timing_r2r; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t mc_emem_arb_timing_w2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t mc_emem_arb_timing_r2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t mc_emem_arb_timing_w2r; + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t mc_emem_arb_da_turns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t mc_emem_arb_da_covers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t mc_emem_arb_misc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t mc_emem_arb_misc1; + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t mc_emem_arb_ring1_throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t mc_emem_arb_override; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t mc_emem_arb_rsv; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t mc_clken_override; + + /* End of generated code by warmboot_code_gen */ +} nvboot_sdram_params; +#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T30_H */ + diff --git a/firmware/coreboot/util/nvidia/cbootimage/src/t30/parse_t30.c b/firmware/coreboot/util/nvidia/cbootimage/src/t30/parse_t30.c new file mode 100644 index 0000000000..4715f39f57 --- /dev/null +++ b/firmware/coreboot/util/nvidia/cbootimage/src/t30/parse_t30.c @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/* + * parse_t30.h - Definitions for the dev/sdram parameters + */ + +#include "../parse.h" +#include "nvboot_bct_t30.h" + +enum_item s_devtype_table_t30[] = { + { "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc }, + { "NvBootDevType_Spi", nvboot_dev_type_spi }, + { "NvBootDevType_Nand", nvboot_dev_type_nand }, + { "Sdmmc", nvboot_dev_type_sdmmc }, + { "Spi", nvboot_dev_type_spi }, + { "Nand", nvboot_dev_type_nand }, + + { NULL, 0 } +}; + +enum_item s_sdmmc_data_width_table_t30[] = { + { + "NvBootSdmmcDataWidth_4Bit", + nvboot_sdmmc_data_width_4bit + }, + { + "NvBootSdmmcDataWidth_8Bit", + nvboot_sdmmc_data_width_8bit + }, + { "4Bit", nvboot_sdmmc_data_width_4bit }, + { "8Bit", nvboot_sdmmc_data_width_8bit }, + { NULL, 0 } +}; + +enum_item s_spi_clock_source_table_t30[] = { + { + "NvBootSpiClockSource_PllPOut0", + nvboot_spi_clock_source_pllp_out0 + }, + { + "NvBootSpiClockSource_PllCOut0", + nvboot_spi_clock_source_pllc_out0 + }, + { + "NvBootSpiClockSource_PllMOut0", + nvboot_spi_clock_source_pllm_out0 + }, + { + "NvBootSpiClockSource_ClockM", + nvboot_spi_clock_source_clockm + }, + + { "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "ClockSource_PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "ClockSource_PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockSource_ClockM", nvboot_spi_clock_source_clockm }, + + + { "PllPOut0", nvboot_spi_clock_source_pllp_out0 }, + { "PllCOut0", nvboot_spi_clock_source_pllc_out0 }, + { "PllMOut0", nvboot_spi_clock_source_pllm_out0 }, + { "ClockM", nvboot_spi_clock_source_clockm }, + + { NULL, 0 } +}; + +enum_item s_nvboot_memory_type_table_t30[] = { + { "NvBootMemoryType_None", nvboot_memory_type_none }, + { "NvBootMemoryType_Ddr3", nvboot_memory_type_ddr3 }, + { "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 }, + { "NvBootMemoryType_Ddr", nvboot_memory_type_ddr }, + { "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 }, + { "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr }, + + { "None", nvboot_memory_type_none }, + { "Ddr3", nvboot_memory_type_ddr3 }, + { "Ddr2", nvboot_memory_type_ddr2 }, + { "Ddr", nvboot_memory_type_ddr }, + { "LpDdr2", nvboot_memory_type_lpddr2 }, + { "LpDdr", nvboot_memory_type_lpddr }, + + { NULL, 0 } +}; + +#define TOKEN(name) \ + token_##name, field_type_u32, NULL + +field_item s_sdram_field_table_t30[] = { + { "MemoryType", token_memory_type, + field_type_enum, s_nvboot_memory_type_table_t30 }, + + { "PllMChargePumpSetupControl", TOKEN(pllm_charge_pump_setup_ctrl) }, + { "PllMLoopFilterSetupControl", TOKEN(pllm_loop_filter_setup_ctrl) }, + { "PllMInputDivider", TOKEN(pllm_input_divider) }, + { "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) }, + { "PllMPostDivider", TOKEN(pllm_post_divider) }, + { "PllMStableTime", TOKEN(pllm_stable_time) }, + { "EmcClockDivider", TOKEN(emc_clock_divider) }, + { "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) }, + { "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) }, + { "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) }, + { "EmcPinProgramWait", TOKEN(emc_pin_program_wait) }, + { "EmcRc", TOKEN(emc_rc) }, + { "EmcRfc", TOKEN(emc_rfc) }, + { "EmcRas", TOKEN(emc_ras) }, + { "EmcRp", TOKEN(emc_rp) }, + { "EmcR2w", TOKEN(emc_r2w) }, + { "EmcW2r", TOKEN(emc_w2r) }, + { "EmcR2p", TOKEN(emc_r2p) }, + { "EmcW2p", TOKEN(emc_w2p) }, + { "EmcRrd", TOKEN(emc_rrd) }, + { "EmcRdRcd", TOKEN(emc_rd_rcd) }, + { "EmcWrRcd", TOKEN(emc_wr_rcd) }, + { "EmcRext", TOKEN(emc_rext) }, + { "EmcWdv", TOKEN(emc_wdv) }, + { "EmcQUseExtra", TOKEN(emc_quse_extra) }, + { "EmcQUse", TOKEN(emc_quse) }, + { "EmcQRst", TOKEN(emc_qrst) }, + { "EmcQSafe", TOKEN(emc_qsafe) }, + { "EmcRdv", TOKEN(emc_rdv) }, + { "EmcRefresh", TOKEN(emc_refresh) }, + { "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) }, + { "EmcPdEx2Wr", TOKEN(emc_pdex2wr) }, + { "EmcPdEx2Rd", TOKEN(emc_pdex2rd) }, + { "EmcPChg2Pden", TOKEN(emc_pchg2pden) }, + { "EmcAct2Pden", TOKEN(emc_act2pden) }, + { "EmcAr2Pden", TOKEN(emc_ar2pden) }, + { "EmcRw2Pden", TOKEN(emc_rw2pden) }, + { "EmcTxsr", TOKEN(emc_txsr) }, + { "EmcTcke", TOKEN(emc_tcke) }, + { "EmcTfaw", TOKEN(emc_tfaw) }, + { "EmcTrpab", TOKEN(emc_trpab) }, + { "EmcTClkStable", TOKEN(emc_tclkstable) }, + { "EmcTClkStop", TOKEN(emc_tclkstop) }, + { "EmcTRefBw", TOKEN(emc_trefbw) }, + { "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) }, + { "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) }, + { "EmcFbioSpare", TOKEN(emc_fbio_spare) }, + { "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) }, + { "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) }, + { "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) }, + { "EmcMrs", TOKEN(emc_mrs) }, + { "EmcEmrsEmr2", TOKEN(emc_emrs_emr2) }, + { "EmcEmrsEmr3", TOKEN(emc_emrs_emr3) }, + { "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) }, + { "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) }, + { "EmcEmrs", TOKEN(emc_emrs) }, + { "EmcMrw1", TOKEN(emc_mrw1) }, + { "EmcMrw2", TOKEN(emc_mrw2) }, + { "EmcMrw3", TOKEN(emc_mrw3) }, + { "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) }, + { "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) }, + { "EmcAdrCfg", TOKEN(emc_adr_cfg) }, + { "McEmemCfg", TOKEN(mc_emem_cfg) }, + { "EmcCfg2", TOKEN(emc_cfg2) }, + { "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) }, + { "EmcCfgDigDllPeriod", TOKEN(emc_cfg_dig_dll_period) }, + { "EmcCfg", TOKEN(emc_cfg) }, + { "EmcDbg", TOKEN(emc_dbg) }, + { "WarmBootWait", TOKEN(warm_boot_wait) }, + { "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) }, + { "EmcOdtWrite", TOKEN(emc_odt_write) }, + { "EmcOdtRead", TOKEN(emc_odt_read) }, + { "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) }, + { "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) }, + { "EmcDdr2Wait", TOKEN(emc_ddr2_wait) }, + { "PmcDdrPwr", TOKEN(pmc_ddr_pwr) }, + { "EmcClockSource", TOKEN(emc_clock_source) }, + { "EmcClockUsePllMUD", TOKEN(emc_clock_use_pll_mud) }, + { "EmcPinExtraWait", TOKEN(emc_pin_extra_wait) }, + { "EmcTimingControlWait", TOKEN(emc_timing_control_wait) }, + { "EmcWext", TOKEN(emc_wext) }, + { "EmcCtt", TOKEN(emc_ctt) }, + { "EmcCttDuration", TOKEN(emc_ctt_duration) }, + { "EmcPreRefreshReqCnt", TOKEN(emc_prerefresh_req_cnt) }, + { "EmcTxsrDll", TOKEN(emc_txsr_dll) }, + { "EmcCfgRsv", TOKEN(emc_cfg_rsv) }, + { "EmcMrwExtra", TOKEN(emc_mrw_extra) }, + { "EmcWarmBootMrw1", TOKEN(emc_warm_boot_mrw1) }, + { "EmcWarmBootMrw2", TOKEN(emc_warm_boot_mrw2) }, + { "EmcWarmBootMrw3", TOKEN(emc_warm_boot_mrw3) }, + { "EmcWarmBootMrwExtra", TOKEN(emc_warm_boot_mrw_extra) }, + { "EmcWarmBootExtraModeRegWriteEnable", + TOKEN(emc_warm_boot_extramode_reg_write_enable) }, + { "EmcExtraModeRegWriteEnable", TOKEN(emc_extramode_reg_write_enable) }, + { "EmcMrsWaitCnt", TOKEN(emc_mrs_wait_cnt) }, + { "EmcCmdQ", TOKEN(emc_cmd_q) }, + { "EmcMc2EmcQ", TOKEN(emc_mc2emc_q) }, + { "EmcDynSelfRefControl", TOKEN(emc_dyn_self_ref_control) }, + { "AhbArbitrationXbarCtrlMemInitDone", + TOKEN(ahb_arbitration_xbar_ctrl_meminit_done) }, + { "EmcDevSelect", TOKEN(emc_dev_select) }, + { "EmcSelDpdCtrl", TOKEN(emc_sel_dpd_ctrl) }, + { "EmcDllXformDqs0", TOKEN(emc_dll_xform_dqs0) }, + { "EmcDllXformDqs1", TOKEN(emc_dll_xform_dqs1) }, + { "EmcDllXformDqs2", TOKEN(emc_dll_xform_dqs2) }, + { "EmcDllXformDqs3", TOKEN(emc_dll_xform_dqs3) }, + { "EmcDllXformDqs4", TOKEN(emc_dll_xform_dqs4) }, + { "EmcDllXformDqs5", TOKEN(emc_dll_xform_dqs5) }, + { "EmcDllXformDqs6", TOKEN(emc_dll_xform_dqs6) }, + { "EmcDllXformDqs7", TOKEN(emc_dll_xform_dqs7) }, + { "EmcDllXformQUse0", TOKEN(emc_dll_xform_quse0) }, + { "EmcDllXformQUse1", TOKEN(emc_dll_xform_quse1) }, + { "EmcDllXformQUse2", TOKEN(emc_dll_xform_quse2) }, + { "EmcDllXformQUse3", TOKEN(emc_dll_xform_quse3) }, + { "EmcDllXformQUse4", TOKEN(emc_dll_xform_quse4) }, + { "EmcDllXformQUse5", TOKEN(emc_dll_xform_quse5) }, + { "EmcDllXformQUse6", TOKEN(emc_dll_xform_quse6) }, + { "EmcDllXformQUse7", TOKEN(emc_dll_xform_quse7) }, + { "EmcDliTrimTxDqs0", TOKEN(emc_dli_trim_tx_dqs0) }, + { "EmcDliTrimTxDqs1", TOKEN(emc_dli_trim_tx_dqs1) }, + { "EmcDliTrimTxDqs2", TOKEN(emc_dli_trim_tx_dqs2) }, + { "EmcDliTrimTxDqs3", TOKEN(emc_dli_trim_tx_dqs3) }, + { "EmcDliTrimTxDqs4", TOKEN(emc_dli_trim_tx_dqs4) }, + { "EmcDliTrimTxDqs5", TOKEN(emc_dli_trim_tx_dqs5) }, + { "EmcDliTrimTxDqs6", TOKEN(emc_dli_trim_tx_dqs6) }, + { "EmcDliTrimTxDqs7", TOKEN(emc_dli_trim_tx_dqs7) }, + { "EmcDllXformDq0", TOKEN(emc_dll_xform_dq0) }, + { "EmcDllXformDq1", TOKEN(emc_dll_xform_dq1) }, + { "EmcDllXformDq2", TOKEN(emc_dll_xform_dq2) }, + { "EmcDllXformDq3", TOKEN(emc_dll_xform_dq3) }, + { "EmcZcalInterval", TOKEN(emc_zcal_interval) }, + { "EmcZcalInitDev0", TOKEN(emc_zcal_init_dev0) }, + { "EmcZcalInitDev1", TOKEN(emc_zcal_init_dev1) }, + { "EmcZcalInitWait", TOKEN(emc_zcal_init_wait) }, + { "EmcZcalColdBootEnable", TOKEN(emc_zcal_cold_boot_enable) }, + { "EmcZcalWarmBootEnable", TOKEN(emc_zcal_warm_boot_enable) }, + { "EmcMrwLpddr2ZcalWarmBoot", TOKEN(emc_mrw_lpddr2zcal_warm_boot) }, + { "EmcZqCalDdr3WarmBoot", TOKEN(emc_zqcal_ddr3_warm_boot) }, + { "EmcZcalWarmBootWait", TOKEN(emc_zcal_warm_boot_wait) }, + { "EmcMrsWarmBootEnable", TOKEN(emc_mrs_warm_boot_enable) }, + { "EmcMrsExtra", TOKEN(emc_mrs_extra) }, + { "EmcWarmBootMrs", TOKEN(emc_warm_boot_mrs) }, + { "EmcWarmBootEmrs", TOKEN(emc_warm_boot_emrs) }, + { "EmcWarmBootEmr2", TOKEN(emc_warm_boot_emr2) }, + { "EmcWarmBootEmr3", TOKEN(emc_warm_boot_emr3) }, + { "EmcWarmBootMrsExtra", TOKEN(emc_warm_boot_mrs_extra) }, + { "EmcClkenOverride", TOKEN(emc_clken_override) }, + { "EmcExtraRefreshNum", TOKEN(emc_extra_refresh_num) }, + { "EmcClkenOverrideAllWarmBoot", + TOKEN(emc_clken_override_allwarm_boot) }, + { "McClkenOverrideAllWarmBoot", TOKEN(mc_clken_override_allwarm_boot) }, + { "EmcCfgDigDllPeriodWarmBoot", + TOKEN(emc_cfg_dig_dll_period_warm_boot) }, + { "PmcVddpSel", TOKEN(pmc_vddp_sel) }, + { "PmcDdrCfg", TOKEN(pmc_ddr_cfg) }, + { "PmcIoDpdReq", TOKEN(pmc_io_dpd_req) }, + { "PmcENoVttGen", TOKEN(pmc_eno_vtt_gen) }, + { "PmcNoIoPower", TOKEN(pmc_no_io_power) }, + { "EmcXm2CmdPadCtrl", TOKEN(emc_xm2cmd_pad_ctrl) }, + { "EmcXm2CmdPadCtrl2", TOKEN(emc_xm2cmd_pad_ctrl2) }, + { "EmcXm2DqsPadCtrl", TOKEN(emc_xm2dqs_pad_ctrl) }, + { "EmcXm2DqsPadCtrl2", TOKEN(emc_xm2dqs_pad_ctrl2) }, + { "EmcXm2DqsPadCtrl3", TOKEN(emc_xm2dqs_pad_ctrl3) }, + { "EmcXm2DqPadCtrl", TOKEN(emc_xm2dq_pad_ctrl) }, + { "EmcXm2DqPadCtrl2", TOKEN(emc_xm2dq_pad_ctrl2) }, + { "EmcXm2ClkPadCtrl", TOKEN(emc_xm2clk_pad_ctrl) }, + { "EmcXm2CompPadCtrl", TOKEN(emc_xm2comp_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl", TOKEN(emc_xm2vttgen_pad_ctrl) }, + { "EmcXm2VttGenPadCtrl2", TOKEN(emc_xm2vttgen_pad_ctrl2) }, + { "EmcXm2QUsePadCtrl", TOKEN(emc_xm2quse_pad_ctrl) }, + { "McEmemAdrCfg", TOKEN(mc_emem_adr_cfg) }, + { "McEmemAdrCfgDev0", TOKEN(mc_emem_adr_cfg_dev0) }, + { "McEmemAdrCfgDev1", TOKEN(mc_emem_adr_cfg_dev1) }, + { "McEmemArbCfg", TOKEN(mc_emem_arb_cfg) }, + { "McEmemArbOutstandingReq", TOKEN(mc_emem_arb_outstanding_req) }, + { "McEmemArbTimingRcd", TOKEN(mc_emem_arb_timing_rcd) }, + { "McEmemArbTimingRp", TOKEN(mc_emem_arb_timing_rp) }, + { "McEmemArbTimingRc", TOKEN(mc_emem_arb_timing_rc) }, + { "McEmemArbTimingRas", TOKEN(mc_emem_arb_timing_ras) }, + { "McEmemArbTimingFaw", TOKEN(mc_emem_arb_timing_faw) }, + { "McEmemArbTimingRrd", TOKEN(mc_emem_arb_timing_rrd) }, + { "McEmemArbTimingRap2Pre", TOKEN(mc_emem_arb_timing_rap2pre) }, + { "McEmemArbTimingWap2Pre", TOKEN(mc_emem_arb_timing_wap2pre) }, + { "McEmemArbTimingR2R", TOKEN(mc_emem_arb_timing_r2r) }, + { "McEmemArbTimingW2W", TOKEN(mc_emem_arb_timing_w2w) }, + { "McEmemArbTimingR2W", TOKEN(mc_emem_arb_timing_r2w) }, + { "McEmemArbTimingW2R", TOKEN(mc_emem_arb_timing_w2r) }, + { "McEmemArbDaTurns", TOKEN(mc_emem_arb_da_turns) }, + { "McEmemArbDaCovers", TOKEN(mc_emem_arb_da_covers) }, + { "McEmemArbMisc0", TOKEN(mc_emem_arb_misc0) }, + { "McEmemArbMisc1", TOKEN(mc_emem_arb_misc1) }, + { "McEmemArbRing1Throttle", TOKEN(mc_emem_arb_ring1_throttle) }, + { "McEmemArbOverride", TOKEN(mc_emem_arb_override) }, + { "McEmemArbRsv", TOKEN(mc_emem_arb_rsv) }, + { "McClkenOverride", TOKEN(mc_clken_override) }, + { NULL, 0, 0, NULL } +}; + +field_item s_nand_table_t30[] = { + + /* Note: NandTiming2 must appear before NandTiming, because NandTiming + * is a prefix of NandTiming2 and would otherwise match first. + */ + { "ClockDivider", TOKEN(nand_clock_divider) }, + { "BlockSizeLog2", TOKEN(nand_block_size_log2) }, + { "PageSizeLog2", TOKEN(nand_page_size_log2) }, + { "NandAsyncTiming3", TOKEN(nand_async_timing3) }, + { "NandAsyncTiming2", TOKEN(nand_async_timing2) }, + { "NandAsyncTiming1", TOKEN(nand_async_timing1) }, + { "NandAsyncTiming0", TOKEN(nand_async_timing0) }, + { "DisableSyncDDR", TOKEN(nand_disable_sync_ddr) }, + { "NandSDDRTiming1", TOKEN(nand_sddr_timing1) }, + { "NandSDDRTiming0", TOKEN(nand_sddr_timing0) }, + { "NandTDDRTiming1", TOKEN(nand_tddr_timing1) }, + { "NandTDDRTiming0", TOKEN(nand_tddr_timing0) }, + { "NandFbioDqsibDlyByte", TOKEN(nand_fbio_dqsib_dly_byte) }, + { "NandFbioQuseDlyByte", TOKEN(nand_fbio_quse_dly_byte) }, + { "NandFbioCfgQuseLate", TOKEN(nand_fbio_cfg_quse_late) }, + { NULL, 0, 0, NULL } +}; + +field_item s_sdmmc_table_t30[] = { + { "ClockDivider", TOKEN(sdmmc_clock_divider) }, + { "DataWidth", + token_sdmmc_data_width, + field_type_enum, + s_sdmmc_data_width_table_t30 }, + { "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) }, + { "SdController", TOKEN(sdmmc_sd_controller) }, + { NULL, 0, 0, NULL } +}; + +field_item s_spiflash_table_t30[] = { + { "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) }, + { "ClockDivider", TOKEN(spiflash_clock_divider) }, + { "ClockSource", + token_spiflash_clock_source, + field_type_enum, + s_spi_clock_source_table_t30 }, + { NULL, 0, 0, NULL } +}; + +parse_subfield_item s_device_type_table_t30[] = { + { "NandParams.", token_nand_params, + s_nand_table_t30, t30_set_dev_param }, + { "SdmmcParams.", token_sdmmc_params, + s_sdmmc_table_t30, t30_set_dev_param }, + { "SpiFlashParams.", token_spiflash_params, + s_spiflash_table_t30, t30_set_dev_param }, + + { NULL, 0, NULL } +};