From 99515baf0bd567a39abc157434eb001ef2f83fef Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Tue, 7 Jun 2016 17:11:51 -0700 Subject: [PATCH] npcx: gpio: Don't increase priority of SHI_CS for non-SHI boards Systems that don't use SHI don't need elevated SHI_CS interrupt priority. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Ica6e82332bc7ef8f92c00d847cd3ff0df7ede429 Signed-off-by: Shawn Nematbakhsh Reviewed-on: https://chromium-review.googlesource.com/350570 Commit-Ready: Shawn N Tested-by: Shawn N Reviewed-by: Randall Spangler --- chip/npcx/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index 93cfd278ef..5b9c0ec417 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -832,12 +832,16 @@ DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 1); DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 1); DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 1); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 1); +#ifdef CONFIG_HOSTCMD_SPS /* * HACK: Make CS GPIO P0 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to * accommodate P1 CS interrupt. */ DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 0); +#else +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 1); +#endif DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 1); DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 1);