From 9a465855f899b42d91b0ca0b8d3baeabfccce6cf Mon Sep 17 00:00:00 2001 From: Vincent Palatin Date: Wed, 25 Jan 2012 22:42:11 +0000 Subject: [PATCH] NVIC registers are not SoC specific Preparatory work to introduce a second SoC : 5/5 All Cortex-M3/4 have the same NVIC registers at the same address. Signed-off-by: Vincent Palatin BUG=None TEST=run EC firmware on BDS and check a few console commands Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1 --- chip/lm4/registers.h | 6 ------ chip/lm4/system.c | 3 ++- core/cortex-m/cpu.h | 23 +++++++++++++++++++++++ core/cortex-m/task.c | 12 ++++++------ 4 files changed, 31 insertions(+), 13 deletions(-) create mode 100644 core/cortex-m/cpu.h diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h index 0e8b341a36..a379be16d8 100644 --- a/chip/lm4/registers.h +++ b/chip/lm4/registers.h @@ -183,12 +183,6 @@ static inline int lm4_fan_addr(int ch, int offset) #define LM4_DMA_DMACHMAP2 LM4REG(0x400ff518) #define LM4_DMA_DMACHMAP3 LM4REG(0x400ff51c) -#define LM4_NVIC_EN(x) LM4REG(0xe000e100 + 4 * (x)) -#define LM4_NVIC_DIS(x) LM4REG(0xe000e180 + 4 * (x)) -#define LM4_NVIC_PRI(x) LM4REG(0xe000e400 + 4 * (x)) -#define LM4_NVIC_APINT LM4REG(0xe000ed0c) -#define LM4_NVIC_SWTRIG LM4REG(0xe000ef00) - /* IRQ numbers */ #define LM4_IRQ_GPIOA 0 #define LM4_IRQ_GPIOB 1 diff --git a/chip/lm4/system.c b/chip/lm4/system.c index 8cf0dc6bb3..30e2f87b8f 100644 --- a/chip/lm4/system.c +++ b/chip/lm4/system.c @@ -6,6 +6,7 @@ /* System module for Chrome EC */ #include "console.h" +#include "cpu.h" #include "registers.h" #include "system.h" #include "uart.h" @@ -234,7 +235,7 @@ int system_reset(int is_cold) { /* TODO: (crosbug.com/p/7470) support cold boot; this is a warm boot. */ - LM4_NVIC_APINT = 0x05fa0004; + CPU_NVIC_APINT = 0x05fa0004; /* Spin and wait for reboot; should never return */ /* TODO: (crosbug.com/p/7471) should disable task swaps while diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h new file mode 100644 index 0000000000..1ec95442fe --- /dev/null +++ b/core/cortex-m/cpu.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Registers map and defintions for Cortex-MLM4x processor + */ + +#ifndef __CPU_H +#define __CPU_H + +#include + +/* Macro to access 32-bit registers */ +#define CPUREG(addr) (*(volatile uint32_t*)(addr)) + +/* Nested Vectored Interrupt Controller */ +#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x)) +#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x)) +#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) +#define CPU_NVIC_APINT CPUREG(0xe000ed0c) +#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00) + +#endif /* __CPU_H */ diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 2e0821e80f..65e86f423e 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -10,10 +10,10 @@ #include "config.h" #include "atomic.h" #include "console.h" +#include "cpu.h" #include "task.h" #include "timer.h" #include "uart.h" -#include "registers.h" #include "util.h" /** @@ -253,19 +253,19 @@ uint32_t task_wait_msg(int timeout_us) void task_enable_irq(int irq) { - LM4_NVIC_EN(irq / 32) = 1 << (irq % 32); + CPU_NVIC_EN(irq / 32) = 1 << (irq % 32); } void task_disable_irq(int irq) { - LM4_NVIC_DIS(irq / 32) = 1 << (irq % 32); + CPU_NVIC_DIS(irq / 32) = 1 << (irq % 32); } void task_trigger_irq(int irq) { - LM4_NVIC_SWTRIG = irq; + CPU_NVIC_SWTRIG = irq; } @@ -285,8 +285,8 @@ static void __nvic_init_irqs(void) uint8_t irq = __irqprio[i].irq; uint8_t prio = __irqprio[i].priority; uint32_t prio_shift = irq % 4 * 8 + 5; - LM4_NVIC_PRI(irq / 4) = - (LM4_NVIC_PRI(irq / 4) & + CPU_NVIC_PRI(irq / 4) = + (CPU_NVIC_PRI(irq / 4) & ~(0x7 << prio_shift)) | (prio << prio_shift); }