From 9b815745fa3329481de7dbed6adcb4106bbb9a78 Mon Sep 17 00:00:00 2001 From: Bill Richardson Date: Mon, 2 May 2016 09:43:46 -0700 Subject: [PATCH] Cr50: Lower all runlevel permissions to medium Two permission registers are already lowered. This adds the remaining two. BUG=chrome-os-partner:52994 BRANCH=none TEST=make buildall; run on Cr50 USB works, SPI works, sleep and deep sleep work, tpmtest.py works. Change-Id: Ifb27d5be81f10537114f4702addb58c6d7e1630c Signed-off-by: Bill Richardson Reviewed-on: https://chromium-review.googlesource.com/342455 Reviewed-by: Vadim Bendebury --- board/cr50/board.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/cr50/board.c b/board/cr50/board.c index 9ecc75c28a..678990e607 100644 --- a/board/cr50/board.c +++ b/board/cr50/board.c @@ -69,8 +69,16 @@ enum permission_level { static void init_runlevel(const enum permission_level desired_level) { volatile uint32_t *const reg_addrs[] = { + /* CPU's use of the system peripheral bus */ GREG32_ADDR(GLOBALSEC, CPU0_S_PERMISSION), + /* CPU's use of the system bus via the debug access port */ + GREG32_ADDR(GLOBALSEC, CPU0_S_DAP_PERMISSION), + /* DMA's use of the system peripheral bus */ GREG32_ADDR(GLOBALSEC, DDMA0_PERMISSION), + /* Current software level affects which (if any) scratch + * registers can be used for a warm boot hardware-verified + * jump. */ + GREG32_ADDR(GLOBALSEC, SOFTWARE_LVL), }; int i;