From a0f1cda90197bad78a98dfbe288779378327c690 Mon Sep 17 00:00:00 2001 From: CHLin Date: Thu, 8 Dec 2016 11:02:23 +0800 Subject: [PATCH] npcx: lpc: Fix KB malfunction after power-key off and then on The original thought of setting LRESET_PLTRST_MODE to 1 is to remove the need to reinitialize host module registers whenever LRESET# occurs in order to save time when boot-up. However, some of these registers will be reset by core domain reset. It means every time LRESET is de-asserted, we need to initialize the host setting again. Therefore, setting LRESET_PLTRST_MODE to 1 is unnecessary and sometimes dangerous. If BIOS believes LRESET will reset ec's host state machine to default but ec not, it will cause unexpected behavior. Modified drivers: 1. lpc.c: allow LRESET/PLTRST generate host domain reset BUG=chrome-os-partner:60211 BRANCH:none TEST=make buildall. run "dut-control pwr_button:press; sleep 11; dut-control pwr_button:release; sleep 7; dut-control pwr_button:press; sleep 1; dut-control pwr_button:release". Verify keyboard works normally. Change-Id: I94d428cde69f828468547c44844983f25686ea04 Signed-off-by: CHLin Reviewed-on: https://chromium-review.googlesource.com/417745 Commit-Ready: Daisuke Nojiri Tested-by: Daisuke Nojiri Reviewed-by: Aaron Durbin Reviewed-by: Daisuke Nojiri --- chip/npcx/lpc.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 7f569af078..63507ce1f1 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -811,9 +811,6 @@ void host_register_init(void) /* enable SHM */ lpc_sib_write_reg(SIO_OFFSET, 0x30, 0x01); - /* An active LRESET or PLTRST does not generate host domain reset */ - SET_BIT(NPCX_RSTCTL, NPCX_RSTCTL_LRESET_PLTRST_MODE); - CPRINTS("Host settings are done!"); }