From 5f70d8de5b696a7b21284d96839caa981c8fdf30 Mon Sep 17 00:00:00 2001 From: Matt Ma Date: Wed, 22 Nov 2017 19:31:28 +0800 Subject: [PATCH] Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS This patch replaces the macro ASM_ASSERTION with the macro ENABLE_ASSERTIONS in ARM Cortex-A53/57/72 MPCore Processor related files. There is build error when ASM_ASSERTION is set to 1 and ENABLE_ASSERTIONS is set to 0 because function asm_assert in common/aarch32/debug.S is defined in the macro ENABLE_ASSERTIONS but is called with the macro ASM_ASSERTION. There is also the indication to use ENABLE_ASSERTIONS but not ASM_ASSERTION in the Makefile. Signed-off-by: Matt Ma --- lib/cpus/aarch32/cortex_a53.S | 4 ++-- lib/cpus/aarch32/cortex_a57.S | 4 ++-- lib/cpus/aarch32/cortex_a72.S | 4 ++-- make_helpers/defaults.mk | 3 --- 4 files changed, 6 insertions(+), 9 deletions(-) diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S index 74cedc35c7..1647e169f6 100644 --- a/lib/cpus/aarch32/cortex_a53.S +++ b/lib/cpus/aarch32/cortex_a53.S @@ -174,7 +174,7 @@ func cortex_a53_core_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) @@ -204,7 +204,7 @@ func cortex_a53_cluster_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S index b5189e77fa..64a6d67451 100644 --- a/lib/cpus/aarch32/cortex_a57.S +++ b/lib/cpus/aarch32/cortex_a57.S @@ -406,7 +406,7 @@ func cortex_a57_core_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) @@ -448,7 +448,7 @@ func cortex_a57_cluster_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S index 69cc2ea558..7550520643 100644 --- a/lib/cpus/aarch32/cortex_a72.S +++ b/lib/cpus/aarch32/cortex_a72.S @@ -120,7 +120,7 @@ func cortex_a72_core_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) @@ -167,7 +167,7 @@ func cortex_a72_cluster_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 660e54e751..e0d822dfe2 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -24,9 +24,6 @@ ARM_ARCH_MINOR := 0 # in EL3. The platform port can change this value if needed. ARM_GIC_ARCH := 2 -# Flag used to indicate if ASM_ASSERTION should be enabled for the build. -ASM_ASSERTION := 0 - # Base commit to perform code check on BASE_COMMIT := origin/master