From ad8a61232105e028fea1e7c6ee420e05fcd98637 Mon Sep 17 00:00:00 2001 From: Aseda Aboagye Date: Mon, 21 May 2018 13:48:39 -0700 Subject: [PATCH] npcx7: Export entering PSL mode. Some boards (like nocturne) use PSL mode, but the deassertion of PSL_OUT does not directly cut the EC's VCC1 rail. Therefore, the board needs to implement a board specific implementation of hibernate while also being able to configure PSL mode. This commit exports a function of entering PSL mode which could be used in a board specific hibernate implementation. BUG=b:79713379 BRANCH=poppy TEST=`make -j buildall` Change-Id: I8debcae5e713b85c6d23ee3419416b6ae5d5dbf0 Signed-off-by: Aseda Aboagye Reviewed-on: https://chromium-review.googlesource.com/1067891 Commit-Ready: Aseda Aboagye Tested-by: Aseda Aboagye Reviewed-by: Furquan Shaikh --- chip/npcx/system-npcx7.c | 8 ++++++-- chip/npcx/system_chip.h | 3 +++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c index c476945e42..4651e425e1 100644 --- a/chip/npcx/system-npcx7.c +++ b/chip/npcx/system-npcx7.c @@ -32,8 +32,7 @@ void system_mpu_config(void) #error "Do not enable CONFIG_HIBERNATE_PSL if npcx ec doesn't support PSL mode!" #endif -/* Hibernate function implemented by PSL (Power Switch Logic) mode. */ -void __keep __attribute__ ((noreturn)) __enter_hibernate_in_psl(void) +void system_enter_psl_mode(void) { /* Configure pins from GPIOs to PSL which rely on VSBY power rail. */ gpio_config_module(MODULE_PMU, 1); @@ -49,7 +48,12 @@ void __keep __attribute__ ((noreturn)) __enter_hibernate_in_psl(void) * setting bit 5 of PDOUT(8). */ SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5); +} +/* Hibernate function implemented by PSL (Power Switch Logic) mode. */ +void __keep __attribute__ ((noreturn)) __enter_hibernate_in_psl(void) +{ + system_enter_psl_mode(); /* Spin and wait for PSL cuts power; should never return */ while (1) ; diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h index a9155a52dd..da400f79bb 100644 --- a/chip/npcx/system_chip.h +++ b/chip/npcx/system_chip.h @@ -67,6 +67,9 @@ extern unsigned int __flash_lplfw_end; /* Configure PSL mode setting for the wake-up pins. */ int system_config_psl_mode(enum gpio_signal signal); +/* Configure PSL pins and enter PSL mode. */ +void system_enter_psl_mode(void); + /* End address for hibernate utility; defined in linker script */ extern unsigned int __after_init_end;