From af2c11e3e39621bc5677b4996fcbbe0e0afe224f Mon Sep 17 00:00:00 2001 From: Randall Spangler Date: Fri, 15 Nov 2013 16:59:10 -0800 Subject: [PATCH] stm32: Flush UART buffer before changing EC core clock speed Otherwise UART output gets garbled because there's a delay between changing core clock and the UART divider. Fortunately, the glitch is cosmetic and doesn't affect proper EC operation. BUG=chrome-os-partner:23982 BRANCH=none TEST=power on, power off on pit or nyan --> no UART glitch Change-Id: I32bef119b850a340fc616b83a4b088b20f17267f Signed-off-by: Randall Spangler Reviewed-on: https://chromium-review.googlesource.com/177087 Reviewed-by: Yung-chieh Lo Tested-by: Yung-chieh Lo Commit-Queue: Yung-chieh Lo --- chip/stm32/clock-stm32l.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c index 3cb09f69bf..b2de4e8073 100644 --- a/chip/stm32/clock-stm32l.c +++ b/chip/stm32/clock-stm32l.c @@ -148,8 +148,14 @@ void clock_enable_module(enum module_id module, int enable) new_mask = clock_mask & ~(1 << module); /* Only change clock if needed */ - if ((!!new_mask) != (!!clock_mask)) + if ((!!new_mask) != (!!clock_mask)) { + + /* Flush UART before switching clock speed */ + cflush(); + clock_set_osc(new_mask ? OSC_HSI : OSC_MSI); + } + clock_mask = new_mask; }