From b2d6bf0ada32042692bfec9ae03586ff0eefe0b7 Mon Sep 17 00:00:00 2001 From: Vijay Hiremath Date: Sat, 14 Oct 2017 14:14:14 -0700 Subject: [PATCH] GLKRVP: Correct GPIO assignment for PCH_WAKE_L BUG=b:67797598 BRANCH=glkrvp TEST=In S3, toggling PCH_WAKE_L wakes system to S0. Change-Id: If4d6786d8b24488c11f7894499c7e19f43a9b7f8 Signed-off-by: Vijay Hiremath Reviewed-on: https://chromium-review.googlesource.com/719486 Commit-Ready: Vijay P Hiremath Tested-by: Vijay P Hiremath Reviewed-by: Shawn N --- board/glkrvp/gpio.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/glkrvp/gpio.inc b/board/glkrvp/gpio.inc index 2571c57a2f..ea1dc28d03 100644 --- a/board/glkrvp/gpio.inc +++ b/board/glkrvp/gpio.inc @@ -28,7 +28,7 @@ GPIO_INT(EC_VOLDN_BTN_ODL, PIN(3, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_inter GPIO(PCH_SMI_L, PIN(C, 6), GPIO_ODR_HIGH) /* EC_SMI_ODL */ GPIO(PCH_SCI_L, PIN(7, 6), GPIO_ODR_HIGH) /* EC_SCI_ODL */ GPIO(PCH_PWRBTN_L, PIN(7, 5), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ -GPIO(PCH_WAKE_L, PIN(7, 0), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ +GPIO(PCH_WAKE_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ GPIO(PCH_SYS_PWROK, PIN(3, 5), GPIO_OUT_LOW) /* EC_PCH_PWROK */ GPIO(ENABLE_BACKLIGHT, PIN(9, 7), GPIO_ODR_HIGH) /* EC_BL_EN_OD */ GPIO(ENTERING_RW, PIN(A, 7), GPIO_OUTPUT) /* EC_ENTERING_RW */ @@ -75,6 +75,7 @@ GPIO(NC_60, PIN(6, 0), GPIO_INPUT) GPIO(NC_61, PIN(6, 1), GPIO_INPUT) GPIO(NC_67, PIN(6, 7), GPIO_INPUT) +GPIO(NC_70, PIN(7, 0), GPIO_INPUT) GPIO(NC_71, PIN(7, 1), GPIO_INPUT) GPIO(NC_73, PIN(7, 3), GPIO_INPUT) GPIO(NC_74, PIN(7, 4), GPIO_INPUT) @@ -87,7 +88,6 @@ GPIO(NC_84, PIN(8, 4), GPIO_INPUT) GPIO(NC_B1, PIN(B, 1), GPIO_INPUT) GPIO(NC_C0, PIN(C, 0), GPIO_INPUT) -GPIO(NC_C1, PIN(C, 1), GPIO_INPUT) GPIO(NC_C2, PIN(C, 2), GPIO_INPUT) GPIO(NC_C3, PIN(C, 3), GPIO_INPUT) GPIO(NC_C4, PIN(C, 4), GPIO_INPUT)