diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index a9706ba787..db9be12b1d 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -8,7 +8,7 @@ #include "clock.h" #include "common.h" #include "gpio.h" -#include "gpio_wui.h" +#include "gpio_chip.h" #include "keyboard_config.h" #include "hooks.h" #include "registers.h" @@ -22,6 +22,14 @@ #include "ec_commands.h" #include "host_command.h" +#if !(DEBUG_GPIO) +#define CPUTS(...) +#define CPRINTS(...) +#else +#define CPUTS(outstr) cputs(CC_GPIO, outstr) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#endif + struct npcx_wui { uint8_t table : 2; uint8_t group : 3; @@ -42,9 +50,6 @@ struct npcx_gpio { BUILD_ASSERT(sizeof(struct npcx_gpio) == 1); -#define NPCX_GPIO_NONE { 0, 0, 0} -#define NPCX_GPIO(port, pin) {GPIO_PORT_##port, pin, 1} - struct npcx_alt { uint8_t group : 4; uint8_t bit : 3; @@ -58,134 +63,16 @@ struct gpio_alt_map { BUILD_ASSERT(sizeof(struct gpio_alt_map) == 2); -/* Convenient macros to initialize the gpio_alt_table */ -#define NPCX_ALT(grp, pin) { ALT_GROUP_##grp, NPCX_DEVALT##grp##_##pin, 0 } -#define NPCX_ALT_INV(grp, pin) { ALT_GROUP_##grp, NPCX_DEVALT##grp##_##pin, 1 } - -/* TODO: Index this table on GPIO# */ -const struct gpio_alt_map gpio_alt_table[] = { - /* I2C Module */ - { NPCX_GPIO(B, 2), NPCX_ALT(2, I2C0_1_SL)}, /* SMB0SDA1 */ - { NPCX_GPIO(B, 3), NPCX_ALT(2, I2C0_1_SL)}, /* SMB0SCL1 */ - { NPCX_GPIO(B, 4), NPCX_ALT(2, I2C0_0_SL)}, /* SMB0SDA0 */ - { NPCX_GPIO(B, 5), NPCX_ALT(2, I2C0_0_SL)}, /* SMB0SCL0 */ - { NPCX_GPIO(8, 7), NPCX_ALT(2, I2C1_0_SL)}, /* SMB1SDA */ - { NPCX_GPIO(9, 0), NPCX_ALT(2, I2C1_0_SL)}, /* SMB1SCL */ - { NPCX_GPIO(9, 1), NPCX_ALT(2, I2C2_0_SL)}, /* SMB2SDA */ - { NPCX_GPIO(9, 2), NPCX_ALT(2, I2C2_0_SL)}, /* SMB2SCL */ - { NPCX_GPIO(D, 0), NPCX_ALT(2, I2C3_0_SL)}, /* SMB3SDA */ - { NPCX_GPIO(D, 1), NPCX_ALT(2, I2C3_0_SL)}, /* SMB3SCL */ - /* ADC Module */ - { NPCX_GPIO(4, 5), NPCX_ALT(6, ADC0_SL)}, /* ADC0 */ - { NPCX_GPIO(4, 4), NPCX_ALT(6, ADC1_SL)}, /* ADC1 */ - { NPCX_GPIO(4, 3), NPCX_ALT(6, ADC2_SL)}, /* ADC2 */ - { NPCX_GPIO(4, 2), NPCX_ALT(6, ADC3_SL)}, /* ADC3 */ - { NPCX_GPIO(4, 1), NPCX_ALT(6, ADC4_SL)}, /* ADC4 */ - /* UART Module 1/2 */ -#if NPCX_UART_MODULE2 - { NPCX_GPIO(6, 4), NPCX_ALT(C, UART_SL2)}, /* CR_SIN */ - { NPCX_GPIO(6, 5), NPCX_ALT(C, UART_SL2)}, /* CR_SOUT */ -#else - { NPCX_GPIO(1, 0), NPCX_ALT(9, NO_KSO08_SL)}, /* CR_SIN/KSO09 */ - { NPCX_GPIO(1, 1), NPCX_ALT(9, NO_KSO09_SL)}, /* CR_SOUT/KSO10 */ -#endif - /* SPI Module */ - { NPCX_GPIO(9, 5), NPCX_ALT(0, SPIP_SL)}, /* SPIP_MISO */ - { NPCX_GPIO(A, 5), NPCX_ALT(0, SPIP_SL)}, /* SPIP_CS1 */ - { NPCX_GPIO(A, 3), NPCX_ALT(0, SPIP_SL)}, /* SPIP_MOSI */ - { NPCX_GPIO(A, 1), NPCX_ALT(0, SPIP_SL)}, /* SPIP_SCLK */ - /* PWM Module */ - { NPCX_GPIO(C, 3), NPCX_ALT(4, PWM0_SL)}, /* PWM0 */ - { NPCX_GPIO(C, 2), NPCX_ALT(4, PWM1_SL)}, /* PWM1 */ - { NPCX_GPIO(C, 4), NPCX_ALT(4, PWM2_SL)}, /* PWM2 */ - { NPCX_GPIO(8, 0), NPCX_ALT(4, PWM3_SL)}, /* PWM3 */ - { NPCX_GPIO(B, 6), NPCX_ALT(4, PWM4_SL)}, /* PWM4 */ - { NPCX_GPIO(B, 7), NPCX_ALT(4, PWM5_SL)}, /* PWM5 */ - { NPCX_GPIO(C, 0), NPCX_ALT(4, PWM6_SL)}, /* PWM6 */ - { NPCX_GPIO(6, 0), NPCX_ALT(4, PWM7_SL)}, /* PWM7 */ - /* MFT Module */ -#if NPCX_TACH_SEL2 - { NPCX_GPIO(9, 3), NPCX_ALT(C, TA1_SL2)},/* TA1_SEL2 */ - { NPCX_GPIO(A, 6), NPCX_ALT(C, TA2_SL2)},/* TA2_SEL2 */ -#else - { NPCX_GPIO(4, 0), NPCX_ALT(3, TA1_SL1)},/* TA1_SEL1 */ - { NPCX_GPIO(7, 3), NPCX_ALT(3, TA2_SL1)},/* TA2_SEL1 */ -#endif - /* Keyboard Scan Module (Inputs) */ - { NPCX_GPIO(3, 1), NPCX_ALT_INV(7, NO_KSI0_SL)},/* KSI0 */ - { NPCX_GPIO(3, 0), NPCX_ALT_INV(7, NO_KSI1_SL)},/* KSI1 */ - { NPCX_GPIO(2, 7), NPCX_ALT_INV(7, NO_KSI2_SL)},/* KSI2 */ - { NPCX_GPIO(2, 6), NPCX_ALT_INV(7, NO_KSI3_SL)},/* KSI3 */ - { NPCX_GPIO(2, 5), NPCX_ALT_INV(7, NO_KSI4_SL)},/* KSI4 */ - { NPCX_GPIO(2, 4), NPCX_ALT_INV(7, NO_KSI5_SL)},/* KSI5 */ - { NPCX_GPIO(2, 3), NPCX_ALT_INV(7, NO_KSI6_SL)},/* KSI6 */ - { NPCX_GPIO(2, 2), NPCX_ALT_INV(7, NO_KSI7_SL)},/* KSI7 */ - /* Keyboard Scan Module (Outputs) */ - { NPCX_GPIO(2, 1), NPCX_ALT_INV(8, NO_KSO00_SL)},/* KSO00 */ - { NPCX_GPIO(2, 0), NPCX_ALT_INV(8, NO_KSO01_SL)},/* KSO01 */ - { NPCX_GPIO(1, 7), NPCX_ALT_INV(8, NO_KSO02_SL)},/* KSO02 */ - { NPCX_GPIO(1, 6), NPCX_ALT_INV(8, NO_KSO03_SL)},/* KSO03 */ - { NPCX_GPIO(1, 5), NPCX_ALT_INV(8, NO_KSO04_SL)},/* KSO04 */ - { NPCX_GPIO(1, 4), NPCX_ALT_INV(8, NO_KSO05_SL)},/* KSO05 */ - { NPCX_GPIO(1, 3), NPCX_ALT_INV(8, NO_KSO06_SL)},/* KSO06 */ - { NPCX_GPIO(1, 2), NPCX_ALT_INV(8, NO_KSO07_SL)},/* KSO07 */ - { NPCX_GPIO(1, 1), NPCX_ALT_INV(9, NO_KSO08_SL)},/* KSO08 */ - { NPCX_GPIO(1, 0), NPCX_ALT_INV(9, NO_KSO09_SL)},/* KSO09 */ - { NPCX_GPIO(0, 7), NPCX_ALT_INV(9, NO_KSO10_SL)},/* KSO10 */ - { NPCX_GPIO(0, 6), NPCX_ALT_INV(9, NO_KSO11_SL)},/* KSO11 */ - { NPCX_GPIO(0, 5), NPCX_ALT_INV(9, NO_KSO12_SL)},/* KSO12 */ - { NPCX_GPIO(0, 4), NPCX_ALT_INV(9, NO_KSO13_SL)},/* KSO13 */ - { NPCX_GPIO(8, 2), NPCX_ALT_INV(9, NO_KSO14_SL)},/* KSO14 */ - { NPCX_GPIO(8, 3), NPCX_ALT_INV(9, NO_KSO15_SL)},/* KSO15 */ - { NPCX_GPIO(0, 3), NPCX_ALT_INV(A, NO_KSO16_SL)},/* KSO16 */ - { NPCX_GPIO(B, 1), NPCX_ALT_INV(A, NO_KSO17_SL)},/* KSO17 */ - /* Clock module */ - { NPCX_GPIO(7, 5), NPCX_ALT(A, 32K_OUT_SL)}, /* 32KHZ_OUT */ - { NPCX_GPIO(E, 7), NPCX_ALT(A, 32KCLKIN_SL)}, /* 32KCLKIN */ -}; +/* Constants for GPIO alternative mapping */ +const struct gpio_alt_map gpio_alt_table[] = NPCX_ALT_TABLE; struct gpio_lvol_item { struct npcx_gpio lvol_gpio[8]; }; -const struct gpio_lvol_item gpio_lvol_table[] = { - /* Low-Voltage GPIO Control 0 */ - { { NPCX_GPIO(B, 5), - NPCX_GPIO(B, 4), - NPCX_GPIO(B, 3), - NPCX_GPIO(B, 2), - NPCX_GPIO(9, 0), - NPCX_GPIO(8, 7), - NPCX_GPIO(0, 0), - NPCX_GPIO(3, 3), }, }, - /* Low-Voltage GPIO Control 1 */ - { { NPCX_GPIO(9, 2), - NPCX_GPIO(9, 1), - NPCX_GPIO(D, 1), - NPCX_GPIO(D, 0), - NPCX_GPIO(3, 6), - NPCX_GPIO(6, 4), - NPCX_GPIO(6, 5), - NPCX_GPIO_NONE , }, }, - /* Low-Voltage GPIO Control 2 */ - { { NPCX_GPIO(7, 4), - NPCX_GPIO(8, 4), - NPCX_GPIO(8, 5), - NPCX_GPIO(7, 3), - NPCX_GPIO(C, 1), - NPCX_GPIO(C, 7), - NPCX_GPIO(E, 7), - NPCX_GPIO(3, 4), }, }, - /* Low-Voltage GPIO Control 3 */ - { { NPCX_GPIO(C, 6), - NPCX_GPIO(3, 7), - NPCX_GPIO(4, 0), - NPCX_GPIO(7, 1), - NPCX_GPIO(8, 2), - NPCX_GPIO(7, 5), - NPCX_GPIO(8, 0), - NPCX_GPIO(C, 5), }, }, -}; +/* Constants for GPIO low-voltage mapping */ +const struct gpio_lvol_item gpio_lvol_table[] = NPCX_LVOL_TABLE; + /*****************************************************************************/ /* Internal functions */ @@ -218,6 +105,9 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit, int8_t func) } } + if (func > 0) + CPRINTS("Warn! No alter func in port%d, pin%d", port, bit); + return -1; } @@ -309,6 +199,10 @@ void gpio_low_voltage_level_sel(uint8_t port, uint8_t mask, uint8_t low_voltage) } } + + if (low_voltage) + CPRINTS("Warn! No low voltage support in port%d, mask%d\n", + port, mask); } /* * Make sure the bit depth of low voltage register. @@ -344,6 +238,12 @@ void gpio_set_level(enum gpio_signal signal, int value) void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) { + /* If all GPIO pins are locked, return directly */ +#if defined(CHIP_FAMILY_NPCX7) + if ((NPCX_PLOCK_CTL(port) & mask) == mask) + return; +#endif + /* * Configure pin as input, if requested. Output is configured only * after setting all other attributes, so as not to create a @@ -402,6 +302,12 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Configure pin as output, if requested 0:input 1:output */ if (flags & GPIO_OUTPUT) NPCX_PDIR(port) |= mask; + + /* Lock GPIO output and configuration if need */ +#if defined(CHIP_FAMILY_NPCX7) + if (flags & GPIO_LOCKED) + NPCX_PLOCK_CTL(port) |= mask; +#endif } int gpio_enable_interrupt(enum gpio_signal signal) @@ -528,6 +434,9 @@ static void gpio_init(void) task_enable_irq(NPCX_IRQ_WKINTF_1); task_enable_irq(NPCX_IRQ_WKINTG_1); task_enable_irq(NPCX_IRQ_WKINTH_1); +#if defined(CHIP_FAMILY_NPCX7) + task_enable_irq(NPCX_IRQ_WKINTFG_2); +#endif } DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); @@ -625,6 +534,27 @@ void __gpio_rtc_interrupt(void) } } +void __gpio_wk1h_interrupt(void) +{ +#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) + /* Handle the interrupt from UART wakeup event */ + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) { + /* + * Disable WKEN bit to avoid the other unnecessary interrupts + * from the coming data bits after the start bit. (Pending bit + * of CR_SIN is set when a high-to-low transaction occurs.) + */ + CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7); + /* Clear pending bit for WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7); + /* Notify the clock module that the console is in use. */ + clock_refresh_console_in_use(); + } else +#endif + gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8)); +} + GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2)); GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3)); GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1)); @@ -637,7 +567,9 @@ GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4)); GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5)); GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6)); GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7)); -GPIO_IRQ_FUNC(__gpio_wk1h_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8)); +#if defined(CHIP_FAMILY_NPCX7) +GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6)); +#endif DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 2); DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 2); @@ -662,6 +594,8 @@ DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); #endif DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 2); DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 2); - +#if defined(CHIP_FAMILY_NPCX7) +DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 2); +#endif #undef GPIO_IRQ_FUNC diff --git a/chip/npcx/gpio_chip-npcx5.h b/chip/npcx/gpio_chip-npcx5.h new file mode 100644 index 0000000000..0dbda59200 --- /dev/null +++ b/chip/npcx/gpio_chip-npcx5.h @@ -0,0 +1,350 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_GPIO_CHIP_NPCX5_H +#define __CROS_EC_GPIO_CHIP_NPCX5_H + +/*****************************************************************************/ +/* Macro functions for MIWU mapping table */ + +/* MIWU0 */ +/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */ +#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0) +#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1) +#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2) +#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3) +#define NPCX_WUI_GPIO_8_4 WUI(0, MIWU_GROUP_1, 4) +#define NPCX_WUI_GPIO_8_5 WUI(0, MIWU_GROUP_1, 5) +#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6) +#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7) + +/* Group B: NPCX_IRQ_TWD_WKINTB_0 */ +#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0) +#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1) +#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2) +#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3) +#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4) +#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5) + +/* Group C: NPCX_IRQ_WKINTC_0 */ +#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1) +#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3) +#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5) +#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7) + +/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */ +#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0) +#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1) +#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2) +#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5) +#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6) + +/* Group E: NPCX_IRQ_WKINTEFGH_0 */ +#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0) +#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1) +#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2) +#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4) + +/* Group F: NPCX_IRQ_WKINTEFGH_0 */ +#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0) +#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1) +#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2) +#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3) +#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4) +#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5) +#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6) +#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7) + +/* Group G: NPCX_IRQ_WKINTEFGH_0 */ +#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0) +#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1) +#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2) +#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3) + +/* Group H: NPCX_IRQ_WKINTEFGH_0 */ +#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) + +/* MIWU1 */ +/* Group A: NPCX_IRQ_WKINTA_1 */ +#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0) +#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1) +#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2) +#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3) +#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4) +#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5) +#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6) +#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7) + +/* Group B: NPCX_IRQ_WKINTB_1 */ +#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0) +#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1) +#define NPCX_WUI_GPIO_1_3 WUI(1, MIWU_GROUP_2, 3) +#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4) +#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5) +#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6) +#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7) + +/* Group C: NPCX_IRQ_KSI_WKINTC_1 */ +#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0) +#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1) +#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2) +#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3) +#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4) +#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5) +#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6) +#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7) + +/* Group D: NPCX_IRQ_WKINTD_1 */ +#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0) +#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1) +#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3) +#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4) +#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6) +#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7) + +/* Group E: NPCX_IRQ_WKINTE_1 */ +#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0) +#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1) +#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2) +#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3) +#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4) +#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5) +#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6) +#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7) + +/* Group F: NPCX_IRQ_WKINTF_1 */ +#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0) +#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1) +#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2) +#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3) +#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4) +#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5) +#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6) +#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7) + +/* Group G: NPCX_IRQ_WKINTG_1 */ +#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0) +#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1) +#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2) +#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3) +#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4) +#define NPCX_WUI_GPIO_6_5 WUI(1, MIWU_GROUP_7, 5) +#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) + +/* Group H: NPCX_IRQ_WKINTH_1 */ +#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0) +#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1) +#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2) +#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3) +#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4) +#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5) +#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6) + +/*****************************************************************************/ +/* Macro functions for Alternative mapping table */ + +/* I2C Module */ +#define NPCX_ALT_I2C0SDA1 ALT(B, 2, NPCX_ALT(2, I2C0_1_SL)) /* SMB0SDA1 */ +#define NPCX_ALT_I2C0SCL1 ALT(B, 3, NPCX_ALT(2, I2C0_1_SL)) /* SMB0SCL1 */ +#define NPCX_ALT_I2C0SDA0 ALT(B, 4, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SDA0 */ +#define NPCX_ALT_I2C0SCL0 ALT(B, 5, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SCL0 */ +#define NPCX_ALT_I2C1SDA ALT(8, 7, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SDA */ +#define NPCX_ALT_I2C1SCL ALT(9, 0, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SCL */ +#define NPCX_ALT_I2C2SDA ALT(9, 1, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SDA */ +#define NPCX_ALT_I2C2SCL ALT(9, 2, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SCL */ +#define NPCX_ALT_I2C3SDA ALT(D, 0, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SDA */ +#define NPCX_ALT_I2C3SCL ALT(D, 1, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SCL */ + +/* ADC Module */ +#define NPCX_ALT_ADC0 ALT(4, 5, NPCX_ALT(6, ADC0_SL)) /* ADC0 */ +#define NPCX_ALT_ADC1 ALT(4, 4, NPCX_ALT(6, ADC1_SL)) /* ADC1 */ +#define NPCX_ALT_ADC2 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2 */ +#define NPCX_ALT_ADC3 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3 */ +#define NPCX_ALT_ADC4 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4 */ + +/* UART Module 1/2 */ +#if NPCX_UART_MODULE2 +#define NPCX_ALT_CR_SIN ALT(6, 4, NPCX_ALT(C, UART_SL2)) /* CR_SIN2 */ +#define NPCX_ALT_CR_SOUT ALT(6, 5, NPCX_ALT(C, UART_SL2)) /* CR_SOUT2 */ +#else +#define NPCX_ALT_CR_SIN ALT(1, 0, NPCX_ALT(9, NO_KSO08_SL)) /* CR_SIN */ +#define NPCX_ALT_CR_SOUT ALT(1, 1, NPCX_ALT(9, NO_KSO09_SL)) /* CR_SOUT */ +#endif + +/* SPI Module */ +#define NPCX_ALT_SPIP_MISO ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */ +#define NPCX_ALT_SPIP_CS1 ALT(A, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_CS1 */ +#define NPCX_ALT_SPIP_MOSI ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */ +#define NPCX_ALT_SPIP_SCLK ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */ + +/* PWM Module */ +#define NPCX_ALT_PWM0 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */ +#define NPCX_ALT_PWM1 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ +#define NPCX_ALT_PWM2 ALT(C, 4, NPCX_ALT(4, PWM2_SL)) /* PWM2 */ +#define NPCX_ALT_PWM3 ALT(8, 0, NPCX_ALT(4, PWM3_SL)) /* PWM3 */ +#define NPCX_ALT_PWM4 ALT(B, 6, NPCX_ALT(4, PWM4_SL)) /* PWM4 */ +#define NPCX_ALT_PWM5 ALT(B, 7, NPCX_ALT(4, PWM5_SL)) /* PWM5 */ +#define NPCX_ALT_PWM6 ALT(C, 0, NPCX_ALT(4, PWM6_SL)) /* PWM6 */ +#define NPCX_ALT_PWM7 ALT(6, 0, NPCX_ALT(4, PWM7_SL)) /* PWM7 */ + +/* MFT Module */ +#if NPCX_TACH_SEL2 +#define NPCX_ALT_TA1_TACH1 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */ +#define NPCX_ALT_TA2_TACH2 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */ +#else +#define NPCX_ALT_TA1_TACH1 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */ +#define NPCX_ALT_TA2_TACH2 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */ +#endif + +/* Keyboard Scan Module (Inputs) */ +#define NPCX_ALT_KSI0 ALT(3, 1, NPCX_ALT_INV(7, NO_KSI0_SL)) /* KSI0 */ +#define NPCX_ALT_KSI1 ALT(3, 0, NPCX_ALT_INV(7, NO_KSI1_SL)) /* KSI1 */ +#define NPCX_ALT_KSI2 ALT(2, 7, NPCX_ALT_INV(7, NO_KSI2_SL)) /* KSI2 */ +#define NPCX_ALT_KSI3 ALT(2, 6, NPCX_ALT_INV(7, NO_KSI3_SL)) /* KSI3 */ +#define NPCX_ALT_KSI4 ALT(2, 5, NPCX_ALT_INV(7, NO_KSI4_SL)) /* KSI4 */ +#define NPCX_ALT_KSI5 ALT(2, 4, NPCX_ALT_INV(7, NO_KSI5_SL)) /* KSI5 */ +#define NPCX_ALT_KSI6 ALT(2, 3, NPCX_ALT_INV(7, NO_KSI6_SL)) /* KSI6 */ +#define NPCX_ALT_KSI7 ALT(2, 2, NPCX_ALT_INV(7, NO_KSI7_SL)) /* KSI7 */ + +/* Keyboard Scan Module (Outputs) */ +#define NPCX_ALT_KSO00 ALT(2, 1, NPCX_ALT_INV(8, NO_KSO00_SL)) /* KSO00 */ +#define NPCX_ALT_KSO01 ALT(2, 0, NPCX_ALT_INV(8, NO_KSO01_SL)) /* KSO01 */ +#define NPCX_ALT_KSO02 ALT(1, 7, NPCX_ALT_INV(8, NO_KSO02_SL)) /* KSO02 */ +#define NPCX_ALT_KSO03 ALT(1, 6, NPCX_ALT_INV(8, NO_KSO03_SL)) /* KSO03 */ +#define NPCX_ALT_KSO04 ALT(1, 5, NPCX_ALT_INV(8, NO_KSO04_SL)) /* KSO04 */ +#define NPCX_ALT_KSO05 ALT(1, 4, NPCX_ALT_INV(8, NO_KSO05_SL)) /* KSO05 */ +#define NPCX_ALT_KSO06 ALT(1, 3, NPCX_ALT_INV(8, NO_KSO06_SL)) /* KSO06 */ +#define NPCX_ALT_KSO07 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */ +#if NPCX_UART_MODULE2 +#define NPCX_ALT_KSO08 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL)) /* KSO08 */ +#define NPCX_ALT_KSO09 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL)) /* KSO09 */ +#else +#define NPCX_ALT_KSO08 /* Used by CR_SOUT */ +#define NPCX_ALT_KSO09 /* Used by CR_SIN */ +#endif +#define NPCX_ALT_KSO10 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */ +#define NPCX_ALT_KSO11 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */ +#define NPCX_ALT_KSO12 ALT(0, 5, NPCX_ALT_INV(9, NO_KSO12_SL)) /* KSO12 */ +#define NPCX_ALT_KSO13 ALT(0, 4, NPCX_ALT_INV(9, NO_KSO13_SL)) /* KSO13 */ +#define NPCX_ALT_KSO14 ALT(8, 2, NPCX_ALT_INV(9, NO_KSO14_SL)) /* KSO14 */ +#define NPCX_ALT_KSO15 ALT(8, 3, NPCX_ALT_INV(9, NO_KSO15_SL)) /* KSO15 */ +#define NPCX_ALT_KSO16 ALT(0, 3, NPCX_ALT_INV(A, NO_KSO16_SL)) /* KSO16 */ +#define NPCX_ALT_KSO17 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */ + +/* Clock module */ +#define NPCX_ALT_32KHZ_OUT ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ +#define NPCX_ALT_32KCLKIN ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */ + +#define NPCX_ALT_TABLE { \ + NPCX_ALT_I2C0SDA1 \ + NPCX_ALT_I2C0SCL1 \ + NPCX_ALT_I2C0SDA0 \ + NPCX_ALT_I2C0SCL0 \ + NPCX_ALT_I2C1SDA \ + NPCX_ALT_I2C1SCL \ + NPCX_ALT_I2C2SDA \ + NPCX_ALT_I2C2SCL \ + NPCX_ALT_I2C3SDA \ + NPCX_ALT_I2C3SCL \ + NPCX_ALT_ADC0 \ + NPCX_ALT_ADC1 \ + NPCX_ALT_ADC2 \ + NPCX_ALT_ADC3 \ + NPCX_ALT_ADC4 \ + NPCX_ALT_CR_SIN \ + NPCX_ALT_CR_SOUT \ + NPCX_ALT_SPIP_MISO \ + NPCX_ALT_SPIP_CS1 \ + NPCX_ALT_SPIP_MOSI \ + NPCX_ALT_SPIP_SCLK \ + NPCX_ALT_PWM0 \ + NPCX_ALT_PWM1 \ + NPCX_ALT_PWM2 \ + NPCX_ALT_PWM3 \ + NPCX_ALT_PWM4 \ + NPCX_ALT_PWM5 \ + NPCX_ALT_PWM6 \ + NPCX_ALT_PWM7 \ + NPCX_ALT_TA1_TACH1 \ + NPCX_ALT_TA2_TACH2 \ + NPCX_ALT_KSI0 \ + NPCX_ALT_KSI1 \ + NPCX_ALT_KSI2 \ + NPCX_ALT_KSI3 \ + NPCX_ALT_KSI4 \ + NPCX_ALT_KSI5 \ + NPCX_ALT_KSI6 \ + NPCX_ALT_KSI7 \ + NPCX_ALT_KSO00 \ + NPCX_ALT_KSO01 \ + NPCX_ALT_KSO02 \ + NPCX_ALT_KSO03 \ + NPCX_ALT_KSO04 \ + NPCX_ALT_KSO05 \ + NPCX_ALT_KSO06 \ + NPCX_ALT_KSO07 \ + NPCX_ALT_KSO08 \ + NPCX_ALT_KSO09 \ + NPCX_ALT_KSO10 \ + NPCX_ALT_KSO11 \ + NPCX_ALT_KSO12 \ + NPCX_ALT_KSO13 \ + NPCX_ALT_KSO14 \ + NPCX_ALT_KSO15 \ + NPCX_ALT_KSO16 \ + NPCX_ALT_KSO17 \ + NPCX_ALT_32KHZ_OUT \ + NPCX_ALT_32KCLKIN } + +/*****************************************************************************/ +/* Macro functions for Low-Voltage mapping table */ + +/* Low-Voltage GPIO Control 0 */ +#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) +#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) +#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) +#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) +#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) +#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) +#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) +#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) + +/* Low-Voltage GPIO Control 1 */ +#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) +#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) +#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) +#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) +#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) +#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) +#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO(6, 5) +#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE + +/* Low-Voltage GPIO Control 2 */ +#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) +#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) +#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) +#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) +#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) + +/* Low-Voltage GPIO Control 3 */ +#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) +#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) +#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) +#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) +#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) +#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) +#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) + +/* 4 Low-Voltage Control Groups on npcx5 */ +#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \ + { NPCX_LVOL_CTRL_ITEMS(1), }, \ + { NPCX_LVOL_CTRL_ITEMS(2), }, \ + { NPCX_LVOL_CTRL_ITEMS(3), }, } + +#endif /* __CROS_EC_GPIO_CHIP_NPCX5_H */ diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h new file mode 100644 index 0000000000..05bc3eb170 --- /dev/null +++ b/chip/npcx/gpio_chip-npcx7.h @@ -0,0 +1,487 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_GPIO_CHIP_NPCX7_H +#define __CROS_EC_GPIO_CHIP_NPCX7_H + +/*****************************************************************************/ +/* Macro functions for MIWU mapping table */ + +/* MIWU0 */ +/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */ +#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0) +#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1) +#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2) +#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3) +#ifndef NPCX_PSL_MODE_SUPPORT +#define NPCX_WUI_GPIO_8_4 WUI(0, MIWU_GROUP_1, 4) /* Used as VSBY in PSL */ +#define NPCX_WUI_GPIO_8_5 WUI(0, MIWU_GROUP_1, 5) /* Used as PSL_OUT in PSL */ +#endif +#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6) +#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7) + +/* Group B: NPCX_IRQ_TWD_WKINTB_0 */ +#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0) +#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1) +#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2) +#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3) +#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4) +#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5) + +/* Group C: NPCX_IRQ_WKINTC_0 */ +#define NPCX_WUI_GPIO_9_6 WUI(0, MIWU_GROUP_3, 0) +#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1) +#define NPCX_WUI_GPIO_A_0 WUI(0, MIWU_GROUP_3, 2) +#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3) +#define NPCX_WUI_GPIO_A_2 WUI(0, MIWU_GROUP_3, 4) +#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5) +#define NPCX_WUI_GPIO_A_4 WUI(0, MIWU_GROUP_3, 6) +#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7) + +/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */ +#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0) +#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1) +#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2) +#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5) +#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6) + +/* Group E: NPCX_IRQ_WKINTEFGH_0 */ +#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0) +#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1) +#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2) +#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4) + +/* Group F: NPCX_IRQ_WKINTEFGH_0 */ +#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0) +#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1) +#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2) +#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3) +#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4) +#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5) +#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6) +#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7) + +/* Group G: NPCX_IRQ_WKINTEFGH_0 */ +#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0) +#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1) +#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2) +#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3) +#define NPCX_WUI_GPIO_D_4 WUI(0, MIWU_GROUP_7, 4) +#define NPCX_WUI_GPIO_D_5 WUI(0, MIWU_GROUP_7, 5) +#define NPCX_WUI_GPIO_D_7 WUI(0, MIWU_GROUP_7, 6) +#define NPCX_WUI_GPIO_E_0 WUI(0, MIWU_GROUP_7, 7) + +/* Group H: NPCX_IRQ_WKINTEFGH_0 */ +#define NPCX_WUI_GPIO_E_1 WUI(0, MIWU_GROUP_8, 0) +#define NPCX_WUI_GPIO_E_2 WUI(0, MIWU_GROUP_8, 1) +#define NPCX_WUI_GPIO_E_3 WUI(0, MIWU_GROUP_8, 2) +#define NPCX_WUI_GPIO_E_4 WUI(0, MIWU_GROUP_8, 3) +#define NPCX_WUI_GPIO_E_5 WUI(0, MIWU_GROUP_8, 4) +#define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5) +#define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6) +#ifndef NPCX_EXT32K_OSC_SUPPORT +#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support */ +#endif + +/* MIWU1 */ +/* Group A: NPCX_IRQ_WKINTA_1 */ +#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0) +#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1) +#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2) +#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3) +#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4) +#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5) +#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6) +#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7) + +/* Group B: NPCX_IRQ_WKINTB_1 */ +#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0) +#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1) +#define NPCX_WUI_GPIO_F_4 WUI(1, MIWU_GROUP_2, 2) +#define NPCX_WUI_GPIO_1_3 WUI(1, MIWU_GROUP_2, 3) +#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4) +#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5) +#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6) +#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7) + +/* Group C: NPCX_IRQ_KSI_WKINTC_1 */ +#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0) +#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1) +#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2) +#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3) +#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4) +#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5) +#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6) +#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7) + +/* Group D: NPCX_IRQ_WKINTD_1 */ +#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0) +#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1) +#define NPCX_WUI_GPIO_F_5 WUI(1, MIWU_GROUP_4, 2) +#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3) +#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4) +#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6) +#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7) + +/* Group E: NPCX_IRQ_WKINTE_1 */ +#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0) +#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1) +#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2) +#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3) +#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4) +#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5) +#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6) +#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7) + +/* Group F: NPCX_IRQ_WKINTF_1 */ +#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0) +#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1) +#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2) +#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3) +#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4) +#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5) +#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6) +#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7) + +/* Group G: NPCX_IRQ_WKINTG_1 */ +#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0) +#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1) +#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2) +#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3) +#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4) +#define NPCX_WUI_GPIO_6_5 WUI(1, MIWU_GROUP_7, 5) +#ifndef NPCX_EXT32K_OSC_SUPPORT +#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if support*/ +#endif + +/* Group H: NPCX_IRQ_WKINTH_1 */ +#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0) +#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1) +#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2) +#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3) +#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4) +#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5) +#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6) + +/* MIWU2 */ +/* Group F: NPCX_IRQ_WKINTFG_2 */ +#define NPCX_WUI_GPIO_F_1 WUI(2, MIWU_GROUP_6, 1) +#define NPCX_WUI_GPIO_F_2 WUI(2, MIWU_GROUP_6, 2) +#define NPCX_WUI_GPIO_B_6 WUI(2, MIWU_GROUP_6, 6) + +/*****************************************************************************/ +/* Macro functions for Alternative mapping table */ + +/* I2C Module */ +#define NPCX_ALT_I2C0SDA0 ALT(B, 4, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SDA0 */ +#define NPCX_ALT_I2C0SCL0 ALT(B, 5, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SCL0 */ +#define NPCX_ALT_I2C1SDA0 ALT(8, 7, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SDA0 */ +#define NPCX_ALT_I2C1SCL0 ALT(9, 0, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SCL0 */ +#define NPCX_ALT_I2C2SDA0 ALT(9, 1, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SDA0 */ +#define NPCX_ALT_I2C2SCL0 ALT(9, 2, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SCL0 */ +#define NPCX_ALT_I2C3SDA0 ALT(D, 0, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SDA0 */ +#define NPCX_ALT_I2C3SCL0 ALT(D, 1, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SCL0 */ +#ifdef NPCX_PSL_MODE_SUPPORT +#define NPCX_ALT_I2C4SDA0 /* No I2CSDA since GPIO85 used as PSL_OUT */ +#define NPCX_ALT_I2C4SCL0 /* Used as PSL_OUT */ +#else +#define NPCX_ALT_I2C4SDA0 ALT(8, 6, NPCX_ALT(2, I2C4_0_SL)) /* SMB4SDA0 */ +#define NPCX_ALT_I2C4SCL0 ALT(8, 5, NPCX_ALT(2, I2C4_0_SL)) /* SMB4SCL0 */ +#endif +#define NPCX_ALT_I2C4SDA1 ALT(F, 2, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SDA1 */ +#define NPCX_ALT_I2C4SCL1 ALT(F, 3, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SCL1 */ +#define NPCX_ALT_I2C5SDA0 ALT(3, 6, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SDA0 */ +#define NPCX_ALT_I2C5SCL0 ALT(3, 3, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SCL0 */ +#define NPCX_ALT_I2C5SDA1 ALT(F, 4, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SDA1 */ +#define NPCX_ALT_I2C5SCL1 ALT(F, 5, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SCL1 */ +#define NPCX_ALT_I2C6SDA0 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */ +#if !(NPCX7_PWM1_SEL) +#define NPCX_ALT_I2C6SCL0 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */ +#else +#define NPCX_ALT_I2C6SCL0 /* Used as PWM1 */ +#endif +#define NPCX_ALT_I2C6SDA1 ALT(E, 3, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SDA1 */ +#define NPCX_ALT_I2C6SCL1 ALT(E, 4, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SCL1 */ +#define NPCX_ALT_I2C7SDA0 ALT(B, 2, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SDA0 */ +#define NPCX_ALT_I2C7SCL0 ALT(B, 3, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SCL0 */ + +/* ADC Module */ +#define NPCX_ALT_ADC0 ALT(4, 5, NPCX_ALT(6, ADC0_SL)) /* ADC0 */ +#define NPCX_ALT_ADC1 ALT(4, 4, NPCX_ALT(6, ADC1_SL)) /* ADC1 */ +#define NPCX_ALT_ADC2 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2 */ +#define NPCX_ALT_ADC3 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3 */ +#define NPCX_ALT_ADC4 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4 */ +#define NPCX_ALT_ADC5 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5 */ +#define NPCX_ALT_ADC6 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6 */ +#define NPCX_ALT_ADC7 ALT(E, 1, NPCX_ALT(F, ADC7_SL)) /* ADC7 */ +#define NPCX_ALT_ADC8 ALT(F, 1, NPCX_ALT(F, ADC8_SL)) /* ADC8 */ +#define NPCX_ALT_ADC9 ALT(F, 0, NPCX_ALT(F, ADC9_SL)) /* ADC9 */ + +/* UART Module 1/2 */ +#if NPCX_UART_MODULE2 +#define NPCX_ALT_CR_SIN ALT(6, 4, NPCX_ALT(C, UART_SL2)) /* CR_SIN2 */ +#define NPCX_ALT_CR_SOUT ALT(6, 5, NPCX_ALT(C, UART_SL2)) /* CR_SOUT2 */ +#else +#define NPCX_ALT_CR_SIN ALT(1, 0, NPCX_ALT_INV(9, NO_KSO08_SL)) /* CR_SIN */ +#define NPCX_ALT_CR_SOUT ALT(1, 1, NPCX_ALT_INV(9, NO_KSO09_SL)) /* CR_SOUT */ +#endif + +/* SPI Module */ +#define NPCX_ALT_SPIP_MISO ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */ +#define NPCX_ALT_SPIP_CS1 ALT(A, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_CS1 */ +#define NPCX_ALT_SPIP_MOSI ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */ +#define NPCX_ALT_SPIP_SCLK ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */ + +/* PWM Module */ +#define NPCX_ALT_PWM0 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */ +#if NPCX7_PWM1_SEL +#define NPCX_ALT_PWM1 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ +#else +#define NPCX_ALT_PWM1 /* Used as SMB6SCL0 */ +#endif +#define NPCX_ALT_PWM2 ALT(C, 4, NPCX_ALT(4, PWM2_SL)) /* PWM2 */ +#define NPCX_ALT_PWM3 ALT(8, 0, NPCX_ALT(4, PWM3_SL)) /* PWM3 */ +#define NPCX_ALT_PWM4 ALT(B, 6, NPCX_ALT(4, PWM4_SL)) /* PWM4 */ +#define NPCX_ALT_PWM5 ALT(B, 7, NPCX_ALT(4, PWM5_SL)) /* PWM5 */ +#define NPCX_ALT_PWM6 ALT(C, 0, NPCX_ALT(4, PWM6_SL)) /* PWM6 */ +#define NPCX_ALT_PWM7 ALT(6, 0, NPCX_ALT(4, PWM7_SL)) /* PWM7 */ + +/* MFT Module */ +#if NPCX_TACH_SEL2 +#define NPCX_ALT_TA1_TACH1 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */ +#define NPCX_ALT_TA2_TACH2 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */ +#else +#define NPCX_ALT_TA1_TACH1 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */ +#define NPCX_ALT_TA2_TACH2 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */ +#endif + +/* Keyboard Scan Module (Inputs) */ +#define NPCX_ALT_KSI0 ALT(3, 1, NPCX_ALT_INV(7, NO_KSI0_SL)) /* KSI0 */ +#define NPCX_ALT_KSI1 ALT(3, 0, NPCX_ALT_INV(7, NO_KSI1_SL)) /* KSI1 */ +#define NPCX_ALT_KSI2 ALT(2, 7, NPCX_ALT_INV(7, NO_KSI2_SL)) /* KSI2 */ +#define NPCX_ALT_KSI3 ALT(2, 6, NPCX_ALT_INV(7, NO_KSI3_SL)) /* KSI3 */ +#define NPCX_ALT_KSI4 ALT(2, 5, NPCX_ALT_INV(7, NO_KSI4_SL)) /* KSI4 */ +#define NPCX_ALT_KSI5 ALT(2, 4, NPCX_ALT_INV(7, NO_KSI5_SL)) /* KSI5 */ +#define NPCX_ALT_KSI6 ALT(2, 3, NPCX_ALT_INV(7, NO_KSI6_SL)) /* KSI6 */ +#define NPCX_ALT_KSI7 ALT(2, 2, NPCX_ALT_INV(7, NO_KSI7_SL)) /* KSI7 */ + +/* Keyboard Scan Module (Outputs) */ +#define NPCX_ALT_KSO00 ALT(2, 1, NPCX_ALT_INV(8, NO_KSO00_SL)) /* KSO00 */ +#define NPCX_ALT_KSO01 ALT(2, 0, NPCX_ALT_INV(8, NO_KSO01_SL)) /* KSO01 */ +#define NPCX_ALT_KSO02 ALT(1, 7, NPCX_ALT_INV(8, NO_KSO02_SL)) /* KSO02 */ +#define NPCX_ALT_KSO03 ALT(1, 6, NPCX_ALT_INV(8, NO_KSO03_SL)) /* KSO03 */ +#define NPCX_ALT_KSO04 ALT(1, 5, NPCX_ALT_INV(8, NO_KSO04_SL)) /* KSO04 */ +#define NPCX_ALT_KSO05 ALT(1, 4, NPCX_ALT_INV(8, NO_KSO05_SL)) /* KSO05 */ +#define NPCX_ALT_KSO06 ALT(1, 3, NPCX_ALT_INV(8, NO_KSO06_SL)) /* KSO06 */ +#define NPCX_ALT_KSO07 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */ +#if NPCX_UART_MODULE2 +#define NPCX_ALT_KSO08 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL)) /* KSO08 */ +#define NPCX_ALT_KSO09 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL)) /* KSO09 */ +#else +#define NPCX_ALT_KSO08 /* Used as CR_SOUT */ +#define NPCX_ALT_KSO09 /* Used as CR_SIN */ +#endif +#define NPCX_ALT_KSO10 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */ +#define NPCX_ALT_KSO11 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */ +#define NPCX_ALT_KSO12 ALT(0, 5, NPCX_ALT_INV(9, NO_KSO12_SL)) /* KSO12 */ +#define NPCX_ALT_KSO13 ALT(0, 4, NPCX_ALT_INV(9, NO_KSO13_SL)) /* KSO13 */ +#define NPCX_ALT_KSO14 ALT(8, 2, NPCX_ALT_INV(9, NO_KSO14_SL)) /* KSO14 */ +#define NPCX_ALT_KSO15 ALT(8, 3, NPCX_ALT_INV(9, NO_KSO15_SL)) /* KSO15 */ +#define NPCX_ALT_KSO16 ALT(0, 3, NPCX_ALT_INV(A, NO_KSO16_SL)) /* KSO16 */ +#define NPCX_ALT_KSO17 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */ + +/* Clock module */ +#define NPCX_ALT_32KHZ_OUT ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ +#ifdef NPCX_EXT32K_OSC_SUPPORT +#define NPCX_ALT_32KCLKIN /* Dedicated 32K clock input in NPCX7mnF/G series */ +#else +#define NPCX_ALT_32KCLKIN ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */ +#endif + +/* PSL module */ +#ifdef NPCX_PSL_MODE_SUPPORT +#define NPCX_ALT_PSL_IN1 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */ +#define NPCX_ALT_PSL_IN2 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */ +#define NPCX_ALT_PSL_IN3 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ +#define NPCX_ALT_PSL_IN4 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ +#else +#define NPCX_ALT_PSL_IN1 /* NO PSL in NPCX7mnG series */ +#define NPCX_ALT_PSL_IN2 /* NO PSL in NPCX7mnG series */ +#define NPCX_ALT_PSL_IN3 /* NO PSL in NPCX7mnG series */ +#define NPCX_ALT_PSL_IN4 /* NO PSL in NPCX7mnG series */ +#endif + +#define NPCX_ALT_TABLE { \ + NPCX_ALT_I2C0SDA0 \ + NPCX_ALT_I2C0SCL0 \ + NPCX_ALT_I2C1SDA0 \ + NPCX_ALT_I2C1SCL0 \ + NPCX_ALT_I2C2SDA0 \ + NPCX_ALT_I2C2SCL0 \ + NPCX_ALT_I2C3SDA0 \ + NPCX_ALT_I2C3SCL0 \ + NPCX_ALT_I2C4SDA0 \ + NPCX_ALT_I2C4SCL0 \ + NPCX_ALT_I2C4SDA1 \ + NPCX_ALT_I2C4SCL1 \ + NPCX_ALT_I2C5SDA0 \ + NPCX_ALT_I2C5SCL0 \ + NPCX_ALT_I2C5SDA1 \ + NPCX_ALT_I2C5SCL1 \ + NPCX_ALT_I2C6SDA0 \ + NPCX_ALT_I2C6SCL0 \ + NPCX_ALT_I2C6SDA1 \ + NPCX_ALT_I2C6SCL1 \ + NPCX_ALT_I2C7SDA0 \ + NPCX_ALT_I2C7SCL0 \ + NPCX_ALT_ADC0 \ + NPCX_ALT_ADC1 \ + NPCX_ALT_ADC2 \ + NPCX_ALT_ADC3 \ + NPCX_ALT_ADC4 \ + NPCX_ALT_ADC5 \ + NPCX_ALT_ADC6 \ + NPCX_ALT_ADC7 \ + NPCX_ALT_ADC8 \ + NPCX_ALT_ADC9 \ + NPCX_ALT_CR_SIN \ + NPCX_ALT_CR_SOUT \ + NPCX_ALT_SPIP_MISO \ + NPCX_ALT_SPIP_CS1 \ + NPCX_ALT_SPIP_MOSI \ + NPCX_ALT_SPIP_SCLK \ + NPCX_ALT_PWM0 \ + NPCX_ALT_PWM1 \ + NPCX_ALT_PWM2 \ + NPCX_ALT_PWM3 \ + NPCX_ALT_PWM4 \ + NPCX_ALT_PWM5 \ + NPCX_ALT_PWM6 \ + NPCX_ALT_PWM7 \ + NPCX_ALT_TA1_TACH1 \ + NPCX_ALT_TA2_TACH2 \ + NPCX_ALT_KSI0 \ + NPCX_ALT_KSI1 \ + NPCX_ALT_KSI2 \ + NPCX_ALT_KSI3 \ + NPCX_ALT_KSI4 \ + NPCX_ALT_KSI5 \ + NPCX_ALT_KSI6 \ + NPCX_ALT_KSI7 \ + NPCX_ALT_KSO00 \ + NPCX_ALT_KSO01 \ + NPCX_ALT_KSO02 \ + NPCX_ALT_KSO03 \ + NPCX_ALT_KSO04 \ + NPCX_ALT_KSO05 \ + NPCX_ALT_KSO06 \ + NPCX_ALT_KSO07 \ + NPCX_ALT_KSO08 \ + NPCX_ALT_KSO09 \ + NPCX_ALT_KSO10 \ + NPCX_ALT_KSO11 \ + NPCX_ALT_KSO12 \ + NPCX_ALT_KSO13 \ + NPCX_ALT_KSO14 \ + NPCX_ALT_KSO15 \ + NPCX_ALT_KSO16 \ + NPCX_ALT_KSO17 \ + NPCX_ALT_32KHZ_OUT \ + NPCX_ALT_32KCLKIN \ + NPCX_ALT_PSL_IN1 \ + NPCX_ALT_PSL_IN2 \ + NPCX_ALT_PSL_IN3 \ + NPCX_ALT_PSL_IN4 } + +/*****************************************************************************/ +/* Macro functions for Low-Voltage mapping table */ + +/* Low-Voltage GPIO Control 0 */ +#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) +#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) +#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) +#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) +#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) +#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) +#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) +#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) + +/* Low-Voltage GPIO Control 1 */ +#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) +#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) +#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) +#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) +#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) +#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) +#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO(6, 5) +#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE + +/* Low-Voltage GPIO Control 2 */ +#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) +#ifdef NPCX_PSL_MODE_SUPPORT +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ +#else +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) +#endif + +#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) +#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) +#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) +#ifdef NPCX_EXT32K_OSC_SUPPORT +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN */ +#else +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) +#endif +#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) + +/* Low-Voltage GPIO Control 3 */ +#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) +#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) +#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) +#ifdef NPCX_EXT32K_OSC_SUPPORT +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE /* Remove 1.8V support since CLKOUT*/ +#else +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) +#endif +#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) +#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) +#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) +#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) + +/* Low-Voltage GPIO Control 4 */ +#ifdef NPCX_PSL_MODE_SUPPORT +#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ +#else +#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) +#endif +#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) +#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) +#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) +#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5) +#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4) +#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4) +#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3) + +/* Low-Voltage GPIO Control 5 */ +#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2) +#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0) +#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE + +/* 6 Low-Voltage Control Groups on npcx7 */ +#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \ + { NPCX_LVOL_CTRL_ITEMS(1), }, \ + { NPCX_LVOL_CTRL_ITEMS(2), }, \ + { NPCX_LVOL_CTRL_ITEMS(3), }, \ + { NPCX_LVOL_CTRL_ITEMS(4), }, \ + { NPCX_LVOL_CTRL_ITEMS(5), }, } + +#endif /* __CROS_EC_GPIO_CHIP_NPCX7_H */ diff --git a/chip/npcx/gpio_chip.h b/chip/npcx/gpio_chip.h new file mode 100644 index 0000000000..1595f6b20d --- /dev/null +++ b/chip/npcx/gpio_chip.h @@ -0,0 +1,47 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_GPIO_CHIP_H +#define __CROS_EC_GPIO_CHIP_H + +/* Macros to initialize the MIWU mapping table. */ +#define NPCX_WUI_GPIO_PIN(port, index) NPCX_WUI_GPIO_##port##_##index +#define WUI(tbl, grp, idx) ((struct npcx_wui) { .table = tbl, .group = grp, \ + .bit = idx }) +#define WUI_INT(tbl, grp) WUI(tbl, grp, 0) + +/* Macros to initialize the alternative and low voltage mapping table. */ +#define NPCX_GPIO_NONE ((struct npcx_gpio) {.port = 0, .bit = 0, .valid = 0}) +#define NPCX_GPIO(grp, pin) ((struct npcx_gpio) {.port = GPIO_PORT_##grp, \ + .bit = pin, .valid = 1}) + +#define NPCX_ALT(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \ + .bit = NPCX_DEVALT##grp##_##pin, .inverted = 0 }) +#define NPCX_ALT_INV(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \ + .bit = NPCX_DEVALT##grp##_##pin, .inverted = 1 }) +#define ALT(port, index, alt) { NPCX_GPIO(port, index), alt }, + +#define NPCX_LVOL_CTRL_ITEMS(ctrl) { NPCX_LVOL_CTRL_##ctrl##_0, \ + NPCX_LVOL_CTRL_##ctrl##_1, \ + NPCX_LVOL_CTRL_##ctrl##_2, \ + NPCX_LVOL_CTRL_##ctrl##_3, \ + NPCX_LVOL_CTRL_##ctrl##_4, \ + NPCX_LVOL_CTRL_##ctrl##_5, \ + NPCX_LVOL_CTRL_##ctrl##_6, \ + NPCX_LVOL_CTRL_##ctrl##_7, } + +/* + * Include the MIWU, alternative and low-Voltage macro functions for GPIOs + * depends on Nuvoton chip series. + */ +#if defined(CHIP_FAMILY_NPCX5) +#include "gpio_chip-npcx5.h" +#elif defined(CHIP_FAMILY_NPCX7) +#include "gpio_chip-npcx7.h" +#else +#error "Unsupported chip family" +#endif + +#endif /* __CROS_EC_GPIO_CHIP_H */ diff --git a/chip/npcx/gpio_wui.h b/chip/npcx/gpio_wui.h deleted file mode 100644 index 92e6be08ef..0000000000 --- a/chip/npcx/gpio_wui.h +++ /dev/null @@ -1,151 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO interrupt/wake-up mapping */ - -#ifndef __CROS_EC_GPIO_WUI_H -#define __CROS_EC_GPIO_WUI_H - -#include "common.h" - -#define NPCX_WUI_GPIO_PIN(port, index) NPCX_WUI_GPIO_##port##_##index -#define WUI(tbl, grp, idx) ((struct npcx_wui) { .table = tbl, .group = grp, \ - .bit = idx }) -#define WUI_INT(tbl, grp) WUI(tbl, grp, 0) - -/* MIWU0 */ -/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */ -#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0) -#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1) -#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2) -#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3) -#define NPCX_WUI_GPIO_8_4 WUI(0, MIWU_GROUP_1, 4) -#define NPCX_WUI_GPIO_8_5 WUI(0, MIWU_GROUP_1, 5) -#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6) -#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7) - -/* Group B: NPCX_IRQ_TWD_WKINTB_0 */ -#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0) -#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1) -#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2) -#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3) -#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4) -#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5) - -/* Group C: NPCX_IRQ_WKINTC_0 */ -#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1) -#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3) -#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5) -#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7) - -/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */ -#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0) -#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1) -#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2) -#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5) -#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6) - -/* Group E: NPCX_IRQ_WKINTEFGH_0 */ -#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0) -#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1) -#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2) -#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4) - -/* Group F: NPCX_IRQ_WKINTEFGH_0 */ -#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0) -#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1) -#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2) -#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3) -#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4) -#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5) -#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6) -#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7) - -/* Group G: NPCX_IRQ_WKINTEFGH_0 */ -#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0) -#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1) -#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2) -#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3) - -/* Group H: NPCX_IRQ_WKINTEFGH_0 */ -#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) - -/* MIWU1 */ -/* Group A: NPCX_IRQ_WKINTA_1 */ -#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0) -#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1) -#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2) -#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3) -#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4) -#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5) -#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6) -#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7) - -/* Group B: NPCX_IRQ_WKINTB_1 */ -#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0) -#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1) -#define NPCX_WUI_GPIO_1_3 WUI(1, MIWU_GROUP_2, 3) -#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4) -#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5) -#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6) -#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7) - -/* Group C: NPCX_IRQ_KSI_WKINTC_1 */ -#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0) -#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1) -#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2) -#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3) -#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4) -#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5) -#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6) -#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7) - -/* Group D: NPCX_IRQ_WKINTD_1 */ -#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0) -#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1) -#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3) -#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4) -#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6) -#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7) - -/* Group E: NPCX_IRQ_WKINTE_1 */ -#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0) -#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1) -#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2) -#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3) -#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4) -#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5) -#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6) -#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7) - -/* Group F: NPCX_IRQ_WKINTF_1 */ -#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0) -#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1) -#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2) -#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3) -#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4) -#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5) -#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6) -#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7) - -/* Group G: NPCX_IRQ_WKINTG_1 */ -#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0) -#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1) -#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2) -#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3) -#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4) -#define NPCX_WUI_GPIO_6_5 WUI(1, MIWU_GROUP_7, 5) -#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) - -/* Group H: NPCX_IRQ_WKINTH_1 */ -#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0) -#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1) -#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2) -#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3) -#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4) -#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5) -#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6) - -#endif /* __CROS_EC_GPIO_WUI_H */ diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 2f263de0a0..c08bd5d614 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -51,6 +51,7 @@ #define SUPPORT_HIB 1 #define SUPPORT_P80_SEG 0 /* Note: it uses KSO10 & KSO11 */ /* Switcher of debugging */ +#define DEBUG_GPIO 0 #define DEBUG_I2C 0 #define DEBUG_TMR 0 #define DEBUG_WDG 0 @@ -227,7 +228,7 @@ #define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 #define NPCX_IRQ_SPI NPCX_IRQ_57 #define NPCX_IRQ58_NOUSED NPCX_IRQ_58 -#define NPCX_IRQ59_NOUSED NPCX_IRQ_59 +#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 #define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 #define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 #define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 @@ -302,7 +303,9 @@ #define NPCX_GLUE_SDPD1 REG8(NPCX_GLUE_REGS_BASE + 0x012) #define NPCX_GLUE_SDP_CTS REG8(NPCX_GLUE_REGS_BASE + 0x014) #define NPCX_GLUE_SMBSEL REG8(NPCX_GLUE_REGS_BASE + 0x021) - +#if defined(NPCX_PSL_MODE_SUPPORT) +#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) +#endif /******************************************************************************/ /* MIWU registers */ #define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + \ @@ -317,7 +320,7 @@ ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) #define NPCX_WKINEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1F + \ ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + n) +#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) #define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) #define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) @@ -366,6 +369,9 @@ enum { #define NPCX_PPUD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004) #define NPCX_PENVDD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005) #define NPCX_PTYPE(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006) +#if defined(CHIP_FAMILY_NPCX7) +#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) +#endif /* GPIO enumeration */ enum { @@ -443,11 +449,18 @@ enum { #define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001) #define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002) #define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006) -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + n) +#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) #define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021) #define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028) #define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029) -#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_SCFG_BASE_ADDR + 0x02A + n) +#if defined(CHIP_FAMILY_NPCX5) +#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) +#elif defined(CHIP_FAMILY_NPCX7) +#define NPCX_LV_GPIO_CTL_ADDR(n) (((n) < 5) ? \ + (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\ + (NPCX_SCFG_BASE_ADDR + 0x026)) +#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) +#endif #define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F) #define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037) @@ -492,6 +505,7 @@ enum { #define NPCX_RSTCTL_HIPRST_MODE 6 #define NPCX_DEV_CTL4_F_SPI_SLLK 2 #define NPCX_DEV_CTL4_SPI_SP_SEL 4 +#define NPCX_DEV_CTL4_WP_IF 5 #define NPCX_DEVPU0_I2C0_0_PUE 0 #define NPCX_DEVPU0_I2C0_1_PUE 1 #define NPCX_DEVPU0_I2C1_0_PUE 2 @@ -500,6 +514,7 @@ enum { #define NPCX_DEVPU1_F_SPI_PUD_EN 7 /* DEVALT */ +/* pin-mux for SPI/FIU */ #define NPCX_DEVALT0_SPIP_SL 0 #define NPCX_DEVALT0_GPIO_NO_SPIP 3 #define NPCX_DEVALT0_F_SPI_CS1_2 4 @@ -507,6 +522,7 @@ enum { #define NPCX_DEVALT0_F_SPI_QUAD 6 #define NPCX_DEVALT0_NO_F_SPI 7 +/* pin-mux for LPC/eSPI */ #define NPCX_DEVALT1_KBRST_SL 0 #define NPCX_DEVALT1_A20M_SL 1 #define NPCX_DEVALT1_SMI_SL 2 @@ -516,21 +532,45 @@ enum { #define NPCX_DEVALT1_CLKRN_SL 6 #define NPCX_DEVALT1_NO_LPC_ESPI 7 +/* pin-mux for I2C */ +#if defined(CHIP_FAMILY_NPCX5) #define NPCX_DEVALT2_I2C0_0_SL 0 #define NPCX_DEVALT2_I2C0_1_SL 1 #define NPCX_DEVALT2_I2C1_0_SL 2 #define NPCX_DEVALT2_I2C2_0_SL 4 #define NPCX_DEVALT2_I2C3_0_SL 6 +#elif defined(CHIP_FAMILY_NPCX7) +#define NPCX_DEVALT2_I2C0_0_SL 0 +#define NPCX_DEVALT2_I2C7_0_SL 1 +#define NPCX_DEVALT2_I2C1_0_SL 2 +#define NPCX_DEVALT2_I2C6_0_SL 3 +#define NPCX_DEVALT2_I2C2_0_SL 4 +#define NPCX_DEVALT2_I2C5_0_SL 5 +#define NPCX_DEVALT2_I2C3_0_SL 6 +#define NPCX_DEVALT2_I2C4_0_SL 7 +#define NPCX_DEVALT6_I2C6_1_SL 5 +#define NPCX_DEVALT6_I2C5_1_SL 6 +#define NPCX_DEVALT6_I2C4_1_SL 7 +#endif +/* pin-mux for PS2 */ #define NPCX_DEVALT3_PS2_0_SL 0 #define NPCX_DEVALT3_PS2_1_SL 1 #define NPCX_DEVALT3_PS2_2_SL 2 #define NPCX_DEVALT3_PS2_3_SL 3 +#define NPCX_DEVALTC_PS2_3_SL2 3 + +/* pin-mux for Tacho */ #define NPCX_DEVALT3_TA1_SL1 4 #define NPCX_DEVALT3_TB1_SL1 5 #define NPCX_DEVALT3_TA2_SL1 6 #define NPCX_DEVALT3_TB2_SL1 7 +#define NPCX_DEVALTC_TA1_SL2 4 +#define NPCX_DEVALTC_TB1_SL2 5 +#define NPCX_DEVALTC_TA2_SL2 6 +#define NPCX_DEVALTC_TB2_SL2 7 +/* pin-mux for PWM */ #define NPCX_DEVALT4_PWM0_SL 0 #define NPCX_DEVALT4_PWM1_SL 1 #define NPCX_DEVALT4_PWM2_SL 2 @@ -540,16 +580,26 @@ enum { #define NPCX_DEVALT4_PWM6_SL 6 #define NPCX_DEVALT4_PWM7_SL 7 +/* pin-mux for JTAG */ #define NPCX_DEVALT5_TRACE_EN 0 #define NPCX_DEVALT5_NJEN1_EN 1 #define NPCX_DEVALT5_NJEN0_EN 2 +/* pin-mux for ADC */ #define NPCX_DEVALT6_ADC0_SL 0 #define NPCX_DEVALT6_ADC1_SL 1 #define NPCX_DEVALT6_ADC2_SL 2 #define NPCX_DEVALT6_ADC3_SL 3 #define NPCX_DEVALT6_ADC4_SL 4 +#if defined(CHIP_FAMILY_NPCX7) +#define NPCX_DEVALTF_ADC5_SL 0 +#define NPCX_DEVALTF_ADC6_SL 1 +#define NPCX_DEVALTF_ADC7_SL 2 +#define NPCX_DEVALTF_ADC8_SL 3 +#define NPCX_DEVALTF_ADC9_SL 4 +#endif +/* pin-mux for Keyboard */ #define NPCX_DEVALT7_NO_KSI0_SL 0 #define NPCX_DEVALT7_NO_KSI1_SL 1 #define NPCX_DEVALT7_NO_KSI2_SL 2 @@ -558,7 +608,6 @@ enum { #define NPCX_DEVALT7_NO_KSI5_SL 5 #define NPCX_DEVALT7_NO_KSI6_SL 6 #define NPCX_DEVALT7_NO_KSI7_SL 7 - #define NPCX_DEVALT8_NO_KSO00_SL 0 #define NPCX_DEVALT8_NO_KSO01_SL 1 #define NPCX_DEVALT8_NO_KSO02_SL 2 @@ -567,7 +616,6 @@ enum { #define NPCX_DEVALT8_NO_KSO05_SL 5 #define NPCX_DEVALT8_NO_KSO06_SL 6 #define NPCX_DEVALT8_NO_KSO07_SL 7 - #define NPCX_DEVALT9_NO_KSO08_SL 0 #define NPCX_DEVALT9_NO_KSO09_SL 1 #define NPCX_DEVALT9_NO_KSO10_SL 2 @@ -576,25 +624,31 @@ enum { #define NPCX_DEVALT9_NO_KSO13_SL 5 #define NPCX_DEVALT9_NO_KSO14_SL 6 #define NPCX_DEVALT9_NO_KSO15_SL 7 - #define NPCX_DEVALTA_NO_KSO16_SL 0 #define NPCX_DEVALTA_NO_KSO17_SL 1 + +/* pin-mux for PSL */ +#if defined(NPCX_PSL_MODE_SUPPORT) +#define NPCX_DEVALTD_PSL_IN1_AHI 0 +#define NPCX_DEVALTD_NPSL_IN1_SL 1 +#define NPCX_DEVALTD_PSL_IN2_AHI 2 +#define NPCX_DEVALTD_NPSL_IN2_SL 3 +#define NPCX_DEVALTD_PSL_IN3_AHI 4 +#define NPCX_DEVALTD_PSL_IN3_SL 5 +#define NPCX_DEVALTD_PSL_IN4_AHI 6 +#define NPCX_DEVALTD_PSL_IN4_SL 7 +#endif + +/* pin-mux for Others */ #define NPCX_DEVALTA_32K_OUT_SL 2 +#if !defined(NPCX_EXT32K_OSC_SUPPORT) #define NPCX_DEVALTA_32KCLKIN_SL 3 +#endif #define NPCX_DEVALTA_NO_VCC1_RST 4 #define NPCX_DEVALTA_NO_PECI_EN 6 #define NPCX_DEVALTA_UART_SL1 7 - -#define NPCX_DEVALTB_RXD_SL 0 -#define NPCX_DEVALTB_TXD_SL 1 - #define NPCX_DEVALTC_UART_SL2 0 #define NPCX_DEVALTC_SHI_SL 1 -#define NPCX_DEVALTC_PS2_3_SL2 3 -#define NPCX_DEVALTC_TA1_SL2 4 -#define NPCX_DEVALTC_TB1_SL2 5 -#define NPCX_DEVALTC_TA2_SL2 6 -#define NPCX_DEVALTC_TB2_SL2 7 /* Others bit definitions */ #define NPCX_LFCGCALCNT_LPREG_CTL_EN 1 @@ -878,7 +932,6 @@ enum NPCX_PMC_PWDWN_CTL_T { #define NPCX_IHOFS1 REG16(NPCX_SHM_BASE_ADDR + 0x052) #define NPCX_SHM_VER REG8(NPCX_SHM_BASE_ADDR + 0x07F) - /* SHM register fields */ #define NPCX_SMC_STS_HRERR 0 #define NPCX_SMC_STS_HWERR 1 @@ -1336,7 +1389,7 @@ enum ITIM16_MODULE_T { #define NPCX_VWEVSM_VALID FIELD(4, 4) #define NPCX_VWEVMS_VALID FIELD(4, 4) -/* Marco functions for eSPI CFG & IE */ +/* Macro functions for eSPI CFG & IE */ #define IS_SLAVE_CHAN_ENABLE(ch) IS_BIT_SET(NPCX_ESPICFG, ch) #define IS_HOST_CHAN_EN(ch) IS_BIT_SET(NPCX_ESPICFG, (ch+4)) #define ENABLE_ESPI_CHAN(ch) SET_BIT(NPCX_ESPICFG, ch) @@ -1373,7 +1426,7 @@ enum ITIM16_MODULE_T { #define ESPIIE_GENERIC (ESPIIE_IBRST | ESPIIE_CFGUPD | \ ESPIIE_BERR | ESPIIE_ESPIRST) -/* Marco functions for eSPI VW */ +/* Macro functions for eSPI VW */ #define ESPI_VWEVMS_NUM 12 #define ESPI_VWEVSM_NUM 10 #define ESPI_VWGPMS_NUM 16 diff --git a/include/gpio.h b/include/gpio.h index 919c7c8c80..8e6fd19444 100644 --- a/include/gpio.h +++ b/include/gpio.h @@ -31,6 +31,7 @@ #define GPIO_INT_SHARED (1 << 15) /* Shared among multiple pins */ #define GPIO_SEL_1P8V (1 << 16) /* Support 1.8v */ #define GPIO_ALTERNATE (1 << 17) /* GPIO used for alternate function. */ +#define GPIO_LOCKED (1 << 18) /* Lock GPIO output and configuration */ /* Common flag combinations */ #define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW)