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https://github.com/Telecominfraproject/OpenCellular.git
synced 2026-01-11 18:35:28 +00:00
Move flash persistent state to flash_common
Persistent state is needed by all platforms to hold the protect-ro-at-boot flag. STM32F100 and LM4 implementations were near-identical, and are now common code (with one #ifdef to handle the single place where they weren't). STM32L doesn't use pstate yet, but it'll need to. I can't simply store the protect-ro-at-boot flag inside the WRP registers themselves because they're still writable in EC-RW. The change to STM32L to use pstate is coming next. BUG=chrome-os-partner:15613 BRANCH=none TEST=build pit, link, spring; on link and spring, do - flashinfo -> (no flags) - enable WP (via screw or dut-control) - flashinfo -> wp_gpio_asserted - flashwp enable - flashinfo -> wp_gpio_asserted ro_at_boot - flashwp now - flashinfo -> wp_gpio_asserted ro_at_boot all_now (and possibly ro_now) - flashwp disable -> fails - flashinfo -> wp_gpio_asserted ro_at_boot all_now - reboot ap-off - flashinfo -> wp_gpio_asserted ro_at_boot ro_now - disable WP (via screw or dut-control) - reboot - flashinfo -> ro_at_boot - flashwp disable - flashinfo -> (no flags) (Note that on Spring you'll need to 'forceen on' before enabling WP, or the console will be disabled once you enable ro_at_boot and reboot.) Change-Id: I415388b98ec8bf1d149803aaaa7fe8c7f3076c36 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56064
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ChromeBot
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@@ -11,6 +11,23 @@
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#include "common.h"
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#include "ec_commands.h" /* For EC_FLASH_PROTECT_* flags */
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/* Number of physical flash banks */
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#define PHYSICAL_BANKS (CONFIG_FLASH_PHYSICAL_SIZE / CONFIG_FLASH_BANK_SIZE)
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/* Read-only firmware offset and size in units of flash banks */
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#define RO_BANK_OFFSET (CONFIG_SECTION_RO_OFF / CONFIG_FLASH_BANK_SIZE)
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#define RO_BANK_COUNT (CONFIG_SECTION_RO_SIZE / CONFIG_FLASH_BANK_SIZE)
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/* Read-write firmware offset and size in units of flash banks */
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#define RW_BANK_OFFSET (CONFIG_SECTION_RW_OFF / CONFIG_FLASH_BANK_SIZE)
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#define RW_BANK_COUNT (CONFIG_SECTION_RW_SIZE / CONFIG_FLASH_BANK_SIZE)
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/* Persistent protection state flash offset / size / bank */
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#define PSTATE_OFFSET CONFIG_SECTION_FLASH_PSTATE_OFF
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#define PSTATE_SIZE CONFIG_SECTION_FLASH_PSTATE_SIZE
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#define PSTATE_BANK (PSTATE_OFFSET / CONFIG_FLASH_BANK_SIZE)
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#define PSTATE_BANK_COUNT (PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE)
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/*****************************************************************************/
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/* Low-level methods, for use by flash_common. */
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@@ -70,6 +87,17 @@ int flash_physical_erase(int offset, int size);
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*/
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int flash_physical_get_protect(int bank);
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/**
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* Set physical write protect status for the next boot.
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*
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* @param start_bank Start bank
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* @param bank_count Number of banks to protect
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* @param enable Enable (non-zero) or disable (zero) protection
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* @return non-zero if error.
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*/
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int flash_physical_set_protect_at_boot(int start_bank, int bank_count,
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int enable);
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/**
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* Force reload of flash protection bits.
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*
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@@ -81,6 +109,27 @@ int flash_physical_get_protect(int bank);
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*/
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int flash_physical_force_reload(void);
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/*****************************************************************************/
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/* Low-level persistent state code for use by flash modules. */
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/**
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* Return non-zero if RO flash should be protected at boot.
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*/
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int flash_get_protect_ro_at_boot(void);
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/**
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* Enable write protect for the read-only code.
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*
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* Once write protect is enabled, it will STAY enabled until the system is
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* hard-rebooted with the hardware write protect pin deasserted. If the write
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* protect pin is deasserted, the protect setting is ignored, and the entire
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* flash will be writable.
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*
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* @param enable Enable write protection
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* @return EC_SUCCESS, or nonzero if error.
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*/
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int flash_protect_ro_at_boot(int enable);
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/*****************************************************************************/
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/* High-level interface for use by other modules. */
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