UT for SDR subsytem

firmware/ec/common/inc/global/Framework.h

@@ -24,7 +24,11 @@
  * OC_CONNECT1.C. This helps host compilation as it doesn't need to know symbol definition for the configs
  * and schema sharing can be achived with limited common files.
  */
+#ifdef UT_FRAMEWORK
+#define SCHEMA_IMPORT extern
+#else
 #define SCHEMA_IMPORT extern __attribute__((weak))
+#endif
 
 /* DriverStruct acts as a generic datatype.
  * In schema we are more intreseted in the address of structure so we use this datatype DriverStruct

firmware/ec/src/subsystem/sdr/sdr.c

@@ -63,6 +63,9 @@ void sdr_pwr_control(Sdr_gpioCfg *sdr_gpioCfg, uint8_t control)
  *****************************************************************************/
 static void sdr_control_ioexpander(Sdr_gpioCfg *sdr_gpioCfg, uint8_t control)
 {
+    if (!sdr_gpioCfg) {
+        return;
+    }
     if (control == OC_SDR_ENABLE) {
         OcGpio_write(&sdr_gpioCfg->pin_rf_fe_io_reset, true);
     } else {
@@ -82,6 +85,9 @@ static void sdr_control_ioexpander(Sdr_gpioCfg *sdr_gpioCfg, uint8_t control)
  *****************************************************************************/
 static void sdr_control_device(Sdr_gpioCfg *sdr_gpioCfg, uint8_t control)
 {
+    if (!sdr_gpioCfg) {
+        return;
+    }
     if (control == OC_SDR_ENABLE) {
         OcGpio_write(&sdr_gpioCfg->pin_sdr_reset_in, true);
     } else {
@@ -101,6 +107,9 @@ static void sdr_control_device(Sdr_gpioCfg *sdr_gpioCfg, uint8_t control)
  *****************************************************************************/
 static void sdr_control_reset(Sdr_gpioCfg *sdr_gpioCfg, uint8_t control)
 {
+    if (!sdr_gpioCfg) {
+        return;
+    }
     if (control == OC_SDR_ENABLE) {
         OcGpio_write(&sdr_gpioCfg->pin_ec_trxfe_reset, true);
     } else {
@@ -121,6 +130,9 @@ static void sdr_control_reset(Sdr_gpioCfg *sdr_gpioCfg, uint8_t control)
  *****************************************************************************/
 static ReturnStatus sdr_fx3_reset(Sdr_gpioCfg* fx3_cfg)
 {
+    if (!fx3_cfg) {
+        return RETURN_NOTOK;
+    }
     /*TODO: We need to figure out a way for configuring PCA pins on Intel reset.*/
     OcGpio_configure(&fx3_cfg->pin_fx3_reset, OCGPIO_CFG_OUTPUT);
 
@@ -153,6 +165,9 @@ bool SDR_fx3Reset(void *driver, void *params) {
  *****************************************************************************/
 bool SDR_Init(void* driver, void *return_buf)
 {
+    if (!driver) {
+        return false;
+    }
     Sdr_gpioCfg *sdr_gpioCfg = (Sdr_gpioCfg*)driver;
     /* Initialize IO pins */
     OcGpio_configure(&sdr_gpioCfg->pin_sdr_reg_ldo_pgood, OCGPIO_CFG_INPUT);
@@ -202,6 +217,9 @@ bool SDR_Init(void* driver, void *return_buf)
 
 bool SDR_reset(void *driver, void *params) {
     Sdr_gpioCfg *sdr_gpioCfg = (Sdr_gpioCfg*)driver;
+    if (!sdr_gpioCfg) {
+        return;
+    }
     if (OcGpio_write(&sdr_gpioCfg->pin_sdr_reset_in, false) <= OCGPIO_FAILURE) {
         return false;
     }

firmware/ec/test/Makefile

@@ -146,6 +146,10 @@ TEST_OCGPIO_SRC=$(OCWARE_ROOT)/src/drivers/OcGpio.c $(OCWARE_ROOT)/src/devices/i
 $(PATHB)Test_OcGpio$(TARGET_EXTENSION): $(STD_FILES) $(TEST_OCGPIO_SRC)
 	$(C_COMPILER) $(CFLAGS) $(INC_DIRS) $(SYMBOLS) $^ -o $@    
 
+TEST_SUBSYS_SDR_SRC=$(OCWARE_ROOT)/src/subsystem/sdr/sdr.c $(OCWARE_ROOT)/src/drivers/OcGpio.c fake/fake_GPIO.c fake/fake_ThreadedISR.c $(OCWARE_ROOT)/src/helpers/memory.c stub/stub_GateMutex.c $(OCWARE_ROOT)/src/drivers/GpioPCA9557.c $(OCWARE_ROOT)/src/Devices/pca9557.c fake/fake_I2C.c $(OCWARE_ROOT)/src/devices/i2cbus.c
+$(PATHB)Test_subsys_sdr$(TARGET_EXTENSION): $(STD_FILES) $(TEST_SUBSYS_SDR_SRC)
+	$(C_COMPILER) $(CFLAGS) $(INC_DIRS) $(SYMBOLS) $^ -o $@    
+
 # Dummy target to allow us to force rebuild of testresults every time
 FORCE:
 

firmware/ec/test/stub/stub_Clock.c

@@ -0,0 +1,18 @@
+/**
+ * Copyright (c) 2017-present, Facebook, Inc.
+ * All rights reserved.
+ *
+ * This source code is licensed under the BSD-style license found in the
+ * LICENSE file in the root directory of this source tree. An additional grant
+ * of patent rights can be found in the PATENTS file in the same directory.
+ */
+
+#include <ti/sysbios/knl/clock.h>
+#include "unity.h"
+
+xdc_Void ti_sysbios_knl_Clock_stop__E( ti_sysbios_knl_Clock_Handle __inst )
+{
+    TEST_ASSERT(__inst);
+    return;
+}
+

firmware/ec/test/stub/stub_Semaphore.c

@@ -0,0 +1,28 @@
+/**
+ * Copyright (c) 2017-present, Facebook, Inc.
+ * All rights reserved.
+ *
+ * This source code is licensed under the BSD-style license found in the
+ * LICENSE file in the root directory of this source tree. An additional grant
+ * of patent rights can be found in the PATENTS file in the same directory.
+ */
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include "unity.h"
+
+xdc_Void ti_sysbios_knl_Semaphore_post__E( ti_sysbios_knl_Semaphore_Handle __inst )
+{
+    return;
+}
+
+ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_create( xdc_Int count,
+                                const ti_sysbios_knl_Semaphore_Params *__prms,
+                                xdc_runtime_Error_Block *__eb )
+{
+    return(ti_sysbios_knl_Semaphore_Handle)1;
+}
+
+xdc_Bool ti_sysbios_knl_Semaphore_pend__E( ti_sysbios_knl_Semaphore_Handle __inst, xdc_UInt32 timeout )
+{
+    return(1);
+}

firmware/ec/test/stub/stub_Task.c

@@ -0,0 +1,41 @@
+/**
+ * Copyright (c) 2017-present, Facebook, Inc.
+ * All rights reserved.
+ *
+ * This source code is licensed under the BSD-style license found in the
+ * LICENSE file in the root directory of this source tree. An additional grant
+ * of patent rights can be found in the PATENTS file in the same directory.
+ */
+
+#include <ti/sysbios/knl/Task.h>
+#include <stdbool.h>
+#include "unity.h"
+uint8_t taskCreated = false;
+uint8_t taskInit = false;
+
+void ti_sysbios_knl_Task_construct( ti_sysbios_knl_Task_Struct *__obj, ti_sysbios_knl_Task_FuncPtr fxn,
+                        const ti_sysbios_knl_Task_Params *__prms, xdc_runtime_Error_Block *__eb )
+{
+    TEST_ASSERT(__obj);
+    TEST_ASSERT(fxn);
+    TEST_ASSERT(__prms);
+    TEST_ASSERT_TRUE((__prms->stackSize > 0));
+    TEST_ASSERT_TRUE((__prms->priority > 0));
+    TEST_ASSERT_TRUE((__prms->stack));
+    TEST_ASSERT_TRUE(taskInit);
+
+    /* check for this in the test suite to indicate task is created */
+    taskCreated = true;
+
+    /* Reset */
+    taskInit = false;
+    return;
+}
+
+xdc_Void ti_sysbios_knl_Task_Params__init__S( xdc_Ptr dst, const xdc_Void *src, xdc_SizeT psz, xdc_SizeT isz )
+{
+    TEST_ASSERT(dst);
+    /* Init is done now task can be created */
+    taskInit = true;
+    return;
+}

firmware/ec/test/suites/Test_subsys_sdr.c

@@ -0,0 +1,160 @@
+#include "common/inc/global/OC_CONNECT1.h"
+#include "drivers/GpioPCA9557.h"
+#include "fake/fake_I2C.h"
+#include "fake/fake_GPIO.h"
+#include "inc/subsystem/sdr/sdr.h"
+#include <string.h>
+#include "unity.h"
+/* ======================== Constants & variables =========================== */
+#define SDR_FX3_IOEXP_ADDRESS                       0x1E
+#define OC_CONNECT1_I2C3                            0x05
+
+static OcGpio_Port s_fake_io_port = {
+    .fn_table = &FakeGpio_fnTable,
+    .object_data = &(FakeGpio_Obj){},
+};
+
+OcGpio_Port sdr_fx3_io = {
+    .fn_table = &GpioPCA9557_fnTable,
+    .cfg = &(PCA9557_Cfg) {
+        .i2c_dev = { OC_CONNECT1_I2C3, SDR_FX3_IOEXP_ADDRESS },
+    },
+    .object_data = &(PCA9557_Obj){},
+};
+
+static uint8_t PCA9557_regs[] = {
+    [0x00] = 0x00, /* Input values */
+    [0x01] = 0x00, /* Output values */
+    [0x02] = 0x00, /* Polarity */
+    [0x03] = 0x00, /* Dir Config */
+};
+
+Sdr_gpioCfg sdr_gpioCfg = (Sdr_gpioCfg) {
+    /* EC_TRXFECONN_GPIO2/SDR_REG_LDO_PGOOD */
+    .pin_sdr_reg_ldo_pgood  = { &s_fake_io_port, OC_EC_SDR_PWR_GD },
+    /* TRXFE_12V_ONOFF */
+    .pin_trxfe_12v_onoff    = { &s_fake_io_port, OC_EC_SDR_PWR_CNTRL },
+    /* EC_FE_RESET_OUT/RF_FE_IO_RESET */
+    .pin_rf_fe_io_reset     = { &s_fake_io_port, OC_EC_SDR_FE_IO_RESET_CTRL },
+    /* EC_TRXFECONN_GPIO1/SDR_RESET_IN */
+    .pin_sdr_reset_in       = { &s_fake_io_port, OC_EC_SDR_DEVICE_CONTROL },
+    /* EC_TRXFE_RESET */
+    .pin_ec_trxfe_reset     = { &s_fake_io_port, OC_EC_RFFE_RESET },
+    /* FX3_RESET */
+    .pin_fx3_reset       = { &sdr_fx3_io, 0 },
+};
+
+static bool sdr_GpioPins[] = {
+    [1] = 0x1, /* Pin = 1 */
+    [OC_EC_GPIOCOUNT] = 0x1,
+};
+
+static uint32_t sdr_GpioConfig[] = {
+    [1] = OCGPIO_CFG_INPUT,
+    [OC_EC_GPIOCOUNT] = OCGPIO_CFG_INPUT,
+};
+
+extern int apState;
+
+/* ============================= Boilerplate ================================ */
+#include <ti/sysbios/knl/Task.h>
+unsigned int s_task_sleep_ticks;
+xdc_Void ti_sysbios_knl_Task_sleep__E( xdc_UInt32 nticks )
+{
+    s_task_sleep_ticks += nticks;
+}
+void SysCtlDelay(uint32_t ui32Count)
+{
+
+}
+
+void suite_setUp(void)
+{
+    FakeGpio_registerDevSimple(sdr_GpioPins, sdr_GpioConfig);
+    fake_I2C_init();
+    fake_I2C_registerDevSimple(OC_CONNECT1_I2C3, SDR_FX3_IOEXP_ADDRESS,
+                               PCA9557_regs, sizeof(PCA9557_regs),
+                               sizeof(PCA9557_regs[0]), sizeof(uint8_t),
+                               FAKE_I2C_DEV_LITTLE_ENDIAN);
+}
+
+void setUp(void)
+{
+}
+
+void tearDown(void)
+{
+}
+
+void suite_tearDown(void)
+{
+}
+
+/* ================================ Tests =================================== */
+void test_sdr_pwr_control(void)
+{
+    /* Enable */
+    sdr_GpioConfig[OC_EC_SDR_PWR_CNTRL] = 0;
+    sdr_pwr_control(&sdr_gpioCfg, OC_SDR_ENABLE);
+    TEST_ASSERT_EQUAL(sdr_GpioConfig[OC_EC_SDR_PWR_CNTRL], OCGPIO_CFG_OUTPUT |
+                                    OCGPIO_CFG_OUT_HIGH);
+    /* Disable */
+    sdr_pwr_control(&sdr_gpioCfg, OC_SDR_DISABLE);
+    TEST_ASSERT_EQUAL(sdr_GpioConfig[OC_EC_SDR_PWR_CNTRL], OCGPIO_CFG_OUTPUT |
+                                    OCGPIO_CFG_OUT_LOW);
+    
+    /* Invalid */
+    sdr_GpioConfig[OC_EC_SDR_PWR_CNTRL] = 0;
+    sdr_pwr_control(&sdr_gpioCfg, 2);
+    TEST_ASSERT_EQUAL(sdr_GpioConfig[OC_EC_SDR_PWR_CNTRL], 0);
+
+    sdr_pwr_control(NULL, OC_SDR_ENABLE);
+}
+
+void test_SDR_Init(void)
+{
+    sdr_GpioConfig[OC_EC_SDR_PWR_GD] = 0;
+    sdr_GpioConfig[OC_EC_SDR_FE_IO_RESET_CTRL] = 0;
+    sdr_GpioConfig[OC_EC_SDR_DEVICE_CONTROL] = 0;
+    sdr_GpioConfig[OC_EC_RFFE_RESET] = 0;
+    sdr_GpioConfig[OC_EC_SDR_PWR_CNTRL] = 0;
+    sdr_GpioPins[OC_EC_SDR_FE_IO_RESET_CTRL] = 0;
+    sdr_GpioPins[OC_EC_SDR_DEVICE_CONTROL] = 0;
+    sdr_GpioPins[OC_EC_RFFE_RESET] = 0;
+    sdr_GpioConfig[0] = 0;
+
+    TEST_ASSERT_TRUE(SDR_Init(&sdr_gpioCfg, NULL));
+    TEST_ASSERT_EQUAL(sdr_GpioConfig[OC_EC_SDR_PWR_GD], OCGPIO_CFG_INPUT);
+    TEST_ASSERT_EQUAL(sdr_GpioConfig[OC_EC_SDR_FE_IO_RESET_CTRL], OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW);
+    TEST_ASSERT_EQUAL(sdr_GpioConfig[OC_EC_SDR_DEVICE_CONTROL], OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW);
+    TEST_ASSERT_EQUAL(sdr_GpioConfig[OC_EC_RFFE_RESET], OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW);
+    TEST_ASSERT_EQUAL(sdr_GpioConfig[OC_EC_SDR_PWR_CNTRL], OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH);
+    TEST_ASSERT_TRUE(sdr_GpioPins[OC_EC_SDR_FE_IO_RESET_CTRL]);
+    TEST_ASSERT_TRUE(sdr_GpioPins[OC_EC_SDR_DEVICE_CONTROL]);
+    TEST_ASSERT_TRUE(sdr_GpioPins[OC_EC_RFFE_RESET]);
+    TEST_ASSERT_EQUAL(PCA9557_regs[0x01], 1);
+
+    /* Invalid */
+    TEST_ASSERT_FALSE(SDR_Init(NULL, NULL));
+}
+
+void test_SDR_reset(void)
+{
+    /*Reset*/
+    sdr_GpioPins[OC_EC_SDR_DEVICE_CONTROL] = 0;
+    TEST_ASSERT_TRUE(SDR_reset(&sdr_gpioCfg, NULL));
+    TEST_ASSERT_TRUE(sdr_GpioPins[OC_EC_SDR_DEVICE_CONTROL]);
+    
+    /* Invalid */
+    TEST_ASSERT_FALSE(SDR_reset(NULL, NULL));
+}
+
+void test_SDR_fx3Reset(void)
+{
+    /* Reset */
+    TEST_ASSERT_TRUE(SDR_fx3Reset(&sdr_gpioCfg, NULL));
+    TEST_ASSERT_EQUAL(PCA9557_regs[0x01], 1);
+
+    /* Invalid */
+    TEST_ASSERT_FALSE(SDR_fx3Reset(NULL, NULL));
+}