From c391492dcaadb327c86592e46c89ffdf33d0965d Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Mon, 9 Nov 2015 15:27:52 -0800 Subject: [PATCH] glados: Add pullup to SPI MISO GPIO When SPI CS is deasserted, SPI MISO is floating, which leads to leakage. BUG=chrome-os-partner:42104 BRANCH=None TEST=Manual on glados. Verify S5 power drops by ~1.5mW and sysjump / EC RW hashing continues to function. Signed-off-by: Shawn Nematbakhsh Change-Id: I0ba8fcab1618f396adc32984da93e37c5ff770a4 Reviewed-on: https://chromium-review.googlesource.com/311821 Commit-Ready: Shawn N Tested-by: Shawn N Reviewed-by: Alec Berg --- board/glados/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/glados/gpio.inc b/board/glados/gpio.inc index d507fcb505..6427284afa 100644 --- a/board/glados/gpio.inc +++ b/board/glados/gpio.inc @@ -148,7 +148,7 @@ ALTERNATE(PIN_MASK(12, 0x01), 1, MODULE_LPC, 0) /* MOSI - GPIO054 */ ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0) /* MISO - GPIO164 */ -ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0) +ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, GPIO_PULL_UP) /* PVT_SCLK - GPIO153 */ ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0) /* SHD_CS0# - GPIO150. Shared SPI chip select */