From d54cdec85b61f27f13bb6c089b5bd3fd05f014f2 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Wed, 7 Feb 2018 19:37:52 -0800 Subject: [PATCH] Fizz: Execute PMIC reset before vboot_main When AP requests cold reboot, currently EC does not perform PMIC reset because chipset_handle_reboot is executed only after EC jumps to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME events because power rails do not cycle. This patch will make EC execute PMIC reset to before vboot_main. BUG=b:73093795 BRANCH=none TEST=reboot, reboot ap-off, verify USB ports are powered after transitionining to dev mode. Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0 Signed-off-by: Daisuke Nojiri Reviewed-on: https://chromium-review.googlesource.com/908094 Reviewed-by: Vincent Palatin --- common/main.c | 6 ++++++ include/chipset.h | 5 +++++ power/skylake.c | 4 +++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/common/main.c b/common/main.c index 90d4a640c3..58f01812ef 100644 --- a/common/main.c +++ b/common/main.c @@ -7,6 +7,7 @@ #include "board_config.h" #include "button.h" +#include "chipset.h" #include "clock.h" #include "common.h" #include "console.h" @@ -170,6 +171,11 @@ test_mockable __keep int main(void) #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON | CONFIG_VOLUME_BUTTONS) */ #if defined(CONFIG_VBOOT_EFS) + /* + * Execute PMIC reset in case we're here after watchdog reset to unwedge + * AP. This has to be done here because vboot_main may jump to RW. + */ + chipset_handle_reboot(); /* * For RO, it behaves as follows: * In recovery, it enables PD communication and returns. diff --git a/include/chipset.h b/include/chipset.h index 5ada8c5c4b..c48eb733b8 100644 --- a/include/chipset.h +++ b/include/chipset.h @@ -104,6 +104,7 @@ static inline void chipset_force_shutdown(void) { } static inline void chipset_reset(int cold_reset) { } static inline void power_interrupt(enum gpio_signal signal) { } static inline void chipset_handle_espi_reset_assert(void) { } +static inline void chipset_handle_reboot(void) { } #endif /* !HAS_TASK_CHIPSET */ @@ -114,4 +115,8 @@ static inline void chipset_handle_espi_reset_assert(void) { } */ int chipset_pltrst_is_valid(void) __attribute__((weak)); +/** + * Execute chipset-specific reboot. + */ +void chipset_handle_reboot(void); #endif /* __CROS_EC_CHIPSET_H */ diff --git a/power/skylake.c b/power/skylake.c index 9cad5baaf4..61c07fb70e 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -124,7 +124,7 @@ __attribute__((weak)) int board_has_working_reset_flags(void) } #ifdef CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET -static void chipset_handle_reboot(void) +void chipset_handle_reboot(void) { int flags; @@ -167,5 +167,7 @@ static void chipset_handle_reboot(void) while (1) ; /* wait here */ } +#ifndef CONFIG_VBOOT_EFS DECLARE_HOOK(HOOK_INIT, chipset_handle_reboot, HOOK_PRIO_FIRST); #endif +#endif /* CONFIG_CHIPSET_HAS_PLATFORM_RESET */