From d5e598646d5b35a13fb12ec8908b995a83da372a Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Tue, 9 Feb 2016 14:58:18 -0800 Subject: [PATCH] cr50: configure GPIOs properly The SPS GPIOs are hard wired, so there is no need to configure the mux, but the default mode of pin operation is "output". The three SPS input pins (CLK, CS, and MOSI) need to be explicitly configured as such. BRANCH=none BUG=chrome-os-partner:50141 TEST=spiraw and TPM tests now pass Change-Id: Ie8f6c6c3cd09420aab831113a1456227d2b3c44b Signed-off-by: Vadim Bendebury Reviewed-on: https://chromium-review.googlesource.com/327064 Reviewed-by: Bill Richardson --- board/cr50/board.c | 8 ++++++++ board/cr50/gpio.inc | 10 ---------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/board/cr50/board.c b/board/cr50/board.c index 1decdbd850..492989b4f1 100644 --- a/board/cr50/board.c +++ b/board/cr50/board.c @@ -136,6 +136,14 @@ static void board_init(void) init_interrupts(); init_trng(); init_runlevel(PERMISSION_MEDIUM); + + /* + * SPS is hardwired, all we need to do is enable input mode on the + * appropriate pins. + */ + GWRITE_FIELD(PINMUX, DIOA2_CTL, IE, 1); /* MOSI */ + GWRITE_FIELD(PINMUX, DIOA6_CTL, IE, 1); /* CLK */ + GWRITE_FIELD(PINMUX, DIOA12_CTL, IE, 1); /* CS */ } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc index 3439393f68..740370de91 100644 --- a/board/cr50/gpio.inc +++ b/board/cr50/gpio.inc @@ -58,16 +58,6 @@ ALTERNATE(PIN_MASK(SW_E_, DIO(M3)), 0, MODULE_GPIO, 0) /* Outputs - also mark as inputs so we can read back from the driven pin */ ALTERNATE(PIN_MASK(LED_2, DIO(A9)), 0, MODULE_GPIO, DIO_INPUT) -ALTERNATE(PIN_MASK(LED_3, DIO(A10)), 0, MODULE_GPIO, DIO_INPUT) ALTERNATE(PIN_MASK(LED_4, DIO(A11)), 0, MODULE_GPIO, DIO_INPUT) -ALTERNATE(PIN_MASK(LED_5, DIO(A12)), 0, MODULE_GPIO, DIO_INPUT) ALTERNATE(PIN_MASK(LED_6, DIO(A13)), 0, MODULE_GPIO, DIO_INPUT) ALTERNATE(PIN_MASK(LED_7, DIO(A14)), 0, MODULE_GPIO, DIO_INPUT) - -/* SPS IOs This is not needed for the FPGA, it is hardwired - * TODO_FPGA (might have to be modified for a new version) -ALTERNATE(PIN_MASK(FUNC(SPS0_SPICLK), DIO(A2)), 0, MODULE_GPIO, DIO_INPUT) -ALTERNATE(PIN_MASK(FUNC(SPS0_SPIMOSI), DIO(A3)), 0, MODULE_GPIO, DIO_INPUT) -ALTERNATE(PIN_MASK(FUNC(SPS0_SPICSB), DIO(A4)), 0, MODULE_GPIO, DIO_INPUT) -ALTERNATE(PIN_MASK(FUNC(SPS0_SPIMISO), DIO(A5)), 0, MODULE_GPIO, DIO_OUTPUT) -*/