From df80ec22ca2aa67e3e70eeb987e20fcd870341fe Mon Sep 17 00:00:00 2001 From: Sam Hurst Date: Tue, 6 Sep 2016 13:56:57 -0700 Subject: [PATCH] pwm: PWM is disabled when duty is set to max value The CTR was set to 1 less than the max PWM value, so when the DCR is set to max PWM value, duty goes to zero. The bug is fixed by setting CTR to PWM max vlaue. BUG=chrome-os-partner:57052 BRANCH=None TEST=Manual on terminal. > pwmduty 1 raw 0 Setting channel 1 to raw 0 1: disabled > pwmduty 1 raw 65535 Setting channel 1 to raw 65535 verified that screen didn't blank Change-Id: I10885d382f1bd252a5e7355da99dc00bd876e29f Reviewed-on: https://chromium-review.googlesource.com/381632 Commit-Ready: Shawn N Tested-by: Shawn N Reviewed-by: Shawn N --- chip/npcx/pwm.c | 4 ++-- common/pwm.c | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/npcx/pwm.c b/chip/npcx/pwm.c index 9d16687ddf..f344f1be6c 100644 --- a/chip/npcx/pwm.c +++ b/chip/npcx/pwm.c @@ -84,9 +84,9 @@ static void pwm_set_freq(enum pwm_channel ch, uint32_t freq) NPCX_PRSC(mdl) = (uint16_t)prescaler_divider; /* Set PWM cycle time */ - NPCX_CTR(mdl) = EC_PWM_MAX_DUTY - 1; + NPCX_CTR(mdl) = EC_PWM_MAX_DUTY; - /* Set the duty cycle to 0% since DCR > CTR */ + /* Set the duty cycle to 100% since DCR == CTR */ NPCX_DCR(mdl) = EC_PWM_MAX_DUTY; } diff --git a/common/pwm.c b/common/pwm.c index 761d1dad25..18651d8358 100644 --- a/common/pwm.c +++ b/common/pwm.c @@ -144,8 +144,7 @@ static int cc_pwm_duty(int argc, char **argv) /* Negative = disable */ pwm_enable(ch, 0); } else { - ccprintf("Setting channel %d to%s%d%%\n", - ch, (max_duty == 100) ? " " : " raw ", value); + ccprintf("Setting channel %d to %d\n", ch, value); pwm_enable(ch, 1); (max_duty == 100) ? pwm_set_duty(ch, value) : pwm_set_raw_duty(ch, value);