diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c
index 9dd1f94f95..f454571e8e 100644
--- a/chip/stm32/clock-stm32h7.c
+++ b/chip/stm32/clock-stm32h7.c
@@ -191,6 +191,14 @@ void clock_enable_module(enum module_id module, int enable)
 
 void clock_init(void)
 {
+	/*
+	 * STM32H743 Errata 2.2.15:
+	 * 'Reading from AXI SRAM might lead to data read corruption'
+	 *
+	 * limit concurrent read access on AXI master to 1.
+	 */
+	STM32_AXI_TARG_FN_MOD(7) |= READ_ISS_OVERRIDE;
+
 #if 0 /* Keep default for now: HSI at 64 Mhz */
 	clock_set_osc(OSC_PLL);
 #endif
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 24fe527658..c6e8321c20 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -368,6 +368,8 @@
 
 #else  /* CHIP_FAMILY_STM32H7 */
 
+#define STM32_GPV_BASE              0x51000000
+
 #define STM32_DBGMCU_BASE           0x5C001000
 
 #define STM32_BDMA_BASE             0x58025400
@@ -2947,6 +2949,14 @@ enum dmamux1_request {
 #define STM32_RNG_SR_DRDY           (1<<0)
 #define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
 
+/* --- AXI interconnect --- */
+
+/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
+#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
+					  0x1000 * (x))
+#define  WRITE_ISS_OVERRIDE         (1 << 1)
+#define  READ_ISS_OVERRIDE          (1 << 0)
+
 /* --- MISC --- */
 #define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
 #define STM32_UNIQUE_ID_LENGTH      (3 * 4)