diff --git a/firmware/psu/inc/devices/eeprom.h b/firmware/psu/inc/devices/eeprom.h index b79b9a8fcc..73059138f3 100644 --- a/firmware/psu/inc/devices/eeprom.h +++ b/firmware/psu/inc/devices/eeprom.h @@ -13,6 +13,7 @@ * HEADER FILES *****************************************************************************/ #include "common/inc/global/ocmp_frame.h" /* Temporary, just for OCMPSubsystem def */ +#include "common/inc/global/post_frame.h" /* Temporary, just for OCMPSubsystem def */ #include "drivers/OcGpio.h" #include "inc/common/i2cbus.h" @@ -20,6 +21,9 @@ * MACRO DEFINITIONS *****************************************************************************/ #define OC_TEST_ADDRESS 0xFD0 +#define OC_SKU_BAND_ADDRESS 3 +#define OC_SKU_GBC_ADDRESS 1 +#if 0 #define OC_CONNECT1_SERIAL_INFO 0x01C6 #define OC_CONNECT1_SERIAL_SIZE 0x12 #define OC_GBC_BOARD_INFO 0x01AC @@ -32,6 +36,7 @@ #define OC_RFFE_BOARD_INFO_SIZE 0x11 #define OC_RFFE_DEVICE_INFO 0x0100 /*TODO: Update offsets*/ #define OC_DEVICE_INFO_SIZE 0x0A +#endif /***************************************************************************** * STRUCT DEFINITIONS @@ -43,14 +48,42 @@ typedef struct EepromDev_Cfg { size_t page_size; } EepromDev_Cfg; +typedef enum band_type { + BAND3 = 3, + BAND5 = 5, + BAND28 = 28 +}band_type; + +typedef struct Eeprom_Skucfg { + bool gbc_presence; + band_type band_nbr; +}Eeprom_Skucfg; + +typedef struct Eeprom_PowerCfg { + OcGpio_Pin pin_24v; + OcGpio_Pin pin_5v0; + OcGpio_Pin pin_3v3; + OcGpio_Pin pin_gbcv2_on; + OcGpio_Pin pin_12v_bb; + OcGpio_Pin pin_12v_fe; + OcGpio_Pin pin_20v_fe; + OcGpio_Pin pin_1v8; +} Eeprom_PowerCfg; + typedef struct Eeprom_Cfg { I2C_Dev i2c_dev; OcGpio_Pin *pin_wp; EepromDev_Cfg type; /*!< Device specific config (page size, etc) */ OCMPSubsystem ss; /* TODO: The HW config need not know about the subsytem to be fixed later */ + Eeprom_PowerCfg *power_cfg; } Eeprom_Cfg, *Eeprom_Handle; +typedef struct Eeprom_data { + uint8_t address; + uint8_t data; +} Eeprom_data; + typedef enum { OC_STAT_SYS_SERIAL_ID = 0, OC_STAT_SYS_GBC_BOARD_ID, @@ -88,5 +121,6 @@ ReturnStatus eeprom_read_device_info_record(const Eeprom_Cfg *cfg, ReturnStatus eeprom_write_device_info_record(Eeprom_Cfg *cfg, uint8_t recordNo, char * device_info); +ePostCode eeprom_handle_sku_id(Eeprom_Cfg *eeprom_cfg , Eeprom_Skucfg *sku_id); #endif /* EEPROM_H_ */ diff --git a/firmware/psu/platform/oc-sdr/cfg/OC_CONNECT_PSU.c b/firmware/psu/platform/oc-sdr/cfg/OC_CONNECT_PSU.c index d1de86560c..c94bd7d3f9 100644 --- a/firmware/psu/platform/oc-sdr/cfg/OC_CONNECT_PSU.c +++ b/firmware/psu/platform/oc-sdr/cfg/OC_CONNECT_PSU.c @@ -32,11 +32,23 @@ SCHEMA_IMPORT const Driver_fxnTable LTC4274_fxnTable; * EEPROM CONFIG *****************************************************************************/ +Eeprom_PowerCfg power_line_cfg = { + .pin_24v = { &pwr_io, 3}, + .pin_5v0 = { &pwr_io, 4}, + .pin_3v3 = { &pwr_io, 5}, + .pin_gbcv2_on = { &pwr_io, 6}, + .pin_12v_bb = { &pwr_io, 7}, + .pin_12v_fe = { &pwr_io, 8}, + .pin_20v_fe = { &pwr_io, 9}, + .pin_1v8 = { &pwr_io, 10}, +}; + Eeprom_Cfg eeprom_psu_sid = { .i2c_dev = { OC_CONNECT1_I2C0, 0x56 }, // .pin_wp = &pin_s_id_eeprom_wp, .type = CAT24C256, // .ss = OC_SS_SYS, + .power_cfg = &power_line_cfg, }; Eeprom_Cfg eeprom_psu_inv = { diff --git a/firmware/psu/platform/oc-sdr/schema/schema.c b/firmware/psu/platform/oc-sdr/schema/schema.c index 8d01f83ab8..ce976dfe00 100644 --- a/firmware/psu/platform/oc-sdr/schema/schema.c +++ b/firmware/psu/platform/oc-sdr/schema/schema.c @@ -97,7 +97,7 @@ const Component sys_schema[] = { }, { .name = "eeprom1", - .driver = &CAT24C04_psu_inv, + .driver = &CAT24C04_psu_sid, .driver_cfg = &eeprom_psu_sid, }, { diff --git a/firmware/psu/src/bigbrother.c b/firmware/psu/src/bigbrother.c index f073dbafaf..f132676fa8 100644 --- a/firmware/psu/src/bigbrother.c +++ b/firmware/psu/src/bigbrother.c @@ -37,7 +37,6 @@ OcGpio_Pin pin_12v_fe = { &pwr_io, 8}; OcGpio_Pin pin_20v_fe = { &pwr_io, 9}; OcGpio_Pin pin_1v8 = { &pwr_io, 10}; - /* Global Task Configuration Variables */ Task_Struct bigBrotherTask; Char bigBrotherTaskStack[BIGBROTHER_TASK_STACK_SIZE]; @@ -85,6 +84,38 @@ extern void uartdma_rx_createtask(void); extern void uartdma_tx_createtask(void); //extern void watchdog_create_task(void);; +/***************************************************************************** + ** FUNCTION NAME : bb_init_powerLines + ** + ** DESCRIPTION : Turn on all the power rails on the PSU board + ** + ** ARGUMENTS : None + ** + ** RETURN TYPE : ReturnStatus + ** + *****************************************************************************/ +ReturnStatus bb_init_powerLines() +{ + OcGpio_configure(&pin_24v, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH); + OcGpio_configure(&pin_5v0, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH); + OcGpio_configure(&pin_3v3, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH); + OcGpio_configure(&pin_gbcv2_on, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH); + OcGpio_configure(&pin_12v_bb, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH); + OcGpio_configure(&pin_12v_fe, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH); + OcGpio_configure(&pin_20v_fe, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH); + OcGpio_configure(&pin_1v8, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_HIGH); + + return RETURN_OK +} + /***************************************************************************** ** FUNCTION NAME : bb_sys_post_complete ** @@ -107,41 +138,8 @@ ReturnStatus bb_sys_post_complete() uartdma_rx_createtask(); // P - 07 uartdma_tx_createtask(); // P - 07 count++; - // uart_enable(); - /* TODO: enable this back */ -#if ENABLE_POWER - OcGpio_configure(&pin_24v, - OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); - OcGpio_write(&pin_24v, 1); - OcGpio_configure(&pin_5v0, - OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); - OcGpio_write(&pin_5v0, 1); - - OcGpio_configure(&pin_3v3, - OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); - OcGpio_write(&pin_3v3, 1); - - OcGpio_configure(&pin_gbcv2_on, - OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); - OcGpio_write(&pin_gbcv2_on, 1); - - OcGpio_configure(&pin_12v_bb, - OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); - OcGpio_write(&pin_12v_bb, 1); - - OcGpio_configure(&pin_12v_fe, - OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); - OcGpio_write(&pin_12v_fe, 1); - - OcGpio_configure(&pin_20v_fe, - OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); - OcGpio_write(&pin_20v_fe, 1); - - OcGpio_configure(&pin_1v8, - OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); - OcGpio_write(&pin_1v8, 1); -#endif + bb_init_powerLines(); } return status; } diff --git a/firmware/psu/src/devices/eeprom.c b/firmware/psu/src/devices/eeprom.c index 0ef0a88f40..5051e231c0 100644 --- a/firmware/psu/src/devices/eeprom.c +++ b/firmware/psu/src/devices/eeprom.c @@ -265,3 +265,61 @@ ReturnStatus eeprom_enable_write(Eeprom_Cfg *cfg) /* TODO: error detection */ return RETURN_OK; } + +#if 0 +/* + * The SKU method of turning on powere lines is currently not needed , we will keep it in codebase + * if similar implementation is needed in future + */ + +void eeprom_init_powerLines(Eeprom_Cfg *eeprom_cfg ) +{ + OcGpio_configure(&eeprom_cfg->power_cfg->pin_24v, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); + OcGpio_configure(&eeprom_cfg->power_cfg->pin_5v0, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); + OcGpio_configure(&eeprom_cfg->power_cfg->pin_3v3, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); + OcGpio_configure(&eeprom_cfg->power_cfg->pin_gbcv2_on, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); + OcGpio_configure(&eeprom_cfg->power_cfg->pin_12v_bb, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); + OcGpio_configure(&eeprom_cfg->power_cfg->pin_12v_fe, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); + OcGpio_configure(&eeprom_cfg->power_cfg->pin_20v_fe, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); + OcGpio_configure(&eeprom_cfg->power_cfg->pin_1v8, + OCGPIO_CFG_OUTPUT | OCGPIO_CFG_OUT_LOW); +} + +ePostCode eeprom_handle_sku_id(Eeprom_Cfg *eeprom_cfg , Eeprom_Skucfg *sku_id) +{ + eeprom_init_powerLines(eeprom_cfg); + OcGpio_write(&eeprom_cfg->power_cfg->pin_12v_bb, 1); + + switch (sku_id->band_nbr) { + case BAND3: + OcGpio_write(&eeprom_cfg->power_cfg->pin_5v0, 1); + OcGpio_write(&eeprom_cfg->power_cfg->pin_3v3, 1); + OcGpio_write(&eeprom_cfg->power_cfg->pin_1v8, 1); + OcGpio_write(&eeprom_cfg->power_cfg->pin_20v_fe, 1); + break; + + case BAND5: + OcGpio_write(&eeprom_cfg->power_cfg->pin_12v_fe, 1); + break; + + case BAND28: + OcGpio_write(&eeprom_cfg->power_cfg->pin_12v_fe, 1); + break; + + default: + /* Do Nothing */ + } + + if(sku_id->gbc_presence) { + OcGpio_write(&eeprom_cfg->power_cfg->pin_gbcv2_on, 1); + } + return POST_DEV_FOUND; +} +#endif diff --git a/firmware/psu/src/devices/ocmp_wrappers/ocmp_cat24c04.c b/firmware/psu/src/devices/ocmp_wrappers/ocmp_cat24c04.c index 378494bf32..f73533a8e7 100644 --- a/firmware/psu/src/devices/ocmp_wrappers/ocmp_cat24c04.c +++ b/firmware/psu/src/devices/ocmp_wrappers/ocmp_cat24c04.c @@ -6,9 +6,8 @@ * LICENSE file in the root directory of this source tree. An additional grant * of patent rights can be found in the PATENTS file in the same directory. */ -#include "common/inc/ocmp_wrappers/ocmp_eeprom_cat24c04.h" - #include "common/inc/global/Framework.h" +#include "common/inc/ocmp_wrappers/ocmp_eeprom_cat24c04.h" #include "inc/common/global_header.h" #include "inc/devices/eeprom.h" @@ -34,9 +33,59 @@ static ePostCode _init_eeprom(void *driver, const void **config, return POST_DEV_CFG_FAIL; } +#if 0 +/* + * The SKU method of turning on powere lines is currently not needed , we will keep it in codebase + * if similar implementation is needed in future + */ +/* Logic for the SKU ID stored in the eeprom is as below + * + * | Address | Type | Value | + * -------------------------------------------------- + * | 0 | LTE/SDR | 'L'- LTE | + * | | | 'S' – SDR | + * + * | 1 | GBC | '0' - No GBC | + * | | '1' - GBC is present| + * + * | 2 | Band | 'B' | + * + * | 3 | value | '3' - band 3 | + * | | | '5' - Band 5 | + * | | | '28' - band 28 | + * + * | 4-7 | Reserved for future use | + * + */ +static ePostCode _probe_sku_id(void *driver, POSTData *postData) +{ + ePostCode returnValue = POST_DEV_NOSTATUS; + Eeprom_Cfg *eeprom_cfg = (Eeprom_Cfg *)driver; + Eeprom_Skucfg sku_id; + /* + * As of now we are using only band id and GBC presence + */ + eeprom_read(eeprom_cfg, OC_SKU_BAND_ADDRESS, &sku_id.band_nbr, 1); + eeprom_read(eeprom_cfg, OC_SKU_GBC_ADDRESS, &sku_id.gbc_presence, 1); + + switch (sku_id.band_nbr) { + case BAND3: + case BAND5: + case BAND28: + returnValue = eeprom_handle_sku_id(eeprom_cfg, &sku_id); + break; + default: + /* Error Condition */ + returnValue = POST_DEV_CRITICAL_FAULT; + } + return returnValue; +} +#endif + const Driver_fxnTable CAT24C04_psu_sid_fxnTable = { /* Message handlers */ .cb_init = _init_eeprom, + //.cb_probe = _probe_sku_id }; const Driver_fxnTable CAT24C04_psu_inv_fxnTable= {