diff --git a/board/cr50/board.c b/board/cr50/board.c
index 96182c7865..b3eb22741d 100644
--- a/board/cr50/board.c
+++ b/board/cr50/board.c
@@ -97,6 +97,7 @@ static void init_pmu(void)
 void pmu_wakeup_interrupt(void)
 {
 	int exiten, wakeup_src;
+	int plt_rst_asserted;
 
 	delay_sleep_by(1 * MSEC);
 
@@ -124,11 +125,21 @@ void pmu_wakeup_interrupt(void)
 		delay_sleep_by(3 * MINUTE);
 
 		/*
-		 * If sys_rst_l is configured to wake on low and the signal is
-		 * low then call sys_rst_asserted
+		 * If sys_rst_l or plt_rst_l (if signal is present) is
+		 * configured to wake on low and the signal is low, then call
+		 * sys_rst_asserted
 		 */
-		if (!gpio_get_level(GPIO_SYS_RST_L_IN) &&
-		    GREAD_FIELD(PINMUX, EXITINV0, DIOM0))
+
+		/*
+		 * TODO(crosbug.com/p/56540): When plt_rst_l is connected to
+		 * DIOM3, need to change DIOA13 below to DIOM3 so that
+		 * the correct wake on low setting is being checked.
+		 */
+		plt_rst_asserted = board_properties & BOARD_USE_PLT_RESET ?
+			!gpio_get_level(GPIO_PLT_RST_L) : 0;
+		if ((!gpio_get_level(GPIO_SYS_RST_L_IN) &&
+		     GREAD_FIELD(PINMUX, EXITINV0, DIOM0)) || (plt_rst_asserted
+		     && GREAD_FIELD(PINMUX, EXITINV0, DIOA13)))
 			sys_rst_asserted(GPIO_SYS_RST_L_IN);
 	}
 
@@ -166,6 +177,25 @@ void board_configure_deep_sleep_wakepins(void)
 	GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 1); /* edge sensitive */
 	GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 0);  /* wake on high */
 	GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1);   /* enable powerdown exit */
+
+	/*
+	 * If the board includes plt_rst_l, configure Cr50 to resume on the
+	 * rising edge of this signal.
+	 */
+	if (system_get_board_properties() & BOARD_USE_PLT_RESET) {
+		/*
+		 * TODO(crosbug.com/p/56540): When plt_rst_l is connected to
+		 * DIOM3, need to change DIOA13 below to DIOM3 so that
+		 * the correct pin is being configured.
+		 */
+		/* Disable sys_rst_l as a wake pin */
+		GWRITE_FIELD(PINMUX, EXITEN0, DIOA13, 0);
+		/* Reconfigure and reenable it. */
+		GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA13, 1); /* edge sensitive */
+		GWRITE_FIELD(PINMUX, EXITINV0, DIOA13, 0);  /* wake on high */
+		/* enable powerdown exit */
+		GWRITE_FIELD(PINMUX, EXITEN0, DIOA13, 1);
+	}
 }
 
 static void init_interrupts(void)
@@ -229,6 +259,32 @@ static void configure_board_specific_gpios(void)
 	/* Add a pullup to sys_rst_l */
 	if (system_get_board_properties() & BOARD_NEEDS_SYS_RST_PULL_UP)
 		GWRITE_FIELD(PINMUX, DIOM0_CTL, PU, 1);
+
+	/*
+	 * TODO(crosbug.com/p/56540): Need to connect platform reset to DI0A13
+	 * for current Reef boards. This function is a no-op for Kevin/Gru. When
+	 * platform reset is moved to DIOM3 in HW, then need change to
+	 * GC_PINMUX_DIOM3_SEL and DIOM3_CTL respectively. In addition,
+	 * uncomment the 3 GRWITE() lines for enabling wake on falling
+	 * edge. Note that the DIO_WAKE_FALLING config is not required for
+	 * DIOA13 as the default for this pad is for uart which already includes
+	 * this option for the pminmux setting.
+	 */
+	/* Connect PLT_RST_L signal to the pinmux */
+	if (system_get_board_properties() & BOARD_USE_PLT_RESET) {
+		/* Signal using GPIO1 pin 10 for DIOA13 */
+		GWRITE(PINMUX, GPIO1_GPIO10_SEL, GC_PINMUX_DIOA13_SEL);
+		/* Enbale the input */
+		GWRITE_FIELD(PINMUX, DIOA13_CTL, IE, 1);
+
+		/* Set power down for the equivalent of DIO_WAKE_FALLING */
+		/* Set to be edge sensitive */
+		/* GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 1); */
+		/* Select failling edge polarity */
+		/* GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 1); */
+		/* Enable powerdown exit on DIOM3 */
+		/* GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1); */
+	}
 }
 
 /* Initialize board. */
@@ -610,6 +666,11 @@ void system_init_board_properties(void)
 			 * benchmark for marking the updated image as good.
 			 */
 			properties |= BOARD_MARK_UPDATE_ON_USB_REQ;
+			/*
+			 * Platform reset is present and will need to be
+			 * configured as a an falling edge interrupt.
+			 */
+			properties |= BOARD_USE_PLT_RESET;
 		}
 
 		/*
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc
index 86c82c8aca..34b64abd06 100644
--- a/board/cr50/gpio.inc
+++ b/board/cr50/gpio.inc
@@ -13,6 +13,7 @@
  * so we attach two internal GPIOs to the same pad.
  */
 GPIO_INT(SYS_RST_L_IN,    PIN(1, 0),  GPIO_INT_FALLING, sys_rst_asserted)
+GPIO_INT(PLT_RST_L,       PIN(1, 10), GPIO_INT_FALLING, sys_rst_asserted)
 GPIO_INT(DETECT_AP,       PIN(1, 1),  GPIO_INT_HIGH, device_state_on)
 GPIO_INT(DETECT_EC,       PIN(1, 2),  GPIO_INT_HIGH, device_state_on)
 GPIO_INT(DETECT_SERVO,    PIN(1, 3),  GPIO_INT_HIGH | GPIO_PULL_DOWN,
diff --git a/include/system.h b/include/system.h
index 92a47e2a37..b8895c02e2 100644
--- a/include/system.h
+++ b/include/system.h
@@ -480,6 +480,7 @@ void system_clear_retry_counter(void);
 						/* controller gets a request */
 /* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */
 #define BOARD_NEEDS_SYS_RST_PULL_UP  (1 << 5)   /* Add a pullup to sys_rst_l */
+#define BOARD_USE_PLT_RESET          (1 << 6)   /* Platform reset exists */
 
 /**
  * Get board properites