Commit Graph

4 Commits

Author SHA1 Message Date
li feng
8412404545 ish i2c: use i2c_ports[] to set bus speed
BUG=None
BRANCH=None
TEST=Tested on Soraka ISH modified board, measured I2C speed for std,
fast, fast plus mode.

Change-Id: I0e07c3c73f5f0302fba41ad8e7f83e10e8f0af99
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/817899
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-12-13 00:32:23 -08:00
li feng
39efbc3ada ish i2c: add I2C Fast Mode Plus 1Mbps speed option
Also added CONFI_ISH_I2C_PORT0_SPEED, CONFI_ISH_I2C_PORT1_SPEED, and
CONFI_ISH_I2C_PORT2_SPEED to define speed for each ISH I2C port. By
default, those are set to fast mode, 400kbps, I2C_SPEED_FAST.
The values can be modified in board.h.

BUG=None
BRANCH=None
TEST=On Soraka modified board for ISH, set I2C stardard mode, fast mode
and fast mode plus, measured I2C clock freq using scope respectively and
confirmed the freq matched I2C mode.

Change-Id: I426b50dc935c3760903360a50f6069e99bd0abff
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/784091
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-04 20:02:58 -08:00
li feng
f50b1cec17 ish: correct i2c write operation buffer size
ISH i2c write operation failed due to wrong buffer size passed.

BUG=None
BRANCH=None
TEST=On reef ISH enabled board, verified sensor i2c read/write are
successful.

Change-Id: Icda625ad16e1e60832bb22e3148e23fcb8e6a937
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/418876
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-12 18:34:32 -08:00
Jaiber John
d7b938f857 ish: Add support for ISH chip
This patch adds the initial support for ISH chip to enable the EC
firmware to boot on Intel Integrated Sensor Hub (ISH). The following are
enabled:

1. Inter-Processor Communication (IPC) driver that enables the ISH to
communicate with the host Operating system via shared registers.
2. High Precision Event Timer (HPET) driver that provides configurable
timers for the FW to use in task scheduling.
3. I2C bus driver for accessing sensors.
4. UART console driver with TX support only.

BUG=chrome-os-partner:51851
BRANCH=None
TEST=`make buildall -j`

Change-Id: I15d4c201b799cfa79bed220ee573b75f5cd7b1f7
Signed-off-by: Jaiber John <jaiber.j.john@intel.com>
Signed-off-by: Alex Brill <alexander.brill@intel.com>
Signed-off-by: Gomathi Kumar <gomathi.kumar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/336710
Commit-Ready: Raj Mojumder <raj.mojumder@intel.com>
Tested-by: Jaiber J John <jaiber.j.john@intel.com>
Tested-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Jaiber J John <jaiber.j.john@intel.com>
Reviewed-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-04 18:31:29 -07:00