This CL simplified TACH_TO_RPM formula and abstracted two definitions
(PULSES_ROUND and RPM_DEVIATION) for the pwm-type fan used on boards.
The developers can modify them in board-level driver if fan doesn't meet
the default spec.
In this CL, it also fixed:
1. Declare rpm_pre as array if FAN_CH_COUNT > 1.
2. Add checking for the value of next duty of pwm.
3. Use TAPND pending bit to make sure TCRA is valid.
BRANCH=none
BUG=none
TEST=test fan used in kahlee and Sunon fan with fanset command on
npcx_evb and use faninfo for verifying. Measure the actual rpm by scope.
Change-Id: Ieb07482eb359912286414ccb9738341d98ea99e4
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/472289
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Using HOOK_PRIO_DEFAULT for peripheral initialization necessitates using
HOOK_PRIO_DEFAULT+1 for board-level code. Instead, use a
higher-than-default relative priority for peripheral initialization
outside of board.
BUG=None
TEST=Verify PWM and ADC are functional on kevin.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia8e90a7a866bdb0a661099dd458e3dfcaaa3f6bb
Reviewed-on: https://chromium-review.googlesource.com/342171
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
To get better power consumption in S0, we add FW support for
CONFIG_LOW_POWER_S0.
Before entering deep idle in S0, we must enable Host interrupt to wake up
EC if it needs to service LPC bus.
This version also add a new bit of sleep_mask (SLEEP_MASK_FAN) in system.h
to prevent EC enter deep idle if fan's duty isn't zero. Normally, the freq of
PWM fan is 25 kHz. It means we must select apb2 clock as the source clock of
PWM fan. Or fan would stop when ec enters deep idle because of no PWM signal.
In hwtimer.c, we reset the preload counter to maximum value in ITEI32's ISR
since preload counter is changed by __hw_clock_source_set all the time.
We also found there're no event set if it's deadline is over 32 bits but
current source clock isn't. To prevent ec doesn't wake-up in deep-idle even if
ITIM32 expires, FW set an event for ITIM32 after process_timers().
Modified sources:
1. wheatley/board.h: Add CONFIG_LOW_POWER_S0 definition.
2. clock.c: Enable Host interrupt for LPC.
3. clock.c: Disable LP_WK_CTL for better power consumption.
4. gpio.c: Add ISR for Host interrupt.
5. uart.c: Introduce bit 6 of USTAT to make sure transmitting is completed.
6. register.h: Add uart_clear_pending_wakeup function.
7. hwtimer.c: Fixed watchdog issue when ITIM32 is closed to overflow.
8. fan.c: Enable deep sleep if duty cycle is zero.
9. include/system.h: Add SLEEP_MASK_FAN for fan control loop.
10. core/cortex-m/task.c: Add "isb" to flash the garbage data in the
instruction pipeline.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ibe3630d0d68cf3f32206adb2afa1b5958916a2be
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/324651
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to support rpm mode, we use a TICK function (fan_tick_func) to
monitor tacho value and adjust PWM duty. In this version, fan driver always
enables clock source of MFT to make sure it can present real-time tacho value.
For better performance, the feedback value to adjust PWM duty is various.
We also change fan & pwm settings for SUNUN 4-pins pwm-type fan.
Modified drivers:
1. npcx_evb/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
2. npcx_evb_arm/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
3. fan_chip.h: Remove unnecessary default_count field of mft_t structure
4. fan.c: Add support for rpm mode
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I25e7bd2f3f726b40fd4e0d9a1049a4d82bbd830d
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320510
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Rather than having various PWM module groups initialized from various
HOOK_INIT functions, group them all into a single module and initialize
them all from a common function in pwm.c.
BUG=chromium:563708
TEST=Manual on samus / samus_pd (with CONFIG_ADC enabled). Verify that
samus fan + KB backlight control is functional and samus_pd correctly
sets PWM output.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9f9b09bfa544cd9bc6b7a867e77757dff0505941
Reviewed-on: https://chromium-review.googlesource.com/314882
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Modified drivers:
1. register.h: Add marco field operation funcs for muti-bits field of register.
2. adc.c/fan.c/pwm.c: Simplify field operations by marco funcs.
3. adc.c: Add support for ADC_CH3/4
4. pwm.c: Add PWM_CONFIG_DSLEEP_CLK flag
6. fan.c: Support multi-fans mechanism
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Iaaeb6c4ae8d55b4245a1cefb9c20feae4c0fdec2
Reviewed-on: https://chromium-review.googlesource.com/300673
Commit-Ready: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add npcx_evb_arm board-level driver for arm-based platform.
Add header.c: for booting from NPCX5M5G A3 Booter.
Remove lfw folder due to those functionalitie have been replaced with Booter
Modified drivers for
Patch Set 1:
1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities
2. hwtimer.c: Add ITIM32 for hwtimer
3. lpc.c: Add checking for LRESET
4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter.
5. uart.c: Add support for module 2
Patch Set 2:
6. lpc.c: Modified lpc_get_pltrst_asserted() func
Patch Set 3:
7. minimize the changes for CONFIG_CODERAM_ARCH in common layer
8. comments of Patch Set1/2
Patch Set 4:
9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat.
10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH.
Patch Set 5:
11. Modified system.c in common folder for supporting *_STORAGE_OFF.
12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash.
Patch Set 6:
13. rebase to newest version
14. system.c: Modified for the newest include/system.h
Patch Set 7:
15. Merge from version 0625
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/272034
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Issues fixed on 0216:
1.Modified CONFIG_KEYBOARD_COL2_INVERTED support in keyboard_raw.c
2.Modified warm_reset checking in gpio.c
3.Modified system_get_chip_name in system.c for package info.
4.Modified fan.c and pwm.c for:
● If the DCRn value is greater than the CTRn value, the PWM_n signal is always low.
● Fan stall condition event:
If the measured fan speed is lower than the lowLimit value (unless the Fan Speed Low Limit value is 0) or in case of erroneous measurement, the userCallback is called.
5. Change cycle_pluses to 480 in board.c
Issues fixed:
1. Jump data at top of RAM is getting corrupted. Changed the flag to
RESET_FLAG_RESET_PIN. Added a workaround method to fix VCC1_RST
issue.
2. Hibernate wake need to report whether wake reason was GPIO or RTC
3. Hibernate wake must be distinguishable from watchdog reset. The
booter will log reset reason in Code RAM. I copy the log data to
battery-backup RAM in little FW. And system driver will refer this
data to distinguish if it's watchdog reset or not.
4. Watchdog reset flag is not set. Same fix as 3.
5. Should return error if unable to clear SPI flash status register.
6. Remove chip_temp_sensor.c
7. Remove use of pstate from flash driver
8. Remove support for watchdog warm reset
9. Keyboard raw driver must support COL2 inverted
10. LPC memory mapped data must be read-only from host
11. LPC should support PLTRST# signal
12. Problems reading chip type/version. Use core registers and ROM data to read IDs.
13. When chip type/version is unknown, report hex value.
14. Watchdog does not consistently print panic information.
15. Remove console force enable logic.
16. Enable only the peripheral clocks that are needed. Please notice
user should add bit mask in CGC_XXX_MASK if they want to enable
additional module. For example, if user wants to enable PWM3, he must
add PWDWN_CTL2_PWM3_PD bit in CGC_PWM_MASK.
Please see HOOK_FREQ_CHANGE and HOOK_INIT these two hook functions.
If I turn off all I2C modules in system_pre_init and turn on the
modules I need in i2c_init, I found its freq is not correct. The root
cause is hook_notify(HOOK_FREQ_CHANGE) is executed first (in
clock_init) before i2c_init. At this time, i2c modules are power-down
and writing to freq register is useless. I re-execute freq-changed
hook function after turning on modules again.
17. MPU properly configured to prevent code execution from data RAM
18. Partial nvcontext implementation. Copy these 16 bytes in our battery-backup RAM.
Additional items we also modified:
1. pwm.c: Support open-drain IO type of PWM. (PWM IO-Type cannot by
determined by GPIO, we use bit 1 & 2 of function byte of gpio_alt_func
array to support it)
2. ec_npcxflash.c: Use definition to replace constant value. Stop
watchdog during flash programing.
3. npcx_cmds.tcl: Adjust script sequence for robustness. Add unlock
MPU commands for Data RAM.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=manually verify changes
Change-Id: I722a77d29e7543b054819480c7b7477af4263119
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/248670
Add npcx_evb in board folder for testing
Add shared-spi arch support in common layer.
Modified drivers for
1. Fan.c: console command “pwmduty”.
2. Pwm.c: for the issue when set duty to 0.
3. System.c: for hw reset only during system reset.
4. Flash.c: Fixed access denied bug of the flash driver for host command.
5. Comments from Patch Set 1
6. Comments from Patch Set 3 (except sha256.c)
7. Add openocd and flash_ec support for npcx_evb
8. Add little FW and spi-flash upload FW in chip folder
9. Add optional make rules for PROJECT_EXTRA
10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes
in common layer sources for shared-spi arch. (except sysjump)
11.Find the root cause of JTAG issue and use workaround method
with SUPPORT_JTAG in clock.c
12 Execute hibernate in low power RAM for better power consumption
13 Add workaround method for version console command
14 Modified coding style issues by checkpatch.pl tool
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I5e383420642de1643e2bead837a55c8c58481786
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233742
