This reverts commit 352276235c.
This is required to ensure that PMIC VR decay is enabled before
SLP_S0# is asserted. Else, the setting does not take effect and hence
results in higher power consumption.
BUG=b:69337192
BRANCH=None
TEST=make -j buildall
Change-Id: I6885e7447277d853a2414be299dfea25f5547df4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771054
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
power_board_handle_host_sleep_event was added to allow boards like
poppy to enable/disable PMIC VR decay only once during S0ix
entry/exit. Now that the chipset hooks have been fixed, there is no
need of this board specific callback. If in the future, there is a
need to have such a callback, this change can be reverted.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I1d60e43da6c0d462132593efa26bc52312b81786
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of using HOST_SLEEP_EVENT_S0IX_RESUME as a reset state to
reinitialize S0ix flag, add a new default state
HOST_SLEEP_EVENT_DEFAULT_RESET. This also allows different parts of
the code to take correct action depending upon the state that is
currently triggered.
BUG=None
BRANCH=None
TEST=Verified that SLP_S0# interrupt doesn't get asserted during
runtime S0ix.
Change-Id: Id6fc8f3b015561d2899a9d39796b77a11a57e758
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745901
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For certain cannonlake designs, the 5V rail can be controlled by both
the chipset task as well as other tasks such as the USB charger tasks to
perform BC1.2 detection. This commit introduces an API that allows the
tasks to enable/disable the 5V rail. Enable requests will immediately
enable the rail, however, attempting to disable the rail will only
result in a request. Once all tasks want to turn off the 5V rail, the
rail will be turned off.
A bitmask is introduced to keep track of the requests. Index 0 is for
the chipset task.
All of this is gated behind a config option:
CONFIG_POWER_PP5000_CONTROL
BUG=b:65991615
BRANCH=None
TEST=With other zoombini code, verify that 5V can be enabled and disabled.
Change-Id: I1722b4a272c4d6ee24408929f5a7402051bb9cf3
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/722322
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Replace structure member "level" in power_signal_info with "flags".
"level" has been used on all boards to indicate active-high or
active-low levels. Addition of "flags" allows easy extension of
power_signal_info structure to define various flags that might be
applicable to power signals (e.g. "level"). Going forward, additional
flag will be added in follow-up CLs.
Also, provide a helper function power_signal_is_asserted that checks
the actual level of a signal and compares it to the flags level to
identify if a power signal is asserted.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679979
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This change allows chipset and board to perform any action when host
indicates intention to enter sleep state. Chipset can take action like
enable/disable power signal interrupts and boards can enable/disable
decay of VRs on host intent to enter/exit S0ix.
BUG=b:65732924
BRANCH=None
TEST=make -j buildall
Change-Id: I6298825d4ee96a07b93523c2f366527ae2be8a27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/677498
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch changes the entry/exit model for S0ix from a PCH
SLP_S0 signal based model to a hybrid host event/direct interrupt
model. The kernel will send host events on kernel freeze/thaw exit;
EC will initiate the S0ix entry based on host command and exit via
another host command from kernel.
The assertion of SLP_S0 comes later than HC(suspend) and deasserion
of SLP_S0 comes earlier than HC(resume).
________ ________
SLP_S0 |______________________|
_____ ________
HC |___________________________|
BRANCH=none
BUG=chrome-os-partner:58740
TEST=Build/flash EC and check 'echo freeze > /sys/power/state'
command in OS shell. Verify idle state transitions during display off
and periodic wakes from S0ix do not lead to state transitions in EC.
Change-Id: Ie18c6c2ac8998f59141641567d1d740cd72c2d2e
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/401072
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Allow the host to self-report its sleep state through
EC_CMD_HOST_SLEEP_EVENT, which will typically be sent with SUSPEND
param when the host begins its sleep process. While the host has
self-reported that it is in SUSPEND, don't assert the interrupt
line, except for designated wake events.
BUG=chrome-os-partner:56156
BRANCH=None
TEST=On kevin, run 'ectool hostsleepstate suspend', verify that
interrupt assertion is skipped for battery host event. Run 'ectool
hostsleepstate resume' and verify interrupt is again asserted by the
battery host event.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I74288465587ccf7185cec717f7c1810602361b8c
Reviewed-on: https://chromium-review.googlesource.com/368391
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
this is to move the existing code from chipset level to board level
since PseudoG3 is a board feature that required specific hardware.
BUG=none
BRANCH=glados
TEST=use hibernate command to enter PseudoG3
Change-Id: I309ef89e0ff7057ce46c634baa9791731a771984
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/327677
Reviewed-by: Shawn N <shawnn@chromium.org>
gcc 5.2 bails out on an inline declaration that isn't followed up with
a definition in the same compilation unit.
BRANCH=none
BUG=chrome-os-partner:49517
TEST=compile tested with coreboot's toolchain. samus, oak and others
that failed now build.
Change-Id: Ic9c28fc12c80e24ea0dbf85f35846fd6a0b56a2d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/324970
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
On assertion of SLP_S0, EC goes to S0ix while system is in Lucid sleep
and EC is eligable to enter heavy sleep idle task.
Wakeup from S0ix by lid open, any key press, power button or track pad
will be done by PCH block by asserting SLP_S0.
At S0ix, 1 msec pulse will be generated every 8sec and this signal
should be ignored since this is NOT S0ix entry/exit related and defered
interrupt for SLP_S0 were added.
BRANCH=master
BUG=none
TEST=in OS shell, run following commands.
Following command is valid with coreboot with S0ix patches.
"echo freeze > /sys/power/state"
then,
Measure EC power consumption and compare it with one in S0.
And on EC console, there should be NO periodic message, "power
state 4 = S0ix, in 0x001d" every 8 sec.
Change-Id: Ia9cf5256b1ad7234815d4b6dbe2b45788aaf49dd
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/307947
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The same code exists in four (soon to be five!) different power
sequencing drivers, so move it up to common.
BUG=None
TEST=Manual on Samus. Run "pause_in_s5 on" on EC console, verify that
system stops in S5 on shutdown. Run "pause_in_s5 off" on EC console,
verify that system again goes to G3 on shutdown.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaf05ef7ce017be4f9d173e83e985a7a879ba278c
Reviewed-on: https://chromium-review.googlesource.com/269566
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In the gpio_info struct, we had a irq_handler pointer defined even
though a majority of the GPIOs did not have irq handlers associated. By
removing the irq_handler pointer out of the struct, we can save some
space with some targets saving more than others. (For example, ~260
bytes for samus_pd).
This change also brings about a new define:
GPIO_INT(name, port, pin, flags, signal)
And the existing GPIO macro has had the signal parameter removed since
they were just NULL.
GPIO(name, port, pin, flags)
In each of the gpio.inc files, all the GPIOs with irq handlers must be
defined at the top of the file. This is because their enum values from
gpio_signal are used as the index to the gpio_irq_handlers table.
BUG=chromium:471331
BRANCH=none
TEST=Flashed ec to samus and samus_pd, verified lightbar tap, lid, power
button, keyboard, charging, all still working.
TEST=Moved a GPIO_INT declaration after a GPIO declaration and watched the build
fail.
TEST=make -j BOARD=peppy tests
TEST=make -j BOARD=auron tests
TEST=make -j BOARD=link tests
Change-Id: Id6e261b0a3cd63223ca92f2e96a80c95e85cdefb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/263973
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
We don't have available GPIO pin for power button as the hibernate
(stand-by) wake-up source. Also, we don't want to do board change.
So, put the EC in a decent infinite loop to pretend the hibernate mode
and wait for particular wake-up event. This should be fine because
the AP is already down before EC hibernates.
BUG=chrome-os-partner:25435
BRANCH=Nyan
TEST=see comment #6 of issue for detailed test steps.
Change-Id: I2cae131789f9ca5808b60d5f2495222ca9016e7c
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186061
Reviewed-by: Randall Spangler <rspangler@chromium.org>
For the better naming for power/common.h, we rename CONFIG_CHIPSET_X86
to CONFIG_POWER_COMMON (no one is actually using it). But keep
CONFIG_CHIPSER_TEGRA for power/build.mk.
BUG=chrome-os-partner:25068
BRANCH=nyan,falco,link,peppy,rambi,samus,squawks
TEST=build only
Change-Id: Ibf1a4c24088dfddac39b38a95b3b887c195152d5
Signed-off-by: Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182732
Integrate with power/common.c -- a real state machine now. Also remove
duplicate and unused functions/consts.
BUG=chrome-os-partner:24831
BRANCH=nyan
TEST=on nyan rev 3.12.
re-plug AC: PASS, power on 2
reboot: PASS, power on 2
power off (S5), power on: PASS, power off 4, power on 5
power off (G3), power on: PASS, power off 4, power on 5
lid close / power off (S5)/ lid open: PASS, power on 3
lid close / power off (G3)/ lid open: PASS, power on 3
press power button and release: nothing happens after 15s.
button off (S5)/ on: PASS, power off 3, power on 4
button off (G3)/ on: PASS, power off 3, power on 4
power off (S5)/ button on: PASS, power off 4, power on 4
power off (G3)/ button on: PASS, power off 4, power on 4
button off (S5)/ power on: PASS, power off 3, power on 5
button off (G3)/ power on: PASS, power off 3, power on 4
button off (S5)/ lid open: PASS, power off 3, power on 3
button off (G3)/ lid open: PASS, power off 3, power on 3
is off, long press button (60s): power on 4, too long, shutdown, stay off
is on, long press button (60s): power off 3, stay off
apreset cold: entered to S5, power off 3, power on 5
apreset warm: power state is not changed, but reboots to BIOS.
Change-Id: Ie12fa4f79b6156f71f89155b2b01880914809c75
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182348
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Renaming file names is the first step. Please see issue tracker
for more details.
BUG=chrome-os-partner:24832
BRANCH=link,falco,samus,rambi,peppy
TEST=build all x86 boards.
make clean BOARD=link && make -j32 BOARD=link && \
make clean BOARD=falco && make -j32 BOARD=falco && \
make clean BOARD=samus && make -j32 BOARD=samus && \
make clean BOARD=rambi && make -j32 BOARD=rambi && \
make clean BOARD=peppy && make -j32 BOARD=peppy
Change-Id: I3a296a0c14f6bebefa858438b1320061ac71dd38
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181400
Reviewed-by: Randall Spangler <rspangler@chromium.org>
