2 Commits

Author	SHA1	Message	Date
Nadim Taha	bfd1aba3cb	common/spi_nor: Adds RDID and 64KiB erase support ... Modified the SPI NOR flash driver to implement and expose a read JEDEC ID command as well as support block (64KiB) erase operations. BUG=None BRANCH=None TEST=Built all targets. Tested on two different EEPROMs. Before: ------------------------------------------- $ ~/haven_updater$ ./read_jedec_ftdi [+] JEDEC_ID=0x1940ef $ ~/haven_updater$ time ./chip_erase_ftdi [+] Success! real 4m0.440s user 0m6.674s sys 0m11.998s ------------------------------------------- $ ~/haven_updater$ ./read_jedec_ftdi [+] JEDEC_ID=0xc21a20c2 $ ~/haven_updater$ time ./chip_erase_ftdi [+] Success! real 5m57.291s user 0m9.964s sys 0m18.363s ------------------------------------------- After: ------------------------------------------- $ ~/haven_updater$ ./read_jedec_ftdi [+] JEDEC_ID=0x1940ef $ ~/haven_updater$ time ./chip_erase_ftdi [+] Success! real 1m33.176s user 0m2.327s sys 0m5.050s ------------------------------------------- $ ~/haven_updater$ ./read_jedec_ftdi [+] JEDEC_ID=0xc21a20c2 $ ~/haven_updater$ time ./chip_erase_ftdi [+] Success! real 2m41.923s user 0m4.191s sys 0m8.576s ------------------------------------------- Change-Id: Ic20372ca9966499977a52a700d6492d3f648d7b2 Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/416903 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>	2016-12-07 23:45:29 +00:00
Ewout van Bekkum	99f62cb3a9	common: Adds a JEDEC SFDP v1.* based Serial NOR Flash driver ... Adds a JEDEC SFDP v1.* compatible Serial NOR Flash driver to control multiple Serial NOR Flash devices (NOR EEPROMs, etc.). The SFDP tables are used to discover parts' page sizes and capacities. This driver only supports parts with capacities under 4GiB. If the parts are larger than 16MiB, then the 0xB7 4-Byte addressing mode entry opcode and 0xE9 4-Byte addressing mode exit opcode are required. This driver also assumes that a 4KiB erase opcode of 0x20 is always available. BRANCH=none BUG=none TEST=Tested on cr51 with multiple EEPROMs with various SFDP revs Change-Id: I5c2b757267e23c4f22ac89c6d5048a54b04de0c3 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321922 Reviewed-by: Bill Richardson <wfrichar@chromium.org>	2016-01-28 21:45:37 +00:00