Commit Graph

8 Commits

Author SHA1 Message Date
Randall Spangler
13ad1c007b Implement HOOK_SYSJUMP and use it to preserve LPC host event mask
This also changes shared_mem to use all the remaining RAM, instead of
reserving a fixed-size buffer.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

BUG=chrome-os-partner:9161
TEST=manual

hostevent  --> all masks should be 0
hostevent smi 0x12300000
hostevent  --> should confirm SMI mask was set
sysjump b
hostevent  --> should confirm SMI mask is still set
reboot
hostevent  --> should confirm SMI mask is back to 0

Change-Id: Iccb6da6ccc93ee5036a3f478d24b717a462d9150
2012-04-19 18:15:18 -07:00
Randall Spangler
ee3edc0116 Clean up inits
We can clear the reset cause in system pre-init now because of a
previous change which preserves it across a sysjump.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

BUG=none
TEST=if it boots, it works

Change-Id: I1d8b99df5a0be0de9545d22ad1a6b7fb3140f813
2012-04-19 11:08:28 -07:00
Louis Yung-Chieh Lo
1a9a415cf6 Support chipinfo command (ectool/host commands)
Add a host command returning chip information. The interface is in common/
while the implementations are in chip-specific code (note: added simple
value for stm).

BUG=chrome-os-partner:8567
TEST=on board
% ectool chipinfo
Chip info:
  vendor:    xx
  name:      yyyy
  revision:  zzzzz

Change-Id: I5030a03a6fcfbfc080d5acd8efb763fde7eefde5
2012-04-09 14:25:30 +08:00
Randall Spangler
ed33516e2e Preserve reset cause when jumping between EC images
BUG=chrome-os-partner:8718
TEST=manual

1) Use 'reboot' command from console to boot image.  Should end up in
image A, with last reset reason soft cold.  'sysinfo' should show we
jumped to this image.

2) sysjump RO.  Should end up in RO; otherwise same as 1)

3) reboot using Power+Esc+Reload.  Should end up in image RO, with last
reset reason reset pin.  'sysinfo' should show we did not jump to this
image.

4) sysjump A.  Should end up in A with reset reason reset pin.
'sysinfo' should show we jumped here.

Change-Id: I2dd5595eab4ba2c91bfe8b2b2e9677d7732aca63
Signed-off-by: Randall Spangler <rspangler@chromium.org>
2012-04-03 09:26:25 -07:00
Louis Yung-Chieh Lo
b71837716d flash write and erase commands protect the active image.
Comapre the range to be write (erase) with the range of active image.
If overlap, return error to indicate the access denied.

Note that we actually protect only runtime code and ro data.
FMAP is intentional unprotected so that flashrom can update to new map
before jumping. Since the vector table and init code are in the same
erase page, they are unprotected as well.

BUG=chrome-os-partner:7478
TEST=

Change-Id: Icb5cc89836432a11cef80e18eb66bb39a6c9b1d9
2012-03-27 14:36:45 +08:00
Vincent Palatin
a94e3277b3 update versioning information stored in the EC
Add build information (date/time/builder) which can be displayed at the
EC console.

Generate a version from the board name and the branch tag.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=chromium-os:27013
TEST=on BDS, run version command on the console.
inspect the built binary.

Change-Id: Idb1f68898ba6b811d02919f17ab4536ed9f8934a
2012-03-02 16:46:26 +00:00
Vincent Palatin
84dc68283e Split reset cause and image copy code.
Preparatory work to introduce a second SoC : 3rd series 2/2

All the RO/A/B firmware copy code could be generic to all our platforms.
The console commands are a 'standard' API.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=None
TEST=on BDS EC console, check the reset cause with the 'sysinfo' command.

Change-Id: Ieeb84571085d88b5747a09da4c33d3852bb0da96
2012-01-26 22:34:41 +00:00
Randall Spangler
bdf7da5b08 Initial sources import 1/3
source files mainly done by Randall.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

Change-Id: Iaff83a842b17f3350fb6f2a3f1597ad4c29bd12a
2011-12-07 19:10:02 +00:00