Add touchpad related host commands:
1) EC_CMD_TP_SELF_TEST: run open short test.
2) EC_CMD_TP_FRAME_INFO: get number of frame and frame size.
3) EC_CMD_TP_FRAME_SNAPSHOT: make a snapshot of the frame.
4) EC_CMD_TP_FRAME_GET: get frame data.
BRANCH=none
BUG=b:62077098
TEST=`make BOARD=rose -j`
`ectool --name=cros_tp tpselftest` and
`ectool --name=cros_tp tpframeget` works
Change-Id: I43db82278e556b1e6f6301fe88233fe7c4a18a14
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/515282
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
When vendor commands are processed by the TPM device, the result of
the command execution is communicated through the TPM response header.
When vendor commands are sent through USB the command execution result
value is lost, as the USB reply includes only the response payload,
(if any), but not the result value.
With this patch the single byte result value is prepended to the USB
response payload. The recipient will always look for the value in the
first byte of the response to find the vendor command execution
status.
The corresponding change to the Cr50 usb_updater will remove the
response code from the payload before considering the command's return
data.
BRANCH=cr50
BUG=b:35587387,b:35587053
TEST=verified proper existing extension commands processing (post
reset, turn update on) by the new version of usb_updater and
backwards compatibility with earlier Cr50 RW version (down to
0.0.13).
Change-Id: I5c8b3ea71d3cbbaccc06c909754944b3ab04675d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/525093
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When invoking vendor command handlers in try_vendor_command(), the
buffer containing the command is passed to the handler to communicate
the command contents and to hold the command execution return data. It
was fine when invoking vendor command handlers from the TPM stack, as
the receive buffer is 4K in size and is large enough for any expected
vendor command response.
It is different in case of USB: the command is in the receive buffer
of the USB queue, and the response data could easily exceed the
command size, which would cause corruption of the USB receive queue
contents when the response data is placed into the same buffer where
the command is.
Let's introduce a local storage to pass the command and receive the
response data from the handler. 32 bytes is enough for the foreseeable
future, should a need arise for a larger buffer, testing would result
in an error (a new error type is added to indicate insufficient buffer
space for command processing).
BRANCH=none
BUG=b:35587387,b:35587053
TEST=with the rest of the patches applied verified proper processing
of the 'Get Board ID' command for which response size exceeds the
request size.
Change-Id: I2131496f3a99c7f3a1869905120a453d75efbdce
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/525092
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Mix in board-generated entropy with the externally provided one,
which should help make the per-device secret stronger.
BRANCH=none
BUG=b:38486828
TEST=reboot; rollbackaddent Hello => works fine when USB is connected,
fails otherwise, as board-generated entropy relies on USB timing.
Change-Id: I314f44759c5f8b859913a748db95e9d42b5cdd11
Reviewed-on: https://chromium-review.googlesource.com/518609
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Mattias Nissler <mnissler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This function will be used to generate some entropy using the
Clock Recovery System.
BRANCH=none
BUG=b:38486828
TEST=make BOARD=hammer -j tests
./util/flash_ec --board=hammer --image=build/hammer/test-entropy.bin
EC console: runtest
TEST=Test fails when no USB connection is active
TEST=Test passes when USB connection is active
TEST=Pasting the values into:
tr ';' '\n' | awk 'BEGIN { e = 0; tot=16384.0 }
{ p = $1/tot; if (p > 0) { e -= p*log(p)/log(2) } }
END { print e }'
shows an entropy > 4 bits per sample.
Change-Id: I2363c7bce42c72c33ef0bf3f099d709ee9c13d13
Reviewed-on: https://chromium-review.googlesource.com/518608
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Cr50 has different gpio configurations for different boards. They cannot
be determined until board_init. We want a way to delay enabling the gpio
interrupts until the board type can be determined.
This change adds a gpio flag, GPIO_INT_DISABLE. When set gpio_pre_init
will setup the interrupt, but not enable it. board_init then enables all
of the interrupts with init_interrupts.
BUG=b:35587228
BRANCH=cr50
TEST=use 'gpiocfg' to verify the setup hasn't changed. Add print
statements to verify that gpio_pre_init skips enabling the interrupt on
any gpio that has GPIO_INT_DISABLE set
Change-Id: I91f73297ab80781b99aa82eda479ae311c13cb77
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/523808
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The UART block on the g chip has no functionality to adjust the parity.
Unfortunately, this feature is needed for certain applications.
This commit adds a UART bit bang driver with support for configuring the
baud rate and parity. It currently only supports 8 data bits.
BUG=b:35648297
BRANCH=cr50
TEST=make -j buildall
TEST=With some other patches, successfully flash rowan EC at 9600 baud.
Change-Id: I86a160c0960e46b3a8bb1057518f625aefb7d81f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/503473
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The default USB packet has a maximum size of 64 bytes, however, we need
to support some USB over I2C write transaction that exceed this default.
To support so with protocol backwards-compatible in mind, we enable a
config option CONFIG_USB_I2C_MAX_WRITE_COUNT that will enlarge the USB
RX queue.
BRANCH=none
BUG=b:35587174
TEST=Complete presubmit test.
TEST=Manually update elan trackpad firmware with interrupt disabled.
Change-Id: Ia8983b036b7297f7ca673459ae34b7e5ecd2ee01
Reviewed-on: https://chromium-review.googlesource.com/513642
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
There is a new keyboard matrix layout:
- We can map the search key to both KSO1, KSI0 and KSO0, KSI3
(old layout will only use the former, new layout will use the latter).
- There is a new key on KSO0, KSI5, which we can map to HID page 0xffd1
code 0x0018.
BRANCH=none
BUG=b:62004286
TEST=Flash hammer
kbpress 0 3 1; kbpress 0 3 0 reports KEY_LEFTMETA as expected
kbpress 0 5 1; kbpress 0 5 0 reports "BTN_0", which is probably
incorrect, and needs to be fixed.
Change-Id: I9fb428805ff756b6d63f50cc5b061c6a0e1defbc
Reviewed-on: https://chromium-review.googlesource.com/512502
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Some device has large pages that take up to 2s to erase.
Add support to send a deferred erase command, that willi
be processed on HOOK task.
It can leave the other tasks (HOST_CMD) responsive.
If the whole EC can stall on flash erase, like the STM32F4 do,
at least the command FLASH_ERASE_GET_RESULT can be retried when it times
out.
BRANCH=none
TEST=Check with flashrom doing a loop of overwrites.
BUG=b:38018926
Change-Id: I8ce8e901172843d00aac0d8d59a84cbd13f58a10
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/510012
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
This patch adds vendor and console commands to read and write the
board ID space in the INFO1 block.
Current image's board ID settings are saved in the image header by the
latest codesigner.
Board ID write attempts are rejected if the board ID space is already
initialized, or if the currently running image will not be allowed to
run with the new board ID space settings.
Error codes are returned to the caller as a single byte value.
Successful read command returns 12 bytes of the board ID space
contents.
The console command always allows to read the board ID value, and
allows to write it if the image was built with debug enabled.
BUG=b:35586335
BRANCH=cr50
TEST=as follows:
- verified that board ID can be read by any image and set by debug
images.
- with the upcoming patches verified the ability to set and read
board ID values using vendor commands.
Change-Id: I35a3e2db92175a29de8011172b80091065b27414
Signed-off-by: Philip Chen <philipchen@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/522234
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Add the implementation of a robust non-volatile incrementing counter
using 2 pages from the underlying flash.
It is used to implement the U2F functionality.
The main goal of the counter is providing a strictly incrementing value
whatever adverse events (malicious or not) happen as it is used to
prevent rollback attacks in the U2F protocol.
Given the limitation of the flash process: ie wear-out endurance and
2kB-page erase granularity only and possible isolated bit-flips
(accentuated by power losses), the counting is done by pulling down
several bits at a time from their erased state (1) to 0.
The counting is implemented this way with 2 pages called LOW and HIGH:
The LOW page is implemented in a strike style, with each "strike" zero-ing
out 4 bits at a time, meaning each word can be struck a total of 8
times.
Once the LOW page is completely struck, the HIGH page is incremented by 2.
The even increment is for the value, the odd increment is a guard signal
that the LOW page must be erased. So as an example:
If HIGH is 2, the LOW page would increment to 3, erase itself, and then
increment to 4. If this process is interrupted for some reason (power loss
or user intervention) and the HIGH left at 3, on next resume, the HI page
will recognize something was left pending and erase again.
For a platform with 2-kB flash pages, it can count up to 8388608, then
it is stuck at 0xFFFFFFF indefinitely.
Mostly copied over from Marius code in cr52 code-base.
Signed-off-by: Marius Schilder <mschilder@google.com>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=cr50
BUG=b:35545754
TEST=with follow-up CLs, run U2FTest on Eve
Change-Id: Idd0756078e3641c4a24f9c4ccf6611909bd5f00f
Reviewed-on: https://chromium-review.googlesource.com/518135
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The previous boards that used double tap both used lightbar
sequence. Eve, also needs double tap, but doens't have lightbar. Added
a board specific call when processing the double tap event to allow
more flexibility.
BUG=b:35584895
BRANCH=none
TEST=Manual tested double tap and verified it was detected based on
the console print.
Change-Id: I73d8669803e7dcbbbac00de09822f4a286965fce
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/516546
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
It needs to be possible to prevent unlocking of CCD on enterprise
enrolled devices, in particular to prevent users from moving into dev
mode.
A bit in the FWMP structure flags field was allocated for the purposes
of preventing console unlock in those cases.
This patch adds code to read the FWMP structure from the TPM NVMEM,
verify it and determine if it should be possible to unlock the
console. The restriction is not honored by Cr50 DBG images.
The FWMP value is read only once per TPM reset, this means each time
the admin console changes the relevant flag bit, the Chrome OS device
has to be rebooted to pick up the new flag value.
BRANCH=cr50
BUG=b:35587387,b:35587053
TEST=verified that FWMP is properly read and acted upon.
Change-Id: I17e15ea2b2293a0c096858fba3ccc389452caede
Reviewed-on: https://chromium-review.googlesource.com/457824
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
In order to ensure we are always meeting the deadlines for the IRQ_HPD
pulse, increase the priority of the processing by moving the rising edge
from the low-priority HOOK task (in a deferred function) to the caller
task (which is the high-priority PD task).
The downside is we are now sleeping in the PD task blocking the
processing of the PD messages during this time.
Changed HPD_DSTREAM_DEBOUNCE_IRQ to 500us instead of 750us. According
to DP spec, the IRQ_HPD pulse width is between 500us and 1000us.
Ensure there is a minimum of 2ms delay in between each IRQ_HPD as specified
by the DP spec, by sleeping before sending the next pulse if needed.
(in practice, this should not wait if we are not too off processing the
messages)
BUG=chromium:711334
BRANCH=glados strago reef oak
TEST=manual, on SKL platform with kernel 3.18 and MST, verify display is
functional on USB-C dock.
Change-Id: Ib2e9dd608c5f1c671cc5a0fd979a5742101375ff
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508629
Reviewed-by: Todd Broch <tbroch@chromium.org>
As part of the pairing process, AP needs to be able to inject
some entropy into the base.
Let's also define PAIR_CHALLENGE, which will be implemented in
a later CL.
BRANCH=none
BUG=b:38487027
TEST=Flash hammer. On host, reboot hammer to RO:
usb_updater2 -r; sleep 0.5; usb_updater2 -s
usb_updater2 -e (adds entropy)
EC console: check that rollbackinfo shows secret is updated
Change-Id: I964bb578c6bfbb1ab5105a70b43682d51df4ed47
Reviewed-on: https://chromium-review.googlesource.com/513807
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Previously, result codes were being stored as `enum ec_status` values.
The compiler was forcing this value to only be one byte large, since
that's all that was necessary to represent all the values of that
enum.
This change fixes this bug by switching result code variable types from
`enum ec_status` to `uint16_t`.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: Iacdca51dc6c1de677d2fbb59ad6dd2572d21ea7f
Reviewed-on: https://chromium-review.googlesource.com/513609
Commit-Ready: Jeff Andersen <jeffandersen@google.com>
Tested-by: Jeff Andersen <jeffandersen@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
For pairing purpose, we want to store some secret random number in
the base. The most convenient location for this is the rollback
region.
Since the rollback region can now be updated without incrementing
rollback_min_version (when we add entropy to the secret), we need
to add an increasing id to tell the code which rollback region is
the latest.
We also add console commands to manually add entropy.
BRANCH=none
BUG=b:38486828
TEST=Flash hammer (with or without CONFIG_ROLLBACK_ENTROPY_SIZE set)
rollbackinfo => 1 version 0 block, 1 empty block, RW verifies
correctly.
rollbackupdate 0; rollbackinfo => No change
rollbackupdate 1; reboot => RO refuses to jump to RW
only when CONFIG_ROLLBACK_ENTROPY_SIZE is set:
rollbackinfo => Secret is [00..00] on both blocks (so the data
was copied correctly)
rollbackupdate 2, 3, 4; rollbackinfo => Writes alternate
between the 2 blocks.
rollbackupdate 2 => Refuses to downgrade version
TEST=From blank secret [00..00], 'rollbackaddent Hello' updates it
to [ba..fa], which matches the output of:
(dd if=/dev/zero bs=1 count=32; echo -n Hello) | sha256sum
Change-Id: I79c3e790e56e21958cc1b4ba05bd4e5f359d3090
Reviewed-on: https://chromium-review.googlesource.com/511985
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Move the existing fingerprint host command in the driver and
add more of them to prepare the new fingerprint architecture.
The commands are mostly stubbed for now.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
CQ-DEPEND=*364728
BRANCH=none
BUG=b:35648259
TEST=make BOARD=eve_fp (with and without a private repository)
do a fingerprint image capture with 'fptest'.
Change-Id: Ie17a5fde2d6470c6272e8059bddc845cea07aff2
Reviewed-on: https://chromium-review.googlesource.com/491071
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Typically, we do not need RW section to be able to update rollback
information (rollback block should be protected when RW is running),
so we can save some flash space by undefining this option.
BRANCH=none
BUG=b:35586219
TEST=make newsizes saves ~420 bytes on hammer and staff.
Change-Id: Ic457673e56ace083f2ebb1ca0f37f54bf125bfa4
Reviewed-on: https://chromium-review.googlesource.com/511983
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Adds min_frequency and max_frequency to struct motion_sensor_t.
New attributes min_frequency and max_frequency are now returned in
ectool's MOTIONSENSE_CMD_INFO response.
Incremented ectool's MOTIONSENSE_CMD_INFO version to version 3.
Add constants for MIN_FREQUENCY and MAX_FREQUENCY to each sensor's
header file.
BRANCH=none
BUG=chromium:615059
TEST=build/boot and verify MOTIONSENSE_CMD_INFO response on kevin,
make buildall -j passes.
Change-Id: I66db9715c122ef6bb4665ad5d086a9ecc9c7c93a
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/482703
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This change adds CONFIG_POWER_BUTTON_INIT_IDLE. When it's set,
the system starts with the power button state idle. It means
when the board boots from power-off, it stays at G3.
BUG=b:37536389
BRANCH=none
TEST=Power on Fizz. Verify it stays at G3. Verify it boots
by pressing power button.
Change-Id: I09a62a69d9f201b2dc261838cc9b4425fe3a8dc1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486945
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Add an option to allow the scancode sets to be mutable. The only
reason to use this is to allow a scancode to be changed at runtime,
for instance to support different keyboards in one image.
The side effect of this is the scancode sets are moved out of the
shared RO section.
BUG=b:36735408
BRANCH=none
TEST=make -j buildall
Change-Id: Iefb97691d1f295411d7b5db603d9214d41af49fd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506717
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
First, libpayload expects the keyboard interface index to be 0.
Then, hid_iface_request needs to reply to USB_HID_DT_HID request
with the content of struct usb_hid_descriptor. With current code,
the variable name is generated (and therefore hard to guess), so
we create a new set of macros so that we can use a specific
variable name.
Also, add support for HID Get_Protocol and Set_Protocol, as they
are compulsory for devices supporting boot protocol, even though
those are mostly no-op for now.
Finally, add a note regarding USB HID keyboard boot protocol, to
make sure that we do not accidentally change the report format.
BRANCH=none
BUG=b:36538963
TEST=Keyboard works in FW screen, both trackpad and keyboard
still work when AP has booted.
TEST=hammer/staff can still be updated (both RO from RW, and RW
from RO)
Change-Id: Ibea4888385909c9ce3b430464e5805c039d4b9ed
Reviewed-on: https://chromium-review.googlesource.com/505796
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some chip supports two owned slave address. The second slave address is
used for other purpose such as board specific i2c commands. This option
can be set if user of the second slave address requires larger host
packet er size.
BRANCH=none
BUG=b:37187312
TEST=`make BOARD=rose -j`
Change-Id: I8d0b04bf4dded55e3957c7b25d849663299593e5
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472288
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
This patch clones I2C slave and hostcmd driver from stm32f0.
This patch contains contribution from Wei-Ning Huang <wnhuang@chromium.org>
for fixing i2c slave transmitter (CL:471726).
BUG=chromium:688979
TEST=build and load on dev board, run i2cget/set on host and check
return value.
BRANCH=none
Change-Id: I3d159d5bdd4bda6c229cf6d275ab4982836628dc
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/461037
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
In principle, trackpad dimensions (logical and physical), can be
probed from the trackpad at runtime, but this would slow down setup
time, as we need to wait for the trackpad to be initialized to read
those. Also, we do not have a framework to generate HID report
at runtime, and a new base with new trackpad would probably require
a new overlay anyway.
Also, set appropriate (temporary) values for both hammer and staff.
BRANCH=none
BUG=b:38277869
TEST=Connect hammer/staff to host, correct logical dimensions are
shown in evtest, and resolution is always 32.
Change-Id: I39b84274d71ca2f4e285f3324c0841331aae9bc1
Reviewed-on: https://chromium-review.googlesource.com/505856
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Cr50 masks the recovery button signal on a proto board when the
power button is being pressed (b:37682117). This bug has to be
fixed for the recovery button to work.
BUG=b:37274183
BRANCH=none
TEST=make buildall
Change-Id: Ia413ffce84d67b6f24f983ccce8ae8277452ac2c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494069
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When (USB-)resuming from deep-sleep, ensure that we avoid switching back
and forth the selected USB PHY at boot, in order to avoid having a
short disconnection at resume.
To achieve this, allow the board configuration to select the PHY it is
really using with the CONFIG_USB_SELECT_PHY_DEFAULT configuration
variable, still keep the default USB_SEL_PHY1 as before.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=manual: build 'proto2' firmware with CONFIG_LOW_POWER_IDLE defined,
with the chip connected to the host on PHY A, make the host issue a USB
Suspend then resume and see no disconnection.
Change-Id: I7abd5e338e5c688c2dd486293f520049cdfd273b
Reviewed-on: https://chromium-review.googlesource.com/501947
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch adds a dedicated charge port. The number of such ports
is specified by CONFIG_DEDICATED_CHARGE_PORT_COUNT. It works as a
sink only. The total number of charge ports is represented by
CHARGE_PORT_COUNT.
BUG=chromium:721383
BRANCH=none
TEST=make buildall. Boot Fizz off of barrel jack.
Change-Id: Ibbb11f3e1c66e35b5abe190e49161eeaa2009994
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501468
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
console_is_restricted() function exists only if
CONFIG_RESTRICTED_CONSOLE_COMMANDS is defined, and a stub if it doesn't.
so we can use CONFIG_LOW_POWER_IDLE without the former.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=manual: build 'proto2' board with CONFIG_LOW_POWER_IDLE defined.
Change-Id: I0c7fd201a1f07371aee2420eafd96ac62a5ae4ca
Reviewed-on: https://chromium-review.googlesource.com/500148
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This CL implements two methods for hibernating on npcx7 ec. One is using
PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The
other is turning off the power of all ram blocks except the last code
ram block. In order to make sure hibernate utilities are located in the
last code ram block and work properly, we introduce a new section called
'after_init' in ec.lds.S.
We also moved the hibernate utilities, workarounds for sysjump and so on
which are related to chip family into system-npcx5/7.c. It should be
easier to maintain.
It also includes:
1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for
hibernating.
2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of
wake-up inputs during hibernating.
3. Add DEVICE_ID for npcx796f.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found. Make
sure AC_PRESENT and POWER_BUTTON_L can wake up system from
hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is
enabled or not on npcx796f evb.
Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/493006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch declares recovery_buttons array, where each board
lists recovery buttons. Pressing those while the board reboots
makes the system enter recovery mode.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I1f204156efbd6d2a507d67ba90f75ce857b03559
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486944
On some boards, the boot key combinations do not make a lot of
sense, so we can just not process them and save a little bit
of code space.
BRANCH=none
BUG=b:37422577
TEST=Flash hammer
TEST=make newsizes shows we save 156 bytes in hammer RW.
Change-Id: Ic96d7ed1dbee10f44f8b08568ab70b2f20961842
Reviewed-on: https://chromium-review.googlesource.com/495968
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On some boards, the special alt-volup-r/h combinations do not make
a lot of sense, so we can just not process them and save a little
bit of code space.
BRANCH=none
BUG=b:37422577
TEST=Flash hammer, alt-volup-r/h does not do anything special
TEST=make newsizes shows we save 124 bytes in hammer RW.
Change-Id: I92770fd6b8ff90780162a6b1de428a550bb44e9b
Reviewed-on: https://chromium-review.googlesource.com/495967
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The cros_ec_debugfs creates the `console_log` debugfs entry if EC
supports EC_CMD_CONSOLE_READ version 1. On device where i2c command
latency is critical, periodic console_read is impacting the timing of
commands.
BRANCH=none
BUG=b:37584134
TEST=on rose with CONFIG_CONSOLE_ENABLE_READ_V1 undefined, the kernel
should not create cros_tp/console_log.
Change-Id: I40d0b959ef36f2f410155fa30e01c8169032a3e9
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/494546
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Add new host command EC_CMD_RWSIG_ACTION for controlling rwsig task.
This allow us to make firmware stay at RO without toggling reset pin.
flashrom can use this host command and removed the need to use any
out-of-band pin to toggle the reset pin (and make RWSIG stay in RO).
BRANCH=none
BUG=b:37584134
TEST=on eve, `ectool --name=cros_tp rwsigaction abort` should prevent EC
from jumpping to RW after RWSIG check.
Change-Id: Ia435e4e3ea8ed612a1250d3bf755ca50e5db9d37
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/497787
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This CL added the support for the quasi-bidirectional buffer which has
an open-drain output and a low-impedance pull-up resistance on KSO pins.
The low-impedance pull-up is active when ec changes the output data
buffers from 0 to 1, thereby reducing the low-to-high transition time.
Add CONFIG_KEYBOARD_KSO_HIGH_DRIVE to enable/disable this feature for
npcx7 series ec.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
Change-Id: I138f0e433394816e1e5c58b5053580f202c1ac48
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/497189
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL added support for 8 i2c controllers and 11 i2c ports in
npcx7 series ec. we also added i2c-npcx5/7.c and moved the functions
related to chip family to them. (Such as i2c_port_to_controller(),
i2c_select_port() and so on.) Note the layout and bit position of i2c
registers which are accessed in these functions are irregular between
npcx5 and npcx7. We think abstracting them from i2c.c is easier to
maintain.
In this CL, we also modified the checking rule for I2C_PORT_COUNT in
task.h in order to prevent compiler error. So far, the ECs besides
stm32 only use TASK_EVENT_I2C_IDLE to wait for i2c hardware completes
its job. Put (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C) checking rule
for all ECs seems not suitable.
It also includes
1. Remove useless NPCX_I2C_PUBIT macro function.
2. Remove useless NPCX_PWDWN_CTL_COUNT in registers.h.
3. Add CGC_OFFSET_I2C2 and CGC_I2C_MASK2 to power down the other 4 i2c
controllers of npcx7 ec.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
All 8 i2c controllers and 10 ports (npcx796f supports PSL.) passed
i2c stress tests on npcx796f evb.
Change-Id: I2b5076d21bcd0f8d17fd811cad2ff7bd200b112a
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/487541
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Create an app to extract relevant information
from the EC code base that's used to create Vendor
Information Files (VIFs) needed for USB Type-C
compliance testing.
BUG=chromium:701852
BRANCH=none
TEST=make -j buildall
Compared generated VIFs to expected values
Change-Id: I600ca78b9fb5d2de78aa65a58264c6f79b36ea17
Reviewed-on: https://chromium-review.googlesource.com/455280
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch clears the typematic buffer when disabling keyboard scan.
When the device goes to tablet mode with a key being pressed, this
should prevent keyboard_protocol_task from sending scan codes to the
host.
BUG=b:35585725
BRANCH=none
TEST=make buildall. Tested on Electro.
Change-Id: I73e9d2948b472458814967307412aebeb410ff2e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425075
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When usb_wake is called (key press, trackpad event), pulse
detection pin for 100us. This allows Lid EC to wake the AP
even when it is in deep S3 mode, where normal wake using USB
lines does not work.
BRANCH=none
BUG=b:35775062
TEST=Flash hammer, looks at poppy console: base power is not
disconnected, but events appear in the console.
Change-Id: I7b8ee407046d4caa1ce75190c30d693b71b00d2e
Reviewed-on: https://chromium-review.googlesource.com/448380
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Augmented PDOs are part of the PD3.0 specification. As present USB PD
sinks can't support these PDO types we need to ignore them.
BRANCH=samus,glados,oak,gru,reef
BUG=b:37476637
TEST=manual,
On samus, plug-in blackcat (EVT) charger and see it ignore these
Augmented PDOs when making its PDO request.
Change-Id: I28a0377e1486368f25f37cad640af71244a4c30b
Reviewed-on: https://chromium-review.googlesource.com/484687
Commit-Ready: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
