We use rand to get timestamp counter low word and do random test
(test_dev = rand % i2c_test_dev_used).
But we will get a negative index (test_dev) if low word larger than
0x80000000 and cause the array to access the wrong locations and
trigger an exception.
This change also fix following error:
error: i2c_s_test may be used uninitialized in this function
[-Werror=maybe-uninitialized]
BRANCH=none
BUG=none
TEST="forcetime 0 0x80000000" then "i2ctest", no exception triggered.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ia2f5a2ff034a6b7b96f7bd4f3b42bf5645a05aed
Reviewed-on: https://chromium-review.googlesource.com/663110
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch adds USB_CHG_TYPE_DEDICATED to enum usb_chg_type. It's
for dedicated AC adapters like a barrel jack adapter used for Fizz.
BUG=b:65591971
BRANCH=none
TEST=make buildall
Change-Id: Ib883c97eb5e468753c73453d7dedd228547ae025
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/665327
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch gives the highest priority to dedicated chargers. It
means if a dedicated power supply is being connected, other power
supplies such as USB-C adapters will not be recognized as a new
charger.
BUG=b:65059574
BRANCH=none
TEST=Boot Fizz on BJ adapter. Verify plugging in Type-C adapter
doesn't shut down the system.
Change-Id: Ie49b128ae64f917a227f9081148565a3f5356212
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/655638
Reviewed-by: Shawn N <shawnn@chromium.org>
1. Add a new config option CONFIG_PORT80_PRINT_IN_INT which is
disabled by default to disable printing of port80 messages in
interrupt context.
2. If CONFIG_BRINGUP is defined, redefine CONFIG_PORT80_PRINT_IN_INT
to enable printing of port80 messages in interrupt context for boards
that are in bringup phase.
3. If print_in_int is disabled, add a deferred call to dump port80
buffer to EC console 4 seconds after the last port80 message is
received.
BUG=b:64196191
BRANCH=None
TEST=Verified following:
1. make -j buildall
2. Port80 messages are not printed by default on Soraka
3. Port80 buffer is dumped 4 seconds after last port80 message, if
BIOS is stuck for 4 seconds, in recovery mode and when reboot from AP
console.
4. Boot time on soraka went down from ~1.59seconds to ~1.45 seconds in
EC reboot case (savings of ~140ms).
Change-Id: I9aee0987765f905b4ac49d04ffc54d71ee3a04f9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/661880
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Messages generated using the CPRINTS macro include a newline in the
end by design, no need to explicitly include it in the message.
BRANCH=cr50
BUG=none
TEST=verified that the message is printed without the extra newline
Change-Id: I01994bcb95c78e2deaa2dc3617bea9ca8a6d1381
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/663668
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The modified CRC8 implementation didn't detect some errors. For
example, using the modified CRC8: CC5QQLALU and DC5QQLALU calculates
to the same value.
BUG=b:37952913
BRANCH=none
TEST=make buildall
Used online CRC-5-USB calculator to test several values against
this implementation.
Signed-off-by: Sam Hurst <shurst@chromium.org>
Change-Id: I5a17941e25691872a25b41525f65f36e2ed1d4fa
Reviewed-on: https://chromium-review.googlesource.com/660812
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Michael Tang <ntang@chromium.org>
Chromebox ECs performs EFS: verifying firmware before the AP boots.
This patch updates host commands which are required for the EFS.
The change includes:
* Update EC_CMD_FLASH_REGION_INFO to accept EC_FLASH_REGION_UPDATE
* Update EC_CMD_VBOOT_HASH to accept EC_VBOOT_HASH_OFFSET_UPDATE
When EC_FLASHS_REGION_UPDATE is specified, EC_CMD_FLASH_REGION_INFO
returns the slot which currently is not hosting a running RW copy.
When EC_VBOOT_HASH_OFFSET_UPDATE is specified, EC_CMD_VBOOT_HASH
computs the hash of the update slot. This hash covers the entire
region, including the signature at the end.
This patch undefines CONFIG_CMD_USBMUX and CONFIG_CMD_TYPEC
for gru to create space.
BUG=b:65028930
BRANCH=none
CQ-DEPEND=CL:648071
TEST=On Fizz, verify:
1. RW_B is old and updated by soft sync. RW_B is activated and
executed after reboot. System continues to boot to OS.
2. RW_A is old and updated by soft sync. RW_A is activated and
executed after reboot. System continues to boot to OS.
Change-Id: I9ece907b764d07ce94054ba27996e048c665a80a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648448
If the PD state machine remains in SRC_DISCOVERY for an extended period
of time, it's likely that a non-PD USB peripheral is attached. In this
case, we don't need to inhibit deep sleep, since we're not likely to
receive PD packets.
This change will cause us to enter deep sleep slightly more
aggressively, not inhibiting deep sleep until source caps are received
or replied with GoodCRC by the port partner. We can accommodate
additional task latency up to this point, since the spec calls for
source caps to be sent up to 50 times before failure.
BUG=b:35582718,chromium:763002
TEST=Test with `sleepmask 1` on kevin.
- Go to S3 with USB-C flash drive plugged, verify `sleepmask` shows 0.
- Go to S3 with zinger + USB C flash drive plugged
- Unplug zinger, verify `sleepmask` shows 0.
- Plug zinger, verify PD negotiates to 20V @ 2A.
- Plug OEM kevin charger, verify same.
BRANCH=gru
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib8e1bc94bdbcfddea004d572edf1ccadc8c8c1ce
Reviewed-on: https://chromium-review.googlesource.com/655919
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reworked suzy-q and suzy-qable all provide Rp, so there is no need for
special detection handling in S5. Also, CONFIG_USB_PD_QUIRK_SLOW_CC_STATUS
is no longer relevant, since we no longer take special action when VBUS
is seen without Rp.
BUG=chromium:737755
BRANCH=None
TEST=On kevin, verify reworked suzy-q and suzy-qable are detected in S5.
Also, verify zinger works in S5 on reef.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I50967bd6415d964a038b2e7d134374132eda11ec
Reviewed-on: https://chromium-review.googlesource.com/656067
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Servo / Suzy-Q related debugging methods is a big challenge
in factory especially after servo debug header is removed.
Expose some information to OS from EC will do a great help
for massive production.
+ expose charge/battery related state to ectool
1. chg_ctl_mode
2. manual_mode
3. battery_seems_to_be_dead
4. battery_seems_to_be_disconnected
5. battery_was_removed
6. disch_on_ac (learn mode state)
BUG=b:65265543
BRANCH=master
TEST=`ectool chargestate param 0x20000~0x20006 get correct state`
Change-Id: Ic2ed38e2eb9def01be29729fa1fe1959eb73fe43
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/646412
Reviewed-by: Shawn N <shawnn@chromium.org>
Minor cleanup to the 'ccd help' command.
Add 'ccd get' as a clearer alias to print the config.
Change CONFIG_CMD_CCDDISABLE to CONFIG_CMD_CCD_DISABLE to indicate
that it's a sub-command for 'ccd'.
BUG=b:65407395
BRANCH=cr50
TEST=manual
ccd -> see clue for 'ccd help'
ccd help -> see 'get' command
ccd get -> prints config
ccd disable -> error (config option isn't defined by default)
Change-Id: Icbcaa178171ca948cfaae58ab1a1e73ab3d95243
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/654380
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
For historical reasons, CCD, reset, and power button control were
scattered around several files. Consolidate the code in more sensible
(in retrospect) places.
No functional changes, just moving code.
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50
Change-Id: Ic381a5a5d0627753cc771189aa377e88b81b155e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/653766
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
SYSTEM_IMAGE_RW_B hasn't been globally treated as a RW copy.
This change makes EC treat it also as a RW copy.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: Iae5a9090cdf30f980014daca44cdf8f2a65ea1f2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656337
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Somewhere this lost a call to ccd_save_config(). Put that back.
Also, make it so 'ccd testlab' prints the current state.
BUG=b:65407184
BRANCH=cr50
TEST=manual with CR50_DEV=1 image
ccd oops
ccd testlab -> disabled
ccd testlab enable
ppresence (or tap power button)
ppresence
ppresence
ccd testlab -> enabled
reboot
ccd testlab -> enabled
ccd lock
ccd -> state=locked
ccd testlab open
ccd -> state=opened
ccd testlab disable
ppresence (or tap power button)
ppresence
ppresence
ccd testlab -> disabled
reboot
ccd testlab -> disabled
ccd testlab open -> acces denied
Change-Id: Iffdd84e8e0df3222b8762638b8a613f146c15f13
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/653765
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Previously, all CCD config commands were their own distinct commands.
This led to accidental side-effects when someone would type 'ccdlock'
thinking it would print the lock state when it would actually lock the
device.
Make them all sub-commands of 'ccd'. So, 'ccd lock', not 'ccdlock'.
Just 'ccd' by itself will print the current config.
No changes to how the sub-commands themselves work.
BUG=b:65407395
BRANCH=cr50
TEST=manual with CR50_DEV=1 build
gpioget # make sure GPIO_BATT_PRES_L=0
ccd help # prints help
ccd lock # lock, because CR50_DEV=1 builds start unlocked
ccd # locked, flags=0, all capabilities default
ccd pass # access denied (we're locked)
ccd reset # access denied
ccd set flashap always # access denied
ccd unlock
ccd # unlocked
ccd pass foo
ccd # flags=2 (password set when unlocked)
ccd set flashap always # access denied
ccd set uartectx unlesslocked
ccd # yes, uartectx permission changed
ccd lock
ccd unlock # fails without password
ccd unlock bar # wrong password
ccd unlock foo # busy
(wait 3 sec)
ccd unlock foo
ccd reset
ccd # no password, flags 0, capabilities all default
ccd open # requires physical presence; tap power or use 'pp'
ccd set uartgsctxecrx unlesslocked
ccd set batterybypasspp ifopened
ccd pass baz
ccd # password set, flag 0, ccdset changes worked
ccd unlock
ccd reset
ccd # uartgsctxecrx back to ifopened, password still set
ccd open baz # still requires physical presence
ccd set opennolongpp always
ccd lock
ccd open baz # no pp required
ccd set unlocknoshortpp unlesslocked
ccd lock
ccd open baz # short pp sequence required (3 taps)
ccd lock
ccd unlock baz # short pp sequence required
ccd open baz # pp not required
ccd set unlocknoshortpp always
ccd lock
ccd testlab open # access denied
ccd testlab enable # access denied
ccd unlock baz
ccd testlab open # access denied
ccd testlab enable # access denied
ccd open baz
ccd testlab enable # requires short pp
ccd # flags 1
ccd reset
ccd # no password, flags=1, caps all default
ccd lock
ccd testlab open
ccd # opened
ccd testlab disable # requires short pp; let it time out
ccd # still opened, flags=1
ccd lock
ccd oops # backdoor in CR50_DEV images to force-reset CCD
ccd # opened, flags=0, all defaults (yes, oops wipes out testlab)
ccd reset rma
ccd # flags = 0x400000, everything but GscFullConsole always
ccd reset # back to flags=0, all default
Change-Id: Ib2905cb7cbeb79a7f4d0fb44151bfd53af361e2e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/653719
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Currently, the Cr50 state machines (EC, AP, RDD, bitbang, etc.) manage
their own enabling and disabling of the ports (UART, SPI, etc.) This
is tricky because the rules for when ports should be enabled are
non-trivial and must be applied in the correct order. In additionl
the changes all need to be serialized, so that the hardware ends up in
the correct state even if multiple state machines are changing
simultaneously.
Consolidate all of that into chip/g/rdd.c. The debug command for it
is now 'ccdstate', which just prints the state machines. This will
allow subsequent renaming of the 'ccdopen', etc. commands to 'ccd
open', etc.
Also include UART bit-banging into that state which must be
consistent. Previously, it was possible for bit-banging to leave UART
TX connected, instead of returning it to the previous state.
Use better names for CCD config fields for UART. I'd had them backwards.
BUG=b:62537474
BRANCH=cr50
TEST=manual, with a CR50_DEV=1 image
1) No servo or CCD
Pull SERVO_DETECT low (disconnected)
Pull CCD_MODE_L high (disabled)
Pull EC_DETECT and AP_DETECT high (on)
Reboot. RX is enabled even if cables are disconnected so we buffer.
ccdstate -> UARTAP UARTEC
Pull EC_DETECT low.
ccdstate -> UARTAP
Pull EC_DETECT high and AP_DETECT low.
ccdstate -> UARTEC
Pull AP_DETECT high.
ccdstate -> UARTAP UARTEC
2) Servo only still allows UART RX
Pull SERVO_DETECT high (connected).
ccdstate -> UARTAP UARTEC
3) Both servo and CCD prioritizes servo.
Pull CCD_MODE_L low (enabled).
ccdstate -> UARTAP UARTEC
Reboot, to make sure servo wins at boot time.
ccdstate -> UARTAP UARTEC
Bit-banging doesn't work when servo is connected.
bitbang 2 9600 even -> superseded by servo
bitbang -> disabled
ccdstate -> UARTAP UARTEC
4) CCD only allows more ports and remembers we wanted to bit-bang
Pull SERVO_DETECT low.
ccdstate --> UARTAP+TX UARTEC+BB I2C SPI
bitbang 2 disable
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI
Reboot and see we don't take over servo ports until we're
sure servo isn't present.
ccdstate --> UARTAP UARTEC (for first second)
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI (after that)
5) Bit-banging takes over ECTX
bitbang 2 9600 even
bitbang -> baud rate 9600, parity even
ccdstate -> UARTAP+TX UARTEC+BB I2C SPI
bitbang 2 disable
ccdstate -> UARTAP+TX UARTEC+TX I2C SPI
6) Permissions work. Allow easy access to full console and ccdopen:
ccdset OpenNoTPMWipe always
ccdset OpenNoLongPP always
ccdset GscFullConsole always
Default when locked is full AP UART EC RO, no I2C or SPI
ccdlock
ccdstate -> UARTAP+TX UARTEC
No EC transmit permission means no bit-banging
bitbang 2 9600 even
bitbang -> disabled
ccdstate -> UARTAP+TX UARTEC
But it remembers that we wanted to
ccdopen
ccdstate -> UARTAP+TX UARTEC+BB I2C SPI
bitbang 2 disable
ccdstate -> UARTAP+TX UARTEC+TX I2C SPI
Try turning on/off permissions
ccdset UartGscTxECRx always
ccdlock
ccdstate -> UARTAP+TX UARTEC+TX
No read means no write either
ccdset UartGscRxECTx ifopened
ccdlock
ccdstate -> UARTAP+TX
ccdopen
ccdset UartGscRXAPTx ifopened
ccdlock
ccdstate -> (nothing)
Check AP transmit permissions too
ccdopen
ccdset UartGscRxAPTx always
ccdset UartGscTxAPRx ifopened
ccdlock
ccdstate -> UARTAP
Check I2C
ccdopen
ccdset I2C always
ccdlock
ccdstate -> UARTAP I2C
SPI port is enabled if either EC or AP flash is allowed
ccdopen
ccdset flashap always
ccdlock
ccdstate -> UARTAP I2C SPI
ccdopen
ccdset flashec always
ccdset flashap ifopened
ccdlock
ccdstate -> UARTAP I2C SPI
Back to defaults
ccdoops
Change-Id: I641f7ab2354570812e3fb37b470de32e5bd10db7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/615928
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Currently, only usb_pd_protocol.c cares about the actual ccd mode
(disabled/partial/enabled). Everything else just cares whether it's
enabled or not. So promote the boolean ccd_is_connected() from
board/cr50 up to chip/g, and rename it to ccd_ext_is_enabled() to
match the new nomenclature (since 'CCD' itself is now too overloaded).
This will make it easier to handle CCD state directly in board/cr50
after we split it from common/case_closed_debug.c
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50; make sure USB endpoints still work
Change-Id: Ic3df7467bfe29f1c5d7060cac1309a1f0e090d9e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648212
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
CCD_CHANGE_HOOK should use CONFIG_CASE_CLOSED_DEBUG_V1.
All boards which use chip/g either use both CONFIG_USB_SERIALNO and
CONFIG_CASE_CLOSED_DEBUG or neither of them, so just depend on
CONFIG_USB_SERIALNO.
This is in preparation for making common/case_closed_debug refer only
to the usb_pd_protocol version (with mode=disabled/partial/enabled),
and cr50 will have its own version (with only enabled/disabled, and
tied more closely to CCD config).
No functionality changes.
BUG=none
BRANCH=cr50
TEST=make buildall -j; boot cr50 and see change hook called
Change-Id: I1985c8c48c1a85fed4549402a7b47b8a9cf135d7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648067
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
LPC area for sensors support 3 sensors:
up to 2 accelerometers and 1 gyro.
If only 1 accelerometer is present, only the first accelerometer slot is
populated.
If there is no gyro, the gyro slot is not populated.
Add tests and remove assumption in the code to be sure the rules above
are enforced.
BRANCH=none
BUG=b:64232053
TEST=compile, check eve is still working.
On soraka:
ectool motionsense odr 2 10000
ectool motionsense
output matches:
grep . /sys/bus/iio/devices/*/in_*_raw
Change-Id: Ifd791a6fa89d94bf91ad1a65b8987f69bada801e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/639319
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Allow reporting that keyboard backlight doesn't exist even when the code
is compiled in. Useful if there are multiple device models that should
share firmware.
BUG=b:64705535
BRANCH=none
TEST=none
Change-Id: I9c1fc370aedf66ef856a571f73831095d27e3d39
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/633926
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
we need to properly restart the anx3429 after a firmware update.
simply initializing the chip doesn't seem to get it to reload its
firmware - at least not the portion of the chip that implements the
firmware version register. so, we explicitly power down and reset the
chip before reinitializing it to force it to run the new firmware.
the chip also needs a 10ms "off" time so the reset is properly seen by
the chip, so i did a light refactoring of the code paths that reset
the anx3429.
TEST=used 2 different firmware blobs and verified it switches between
them during software sync.
BRANCH=none
BUG=b:35586895
Change-Id: I967898dd906f21bdc5bc4ce9c1dff9f873d198c1
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/631976
For some boards, the control lines to the charging port controller are
all tied to a power rail. In essence, this leaves the ILIM_SEL as the
only signal able to be controlled, which means that we only support
CDP/SDP.
This commit adds a new CONFIG_* option which describes this.
CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
Additionally, some cleanup is made to not always assume the number of
smart power ports.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I080ccd67ffc20ccccf1e6b33a3cf9374a6b70ad6
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/634274
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently, chip/g uses jtag_pre_init() to do some chip
pre-initialization that isn't actually related to JTAG. This has been
harmless, but it's currently the only chip which actually does "JTAG"
pre-init, and we'd like to get rid of that. So, move that
functionality to a new optional chip_pre_init() function.
BUG=chromium:747629
BRANCH=cr50
TEST=make buildall
boot cr50
make all dis; confirm chip_pre_init() is called early in <main>
Change-Id: I3cae0747ab0c3cc974fce9f108947207b38e035f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/629876
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the board level TCPC run as an init hook it will frequently
lead to an EC reset when we are trying to recovery a disconnected
battery, potentially even a reboot loop with the most unlucky
timing.
If we instead call it from the pd_task before tcpc_init is called
then the board init hook can stall the pd_task init until the
battery is out of disconnect mode, or giving up after 2 seconds
in case the battery never seems to recover.
This accomplishes two goals: ensure the PD chips are not reset until
the battery is out of disconnect and delay start of the pd_task
(and PD negotiation) until the battery is out of disconnect state.
This change was done in the Eve FW branch. Pulling it into TOT so it
can be used for other boards that have the same
issue. https://chromium-review.googlesource.com/c/592716. The change
to wait for the battery to be out of disconnect mode is in the board
specific board_tcpc_init() function and so will be in subsequent board
specific CLs.
BUG=b:63957122
BRANCH=none
TEST=manual Verify that 'make buildall' is successful.
Change-Id: I14c3dbb89cdc05fa9231fbe9db2e1de19fa941b6
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/627114
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to satisfy factory testing requirements we need to
boot a bare board with just an AC adapter without requiring
a power button.
However we also don't want to always allow booting of the
battery is present but cut-off (which will indicate BP_NO so
we can't use the existing battery_is_present function) or has
critically low level as it may not immediately boot.
To accomplish this add a function that allows the board to
specify a custom "hardware presence" for the battery that is
separate from the battery presence check.
This CL is taking a change done for Eve and pulling into TOT so it can
be used for other projects that have the same
requirements. https://chromium-review.googlesource.com/c/582544
BUG=b:63957122
BRANCH=none
TEST=manual
Change-Id: Ib1dc4f659adbf0eebd3dc8c3c61b39b8fa36cb4a
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/627113
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this makes the PD_CONTROL_DISABLE subcommand of EC_CMD_PD_CONTROL port
specific like all the other subcommands already are.
the only place depthcharge uses PD_CONTROL_DISABLE is in anx7688.c and
that code already passes the correct chip ID along, so this will not
affect the current use case. ectool already does the right thing as
well.
TEST=used ectool to verify each port can be disabled independently.
BRANCH=none
BUG=b:64956885
Change-Id: I6514eb300793b8958ed78846298ec5b95f78e6dc
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/616259
Reviewed-by: Shawn N <shawnn@chromium.org>
Use the previously introduced TPM logging framework to log TPM reset
events. The two lowest data field bits are used to communicate the
type of reset passed to tpm_reset_request(),
BRANCH=cr50
BUG=b:63760920
TEST=with the upcoming patches verified that TPM initialization is
logged as expected
Change-Id: Ic0874723ec6df616a8237b036542398b29fe5ccc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/620113
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
SVr4/4.3BSD/C89/C99 use a return value of size_t. To
make interaction with code running on both userland
and on the EC easier, change our function prototype
to return size_t as well.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BRANCH=none
BUG=none
TEST=make buildall -j works
Change-Id: I0f097c4d0db4232d888e1d54e6c1d22f4859a112
Reviewed-on: https://chromium-review.googlesource.com/618269
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
A common failure condition on the i2c bus is when the master
unexpectedly stops clocking the bus while the slave is driving the SDA
line low. In this case the master is not able to issue Stop or Start
sequences, which makes the bus unusable.
Good slave controllers are able to detect this condition and recover
from it by removing the pull down from the SDA line. This patch adds
this capability to the g chip i2c slave controller.
A new timer function is created which samples the SDA line twice a
second. If it detects that SDA is low in two consecutive invocations
and the number of i2cs read interrupts has not advanced, it decides
that the "hosed slave" condition is happening and reinitializes the
i2c driver, which removes the hold from the SDA line.
Even though the state of the SDA line is supposed to be accessible
through the I2CS_READVAL register, it in fact is not, reads always
return zero in the SDA bit. To work around this a GPIO (port 0, bit
14) is being allocated to allow to monitor the state of the line, it
is multiplexed to the same pin the SDA line uses.
When the AP is in low power modes the SDA line is held low, this state
should not trigger i2c reinitializations.
CQ-DEPEND=CL:616300
BRANCH=none
BUG=b:35648537
TEST=connected H1 on the test board to an I2c master capable of
stopping clocking mid byte. Observed that the existing code would
just sit in the "hosed" state indefinitely. The code with the fix
recovers from the condition (drives the SDA line high) 500ms to
1s after the failure condition is created.
Change-Id: Iafc7433bbae9e49975a72ef032a923274f8aab3b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/614391
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
A subsequent CL will massively refactor the device state machines.
Add the helper functions which will be used by that CL, so that
the refactoring touches fewer files.
No change in functionality.
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50 with a CR50_DEV=1 image
Change-Id: I3499d45e93fa15b6de9c04ce398d1c5bfbbc01e9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/616300
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This way, when HOOK_CCD_CHANGE triggers, the debug message is printed
before any of the effects of the change due to other hooks.
No effect on the rest of the code.
BUG=none
BRANCH=cr50
TEST=manual in CR50_DEV=1 image
ccdlock
ccdoops
"CCD change hook called" should be seen before "Enabling I2C" or
"Disabling I2C" messages.
Change-Id: I2e083b70fe8ac3938abc56e14b5e50fe9e237752
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/616179
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
In the SRC_READY state, we'll only request sink caps if we haven't
received them yet and only if its the first transition to the state.
However, we also don't send any PD traffic in that state if there's an
incoming message in order to prevent a collision. This could create a
scenario where upon entry to the SRC_READY state, a message is incoming.
When this occurs, we never request the sink caps.
This commit simply removes the condition that we may only request sink
caps on the first transition to the SRC_READY state.
BUG=b:64037926
BRANCH=gru
TEST=Flash kevin; Connect to a DR port partner; Verify that sink caps
are requested even after the first transition to the SRC_READY state.
Change-Id: I6bc9ad01d45e6584a7a14b28806ae4872a22d98f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/611320
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT is defined for a board, as
its name implies, the board can source a higher current if there is
only one port acting as a source.
This commit fixes an issue with selecting the right source capability
message to advertise. charge_manager_get_source_pdo() was simply
checking if there was more than one sink connected, instead of checking
if there were any *other* sinks connected. In the event that a sink
was connected to a different port, we would advertise the max source
PDO.
BUG=b:64037926, b:35577509
BRANCH=gru,eve,reef
TEST=Connect sink to port 1. Connect a AMA to port 0 that claims that
VBUS isn't necessary. Start sending source caps, verify that the max
PDO is not being advertised in the source caps.
Change-Id: Ie4145ecaf98d5b9070ad3e8b139e5653685fa801
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/610479
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Allow TPM to log events in a circular buffer through tpm_log_event().
Logs can be retrieved through a new vendor command
VENDOR_CC_POP_LOG_ENTRY.
BUG=b:63760920
TEST=On eve, store TPM logs through 'logentry' cr50 console command,
verify logs are fetched correctly through 'trunks_send --pop_logentry'.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Idbc405728c0ba68078447fb59717d6115830e3d8
Reviewed-on: https://chromium-review.googlesource.com/599352
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In the field, we want to update touchpad FW using the same USB
update protocol as the main EC FW.
To distinguish between EC FW update and touchpad FW update, we
use a virtual address, defined by CONFIG_TOUCHPAD_VIRTUAL_OFF,
that does not map to anything on the EC chip.
Also, this will allow us to verify hashes of each block of the
flashed touchpad firmware, so that we can ensure its integrity
before flashing it into the touchpad. A stub is implemented in
update_fw.c:contents_allowed.
BRANCH=none
BUG=b:63993173
TEST=With follow-up CLs, ./usb_updater2 -p 144.0_2.0.bin
Change-Id: I4de1d7d138fc01fe1552a4173c8ef208ecb834a7
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/593373
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
If board selects both CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF and
CONFIG_HIBERNATE, then CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF should
be given higher preference when deciding what action to take in case
of critical battery.
This is necessary on boards where components like H1 chip could be
consuming more power than is healthy when the battery is already
critically low, depleting it to dangeriously low voltage levels faster
than it should.
(Reference: https://chromium-review.googlesource.com/582543)
BUG=b:64460667
BRANCH=None
TEST=Manual testing to ensure that EC cuts off battery when it is
critically low instead of hibernating on soraka.
Change-Id: I6efacd7206199ca19f1073296b113b6cf18ec655
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/605014
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This mostly adds a bunch of comments, but does make a few changes to
the code:
1) The devices console command now prints both the current device
state and the last known state.
2) servo_state_unknown() also checks if we're bit-banging the EC UART,
since that could also cause EC_DETECT to go high.
BUG=none
BRANCH=cr50
TEST=make buildall; use 'devices' command
Change-Id: I73e7524545ef49494eb36155b99f4042c1fd466d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/602695
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
