Commit Graph

4 Commits

Author SHA1 Message Date
Shawn Nematbakhsh
d008477824 cortex-m*: Save panicinfo on non-exception panics
Make non-exception "software" panics such as stack overflow and assert
failure save a panic log. Log the panic type in r4, and misc. panic data
in r5 so that panic reasons can be distinguished.

BUG=chrome-os-partner:36744
TEST=Manual on samus_pd. Run 'crash divzero' then 'panicinfo' after
reboot. Verify that panic info is printed with "r4 :dead6660". Trigger
stack overflow, verify that panic info is printed with "r4 :dead6661".
BRANCH=Samus

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I5f7a8eb0a5c2ac5799d29bb241deb24fabf38f68
Reviewed-on: https://chromium-review.googlesource.com/249912
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
2015-02-18 04:53:51 +00:00
Vincent Palatin
e2355ff432 cortex-m0: optimize out unused assembly helpers
Put each assembly helper function in its own .text.__funcname__ section,
so the linker can remove the unused ones.

Also remove a few entrypoints used only by deprecated ABIs.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=samus
BUG=none
TEST=make buildall
check the firmware size and see we are saving 88 bytes on Zinger.

Change-Id: I6714da671c3449220652780d47993d6c919c331c
Reviewed-on: https://chromium-review.googlesource.com/240582
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
2015-01-14 21:50:03 +00:00
Vincent Palatin
6473343075 better unhandled exception panic without runtime
On panic, reboot properly the CPU rather than just jumping to the reset
vector as that might lead to some incorrect initializations.

Properly plug the div by 0 to the panic handling.

Add a small trace if the debug output is activated.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:29840
TEST=add adhoc code triggering a data abort and see the firmware
printing a trace, then rebooting immediatly in a working state.

Change-Id: I1d5a98d9113c8ae08e05588a40f941d1ed22cebe
Reviewed-on: https://chromium-review.googlesource.com/206268
Reviewed-by: Vic Yang <victoryang@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
2014-07-03 02:56:52 +00:00
Vincent Palatin
0f73a129b4 Add Cortex-M0 core support
The Cortex-M0 core is based on ARMv6-M instruction set rather than
ARMv7-M as Cortex-M3 and M4.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=run console on STM32F072,
and pass all available unit-tests on target.

Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e
Reviewed-on: https://chromium-review.googlesource.com/188982
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
2014-03-11 05:52:41 +00:00