The decision on whether to ramp (and how high) depends on the quirks of
charger identification, so move the decision out of board, into the
drivers that implement usb_charger.
Also, rename CONFIG_CHARGE_RAMP to CONFIG_CHARGE_RAMP_SW, to better
contrast with the existing CONFIG_CHARGE_RAMP_HW.
BUG=None
TEST=Manual on kevin, verify ramp occurs when port plugged into Z840
workstation.
BRANCH=None
Change-Id: I5b395274133837a18a4f4ac34b59b623287be175
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/702681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a PERSO_AUTH appid to sign data passed through the
AUTH mn50.
Add a signer command to start and generate signatures.
Clean UART init to avoid spurious nonprinting characters
that will contaminate the siugnature.
BUG=b:36910757
BRANCH=None
TEST=generates signature for uart and spi
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I5fc3c4ee34898421060b57b774a09734f6a1bae5
Reviewed-on: https://chromium-review.googlesource.com/670984
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Turn on FORCE_CONSOLE_RESUME and also shuffle around
the context to ensure alphabetical order.
BUG=b:67379662
BRANCH=none
TEST=manually on Scarlet rev1: put AP in suspend mode,
verify EC console still works, and confirm EC goes into
low power idle mode by EC console command 'idlestats'.
Change-Id: I2563e6ed4fdb47123912932ad8ba9172b0c9c13c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/702918
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Boards that use charge_manager have identical implementations of
typec_set_input_current_limit() and pd_set_input_current_limit(), so
move these functions to charge_manager.
BUG=b:67413505
TEST=`make buildall -j`, also verify that fizz continues to power-on and
boot AP, in both protected and unprotected mode, with barrel jack power
and with zinger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I99a5314d02c4696db944c0f8ac689405f4f1f707
Reviewed-on: https://chromium-review.googlesource.com/701412
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
CONFIG_CASE_CLOSED_DEBUG (CCD functionality implemented by EC) is no
longer used in conjunction with CONFIG_USB_POWER_DELIVERY, and the
common routines are only used by one board.
BUG=chromium:737755
BRANCH=None
TEST=`make buildall -j`
Change-Id: Idc3d2fccef6cbec2af786cef634d752a02a0e859
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656315
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This enables pull-down on F_DIO1 (SPI MISO), and F_DIO0 (SPI MOSI),
whenever the EC is not doing SPI flash transactions. This avoids
floating SPI buffer input (MISO), which causes power leakage.
BRANCH=none
BUG=b:64797021
TEST=Flash soraka, check output of rw .b 0x400C3029 is 0x80
Check that U58 (SN74LVC244ARWPR) leakage drops from 1.2 mA to 0.
TEST=1. flashrom from host to EC spi flash using servo
2. flashrom from host to EC spi flash using suzyq
3. flashrom from device to EC spi flash
4. EC SW sync
Change-Id: I5ac22142f6a1a5b1c31d6ae272ed7516a112f29e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/701717
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch undefines CONFIG_SYSTEM_UNLOCKED, which forces the system
to be unlocked, and defines CONFIG_USB_PD_COMM_LOCKED, which enables
PD only if EC is in RW. With this change, if SW write-protect is
enabled, the system will stay in G3 until 50W or more power is
supplied.
BUG=b:38462249
BRANCH=none
TEST=Lock Fizz and boot it on type-c adapter. Verify RW image is
successfully verified and executed.
Change-Id: Id8255c5c8e6af93bda3fd4de079008561f46e14c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/558377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A couple of bugs have crept in with the latest series of patches:
- the board ID value endianness does not have to be changed
- the test RMA server public key value is wrong
BRANCH=cr50
BUG=b:67007905
TEST=the generated challenge is now accepted by the server, and the
generated auth code matches between the server and the Cr50.
Change-Id: I18f413ab0bcc14d9cc50b115ac3784fdfcd5851c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/700798
Reviewed-by: Michael Tang <ntang@chromium.org>
Runtime S0ix results in SLP_S0 signal being toggled continuously
resulting in an interrupt storm on the EC. In order to avoid this,
enable SLP_S0 power signal only when host indicates intent to enter
S0ix and disable when host exits from S0ix.
BUG=b:65421825
BRANCH=None
TEST=Verified that runtime S0ix no longer results in interrupt storm
on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0
using powerindebug.
Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the battery gets to returns the FULL flag, bd99956 charging is
disabled and battery learning is enabled. This state will remain until
the FULL flag is cleared by the battery. The original fix had this
level at 97%, but on the various batteries tested this appears to
happen at 95%. The CONFIG_BATTERY_LEVEL_NEAR_FULL allows an adjustment
for this level and is only used for LED states.
BUG=b:64192049
BRANCH=None
TEST=Manual Let system charge to 100% when FULL flag is set in the
battery, verified the LED was in correct state. Then let battery drain
until the FULL flag is clear and observe that the battery requests
charge current. The LED stays in the expected full charge state.
Change-Id: I74d26abd5d8021bcfacdc3a4c3d4baba6a978bca
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/693386
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace structure member "level" in power_signal_info with "flags".
"level" has been used on all boards to indicate active-high or
active-low levels. Addition of "flags" allows easy extension of
power_signal_info structure to define various flags that might be
applicable to power signals (e.g. "level"). Going forward, additional
flag will be added in follow-up CLs.
Also, provide a helper function power_signal_is_asserted that checks
the actual level of a signal and compares it to the flags level to
identify if a power signal is asserted.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679979
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Enable necessary flags for the Cr50 to start supporting RMA
authentication. This also requires that the RMA server public key
definition is split between the actual and test. Even though they are
the same at this time, the actual public key would be defined in the
new future and it would be different from the test key.
BRANCH=cr50
BUG=b:65253310
TEST=make buildall -j passes. More tests were conducted on the full
patchset.
Change-Id: I5a3f9d8c71374d78192e3f0a2752391b842da962
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/691554
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To aid with severe flash space shortage, let's enable
CRYPTO_TEST_SETUP only if CR50_DEV is set to a value exceeding 1.
board/mn50/board.h used to define CR50_DEV without any value assigned
to it, correct this so that the check in dcrypto.h works when mn50 is
built.
BRANCH=cr50
BUG=b:65253310
TEST=compiling with CR50-DEV=1 vs CR50_DEV=2 saves more than
17.5 Kbytes per RW image.
Change-Id: Ic77fa45b1a8f7631efa91c08e63438d412196eed
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690993
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, when CCD is opened, there is no way to disable the EC
and/or AP UARTs. But if there is some problem with the EC and/or AP,
and their UARTs are spamming interrupts, it can make debugging more
difficult.
If servo detection malfunctions, then CCD may drive the ports and
interfere with servo.
Add a new ccdblock command to disable the AP UART, EC UART, or any
ports shared with servo, until the next cr50 reboot.
BUG=b:65639347
BRANCH=cr50
TEST=manual with CR50_DEV=1 image, AP/EC powered on, suzyq connected
ccdblock --> (none)
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI
ccdblock AP on
ccdstate --> UARTEC+TX I2C SPI
ccdblock EC on
ccdstate --> I2C SPI
ccdblock -> AP EC
ccdblock AP off
ccdstate --> UARTAP+TX I2C SPI
ccdblock EC off --> (none)
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI
ccdblock SERVO on
ccdstate --> UARTAP UARTEC
ccd lock
ccdblock AP on --> access denied
Change-Id: I3dcc8314fc98a17af57f2fe0d150ecd1a19ccf52
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/693041
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
On proto3, PMIC isn't powered on POR, thus board_pmic_init fails.
With this change, EC waits until AP power is ready before it
notifies HOOK_CHIPSET_PRE_INIT where PMIC will be initialized.
When AP power is ready, PMIC should be ready as well.
BUG=b:65839247,b:64944394
BRANCH=none
TEST=Run reboot [/cold/ap-off] command on BJ and Type-C.
Change-Id: I7e7e07b5acf92167584966ded0a5f14fb6b04f0b
Reviewed-on: https://chromium-review.googlesource.com/672152
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fizz EC verifies RW by itself and jumps to RW before AP boots.
If this fails, the system needs recovery. Since EC isn't
capable of showing any info on a display, we use the power
LED to inform the user.
BUG=b:66914368
BRANCH=none
TEST=Make Fizz fail RW verification. Observe LED illuminates
in red.
Change-Id: Ia07de60a316b40e74b1917903996d78750b4ae43
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/683218
This patch makes the LED blink to alert the user when there is
not enough power to boot the system.
This patch also changes minimum boot power to 50W. It's common
for all SKUs.
BUG=b:37646390
BRANCH=none
TEST=Power Fizz with 15W, 45W, 60W chargers. Verify LED blinks as
expected.
Change-Id: If269897f5022f6cba80f37ce03e2315cfb2cf504
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/682876
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We need to response EC ACPI device orientation command or
keyboard/trackpad didn't work on OS image version R58 and
after.
BRANCH=none
BUG=none
TEST=keyboard and trackpad work on R58 and after.
Change-Id: I49f9c90e73a5e529eb228169e4148f4dcd4a45e6
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/689715
Reviewed-by: Shawn N <shawnn@chromium.org>
The current stm32 rtc driver only uses RTC_TR and RTC_SSR.
So we son't be able to use rtc for applications which need
time > 24 hours.
To support such applications, this patch adds operations
for RTC date register (RTC_DR).
BUG=b:63908519
CQ-DEPEND=CL:666985
BRANCH=none
TEST=manually with 'ectool rtcset/rtcset' and '/sys/class/rtc/rtc0',
verify the conversion between calendar time and Unix epoch time works.
Change-Id: Iacd5468502e4417a70880d7239ca5e03353d9469
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/659337
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
1.Add LG battery for Santa and Porbeagle.
2.Santa LG battery manufacture name is same as BATTERY_LGC011, so use
device name to recoginze Santa LG battery.
3.These two battery have different process to get FET status, make
sure battery not use this process is before BATTERY_LGC15 to separate
these two different process.
BRANCH=none
BUG=b:65426428, b:64772598
TEST=Make sure battery can cutoff by console "cutoff" or "ectool cutoff"
and resume by plug in adapter.
Change-Id: I7095b9d0915fb4d39aa6c9f8c8751aa22941e938
Signed-off-by: David Huang <David.Huang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/674472
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch raises the max power for a type-c adapter to 60W (20V @3A).
We can't go above the regular cable capacity (3A) until we add e-marked
cable detection.
BUG=none
BRANCH=none
TEST=Boot Proto3 on Zinger. Observe 60W (20V @3A) is selected.
Change-Id: I9670d710e363c7db1136a7ce7a7f8401b0ad8240
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679210
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In this CL, we add the follow changes for npcx7 evb board:
1. Add comments in the build.mk to indicate how to set
CHIP_VARIANT for EVBs which use different npcx7 ec.
- npcx7m6f : 144 pins (default)
- npcx7m6g : 128 pins
2. Turn on the eSPI host interface as default in board.h
BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
Change-Id: Ib926e8596a09a28f547c35a0256be2aa394f9a36
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/674887
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The hash test code memory management is somewhat loose: it does not
clean up allocated buffer, but then uses it to check for presence of
the previously created handles, which can result in false positives.
Let's zero the buffer each time it is allocated and let's use
hash_test_db.contexts as the indicator if the buffer is allocated or
not.
BRANCH=cr50
BUG=none
TEST=ran ./test/tpm_test/tpmtest.py, observed rsa tests pass.
Change-Id: Iad4b4e2662fc7266ee6f556f6ddfd0051e7172d7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/665321
Reviewed-by: Shawn N <shawnn@chromium.org>
Based on measurements, Samus can pull more current than desired, even
taking into account the existing INPUT_CURRENT_LIMIT_OFFSET_MA
adjustment. Decrease the programmed current limit by an additional
factor, determined by taking the worst-case power measurements across 15
different Samus devices, to ensure that Samus never pulls more current
than desired.
BUG=chrome-os-partner:55297
BRANCH=samus
TEST=Verify with debug prints that curr_lim_ma becomes 256 when
negotiated current limit is 500mA and curr_lim_ma becomes 2556 when
negotiated limit is 3000mA.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6912d987c5a519f55a831698873a69c4cac817b8
Reviewed-on: https://chromium-review.googlesource.com/684696
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Fizz has an over current control system. There are two FETs
connected to two registers: PR257 & PR258. They control
the max input current as follows:
PR257, PR258
For 4.62A (90W BJ adapter), on, off
For 3.33A (65W BJ adapter), off, on
For 3.00A (Type-C adapter), off, off
BJ adapters are distinguished by reading GPIO71.
This patch also removes ISL9238 driver and ramping code. The
charger chip has been removed from the board since proto2.
BUG=b:65013352
BRANCH=none
TEST=Boot Fizz Proto3 on BJ and Type-C.
Change-Id: I32c2467f4ab23adf3f9313a03914d74d64a722df
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/668119
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Prepare the future and return a WebUSB descriptor to be able to use the
dongle from this website.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=twinkie
BUG=none
TEST=manual: enumerate WebUSB descriptors with lsusb and connect to
a WebUSB page in Chrome R61+.
Change-Id: I6a36538667ac114fc4b40cb87b2d6e946e265c4d
Reviewed-on: https://chromium-review.googlesource.com/677285
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Kionix Accel does not have FIFO, enable force mode for it.
Chrome needs sensor for screen orientation, set to to 10Hz
in S0 in the EC.
BRANCH=none
BUG=b:62029360
TEST=none
Change-Id: I5545580f2073e9d1145bd86cfcd594164119cae7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675575
Tested-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
The TCPC interrupts were setup, but they weren't enabled yet. This
commit enables the interrupts.
Additionally, a "tcpcdump" debug command is added. This can be removed
later or expanded upon to be more generic.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that we respond to TCPC alerts.
Change-Id: Iba9523cbfb96a570b76e7bdc0ba21dd782854f24
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670063
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch makes LED pulse using deferred call to save RAM and
CPU cycles.
This patch also adds led_alert API. It blinks LED as a warning.
BUG=b:37646390
BRANCH=none
TEST=Verify LED on in S0, pulse in S3, and off in S5.
Run 'led alert' command.
Change-Id: I8c61f91f095eed562d2ee9582868879241df626f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675749
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Just setting the global VRMODECTRL register is not enough to disable
the effect of SLP_S0# signal. Each VR control register needs to be set
correctly to ignore the effect as well. However, disabling VR decay on
SLP_S0# assertion by default results in additional power consumption
during S0ix. In order to prevent this, VR decay on SLP_S0# assertion
needs to be enabled and disabled dynamically as follows:
1. By default on EC boot, PMIC will be initialized to disable VR decay
on SLP_S0# assertion.
2. When host indicates intent to enter S0ix, EC will enable decay of
VRs on SLP_S0# assertion.
3. When host exits from S0ix and updates the intent to no longer enter
S0ix using host command, EC will disable decay of VRs on SLP_S0#
assertion.
actual SLP_S0# assertion because PMIC seems to honor the setting only
at SLP_S0# assertion and not if it is already asserted.
BUG=b:65732924
BRANCH=None
TEST=Verified with this change that the failing Lux device is stable
for a long time even with runtime S0ix.
Change-Id: I9c5afb408694b3b467e85dcea723f7574bc639c1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/674034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to get a Twinkie firmware image with the regular Twinkie sniffer
firmware in the RO partition and a firmware behaving as a USB PD sink in
the RW partition, I had created the (questionable) build_rw_variant bash
script.
Now the EC build can do this natively, so remove the script and the
dedicated task list and use conditional task declaration in the
ec.tasklist.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=twinkie
BUG=none
TEST=build the former firmware with './board/twinkie/build_rw_variant',
build the new one with this patch and 'make BOARD=twinkie' -j,
compare the 2 resulting binaries, they are identical.
Change-Id: I3adb24e2c2825e5bd6f43a7440f829efd70038cc
Reviewed-on: https://chromium-review.googlesource.com/677284
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When battery is at critical charge level, reject charge port disable
request. Since battery is not able to provide enough power to the EC
on boot, we should not cut off our input power, regardless of
dual-role determination or other charging policy.
(Reference:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/351224)
BUG=b:64703097
BRANCH=None
TEST=make -j buildall. Verified that both right and left port are
able to boot the EC up successfully. No reboot loops observed in
critical battery conditions.
Change-Id: I098083036388783c0975ac772da3a3412895e26f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675586
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Vbus adc channel was defined as 0 in the enum, however, we don't
actually have a Vbus ADC channel, therefore it should be defined as -1.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that when charge manager tries to read the
Vbus voltage, the EC doesn't panic due to a non-existing channel.
Change-Id: I53dd3259afc7ae76f587e5b7925ce2f9daa06402
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670123
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit enables the PSL pins for zoombini. Previously, we were
initializing the PSL_OUT pin to high, but it actually turns out that
setting the output from a 0 to a 1 indicates that the firmware wants to
remove Vcc1. This caused the EC to not boot up. This commit removes
the improper initialization of the GPIO and additionally sets up the
hibernate wake pins accordingly such that they can be used by the PSL
glue logic.
BUG=b:65647213
BRANCH=None
TEST=Flash zoombini without rework. Verify board comes up okay.
TEST=Enter `hibernate` on console; Verify board goes to sleep. Verify
that each hibernate wake pins wakes up the board successfully.
Change-Id: Ife1b82eec7957b44bbe409cdeba9c3972168812f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670062
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The keyboard config was the old chrome OS keyboard, but it should be the
new one introduced in April of this year.
Additionally, change KSO2 inverted to be push-pull instead of open
drain. This was causing the entire row to not be detected.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that every key on the keyboard is detected.
Change-Id: I408739eed84f06bd9a2df5a9053c75859f8aaa0b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670061
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The LEDs were on when they were intended to be off. This commit just
inverts the duty cycles.
BUG=None
BRANCH=None
TEST=Flash zoombini. Verify all LEDs are off. Plug in battery, verify
that Red LED is on.
Change-Id: I78e2bce45603fd223ebaeacb024a210c5db70123
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670060
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This is used for factory test with following command
1. ectool command
ectool led power query
ectool led power green=100
ectool led power red=100
ectool led power amber=100
ectool led power off
ectool led power auto
2. console command
led debug >> enter debug mode
led green
led red
led amber
led off
led debug >> exit debug mode
BUG=b:65651340
BRANCH=master
TEST=`ectool ...` works good
Change-Id: Icb87e479075d90f509d60121a3e1df0afe66d41f
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/666418
This change makes the power LEDs pulse using PWM.
S0: solid green.
S3: pulsing amber (= mix of green and red)
S5: off
BUG=b:64975836
BRANCH=none
TEST=Verify LED behavior described above on Proto3
Change-Id: I696cf8279dd762236b7b7f000a316820d58916bf
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/669773
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
